From patchwork Wed Jun 10 08:08:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 1306634 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=hg4s5Qkt; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49hfkY72Rcz9sRR for ; Wed, 10 Jun 2020 18:08:20 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DBCEB388F062; Wed, 10 Jun 2020 08:08:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id 6E641388F062 for ; Wed, 10 Jun 2020 08:08:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6E641388F062 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kito.cheng@sifive.com Received: by mail-pj1-x1029.google.com with SMTP id jz3so548213pjb.0 for ; Wed, 10 Jun 2020 01:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=LOnPpnuMKkccMrLHa9CGSbvxkJcyPXIgAVNGagVwJaU=; b=hg4s5Qktk8tZ9abTdmkV5wO7Ard9Q/crCPOhXD5oeAuEUhdY/fe6vD+8/DcrIEjm8e kee9UvpHbIc84pnLVrSpkxIXrxB9ppkFea9xToVunUH6QUXEuHKKzi6UgqUhWsKTF7RJ 7K/th5w89V2TJenQxjWtZdANFWLlOeoszrceGr2uAaw2WrKRpzpi6+qXiC+OPIlASQRQ LURP47mbVKfI5Aor0iEixgODhFsRcG0QcgTp0kn59si/qFOx1Tda/lzdfYtyPBDdCGkb U0GzmEYryQnlpUz9e8UWnN4sFUry6+xluXkR4ofmyJK2tBmn3zQdi+7wQgKmwBj5I0ei Iz/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LOnPpnuMKkccMrLHa9CGSbvxkJcyPXIgAVNGagVwJaU=; b=J+Hb0jeRo/DKHD3/2ngNEU0nM32ump03UpxA1JP78kfiBj6iCSfNfCyNV9TRz+rkcU MgDdLj+6a6IWIqpnKIqVn8GAkbzj7NcpTttIM9XcWZF8HdVMYAoteT2f4YvCHwDU+VQb BDWzpZtfS2FBp+ibXJtds061Cdbyu32pj3S32cLigc30Gde3eDBmeoOEW7wSJqaPSkF6 8pqTKwj57QheX+YBYqcS3UZMCFOn1luKZQdozo1cL/b7xvFpvhMOfViD9w/nbwnyfZ+5 Wr+dpRfrACplrRMVK1yKG3sOCNX7xsMQZ6OnsdCBjb+QhKpatQNq9xfmrs77IV/i0xAA Jdxw== X-Gm-Message-State: AOAM533Cx/XF4IcI806Db/CtgzPFZfXSTw1HvMq9yUAr7zk+dLCA/QAe g+aAzzK1wR8AQxs0hXVmesCp1UCVQuiqCQ== X-Google-Smtp-Source: ABdhPJy1ADybeVlv5SFBQVeYOChoZjrtX3iGB8d7vMl6gaX1++ZZNjXsi+CYspLJty+pJUHTsRoUow== X-Received: by 2002:a17:902:7d8a:: with SMTP id a10mr1942148plm.116.1591776492887; Wed, 10 Jun 2020 01:08:12 -0700 (PDT) Received: from gamma16.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id b140sm11920633pfb.119.2020.06.10.01.08.12 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Jun 2020 01:08:12 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com Subject: [PATCH 1/2] RISC-V: Describe correct USEs for gpr_save pattern [PR95252] Date: Wed, 10 Jun 2020 01:08:09 -0700 Message-Id: <1591776490-381147-1-git-send-email-kito.cheng@sifive.com> X-Mailer: git-send-email 2.7.4 X-Spam-Status: No, score=-16.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" - Verified on rv32emc/rv32gc/rv64gc bare-metal target and rv32gc/rv64gc linux target with qemu. gcc/ChangeLog: * config/riscv/predicates.md (gpr_save_operation): New. * config/riscv/riscv-protos.h (riscv_gen_gpr_save_insn): New. (riscv_gpr_save_operation_p): Ditto. * config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls): Ignore USEs for gpr_save patter. * config/riscv/riscv.c (gpr_save_reg_order): New. (riscv_expand_prologue): Use riscv_gen_gpr_save_insn to gen gpr_save. (riscv_gen_gpr_save_insn): New. (riscv_gpr_save_operation_p): Ditto. * config/riscv/riscv.md (S3_REGNUM): New. (S4_REGNUM): Ditto. (S5_REGNUM): Ditto. (S6_REGNUM): Ditto. (S7_REGNUM): Ditto. (S8_REGNUM): Ditto. (S9_REGNUM): Ditto. (S10_REGNUM): Ditto. (S11_REGNUM): Ditto. (gpr_save): Model USEs correctly. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr95252.c: New. --- gcc/config/riscv/predicates.md | 6 +++ gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-sr.c | 4 ++ gcc/config/riscv/riscv.c | 79 +++++++++++++++++++++++++++++++- gcc/config/riscv/riscv.md | 19 ++++++-- gcc/testsuite/gcc.target/riscv/pr95252.c | 47 +++++++++++++++++++ 6 files changed, 152 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr95252.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index f722881..f764fe7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -206,3 +206,9 @@ (define_predicate "fp_branch_comparison" (match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge")) + +(define_special_predicate "gpr_save_operation" + (match_code "parallel") +{ + return riscv_gpr_save_operation_p (op); +}) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 2f3ca99..9cda6a8 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -73,6 +73,8 @@ extern bool riscv_can_use_return_insn (void); extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); extern bool riscv_expand_block_move (rtx, rtx, rtx); extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); +extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); +extern bool riscv_gpr_save_operation_p (rtx); /* Routines implemented in riscv-c.c. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv-sr.c b/gcc/config/riscv/riscv-sr.c index 744d0c4..b8fe9d0 100644 --- a/gcc/config/riscv/riscv-sr.c +++ b/gcc/config/riscv/riscv-sr.c @@ -306,6 +306,10 @@ riscv_remove_unneeded_save_restore_calls (void) if (CALL_P (insn)) ++call_count; + /* Ignore any USEs in the gpr_save pattern. They don't prevent us + from optimizing away the save call. */ + else if (insn == prologue_matched) + ; else { df_ref use; diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 1ad9799..715c263 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -334,6 +334,14 @@ static const struct attribute_spec riscv_attribute_table[] = { NULL, 0, 0, false, false, false, false, NULL, NULL } }; +/* Order for the CLOBBERs/USEs of gpr_save. */ +static const unsigned gpr_save_reg_order[] = { + INVALID_REGNUM, T0_REGNUM, T1_REGNUM, RETURN_ADDR_REGNUM, + S0_REGNUM, S1_REGNUM, S2_REGNUM, S3_REGNUM, S4_REGNUM, + S5_REGNUM, S6_REGNUM, S7_REGNUM, S8_REGNUM, S9_REGNUM, + S10_REGNUM, S11_REGNUM +}; + /* A table describing all the processors GCC knows about. */ static const struct riscv_cpu_info riscv_cpu_info_table[] = { { "rocket", generic, &rocket_tune_info }, @@ -4069,9 +4077,9 @@ riscv_expand_prologue (void) rtx dwarf = NULL_RTX; dwarf = riscv_adjust_libcall_cfi_prologue (); - frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ size -= frame->save_libcall_adjustment; - insn = emit_insn (gen_gpr_save (GEN_INT (mask))); + insn = emit_insn (riscv_gen_gpr_save_insn (frame)); + frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ RTX_FRAME_RELATED_P (insn) = 1; REG_NOTES (insn) = dwarf; @@ -5177,6 +5185,73 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr) return new_cost <= old_cost; } +rtx +riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) +{ + unsigned count = riscv_save_libcall_count (frame->mask); + /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */ + unsigned veclen = 1 + 2 + 1 + count; + rtvec vec = rtvec_alloc (veclen); + + gcc_assert (veclen <= ARRAY_SIZE (gpr_save_reg_order)); + + RTVEC_ELT (vec, 0) = + gen_rtx_UNSPEC_VOLATILE (VOIDmode, + gen_rtvec (1, GEN_INT (frame->mask)), UNSPECV_GPR_SAVE); + + for (int i = 1; i < veclen; ++i) + { + unsigned regno = gpr_save_reg_order[i]; + rtx reg = gen_rtx_REG (Pmode, regno); + rtx elt; + + /* t0 and t1 are CLOBBERs, others are USEs. */ + if (i < 3) + elt = gen_rtx_CLOBBER (Pmode, reg); + else + elt = gen_rtx_USE (Pmode, reg); + + RTVEC_ELT (vec, i) = elt; + } + + /* Largest number of caller-save register must set in mask if we are + not using __riscv_save_0. */ + gcc_assert ((count == 0) || + BITSET_P (frame->mask, gpr_save_reg_order[veclen - 1])); + + return gen_rtx_PARALLEL (VOIDmode, vec); +} + +bool +riscv_gpr_save_operation_p (rtx op) +{ + HOST_WIDE_INT len = XVECLEN (op, 0); + gcc_assert (len <= ARRAY_SIZE (gpr_save_reg_order)); + for (int i = 0; i < len; i++) + { + rtx elt = XVECEXP (op, 0, i); + if (i == 0) + { + /* First element in parallel is unspec. */ + if (GET_CODE (elt) != UNSPEC_VOLATILE + || GET_CODE (XVECEXP (elt, 0, 0)) != CONST_INT + || XINT (elt, 1) != UNSPECV_GPR_SAVE) + return false; + } + else + { + /* Two CLOBBER and USEs, must check the order. */ + unsigned expect_code = i < 3 ? CLOBBER : USE; + if (GET_CODE (elt) != expect_code + || !REG_P (XEXP (elt, 1)) + || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i])) + return false; + } + break; + } + return true; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f4bdb7d..d9028c5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -75,6 +75,15 @@ (S0_REGNUM 8) (S1_REGNUM 9) (S2_REGNUM 18) + (S3_REGNUM 19) + (S4_REGNUM 20) + (S5_REGNUM 21) + (S6_REGNUM 22) + (S7_REGNUM 23) + (S8_REGNUM 24) + (S9_REGNUM 25) + (S10_REGNUM 26) + (S11_REGNUM 27) (NORMAL_RETURN 0) (SIBCALL_RETURN 1) @@ -2427,10 +2436,14 @@ "" "ebreak") +;; Must use the registers that we save to prevent the rename reg optimization +;; pass from using them before the gpr_save pattern when shrink wrapping +;; occurs. See bug 95252 for instance. + (define_insn "gpr_save" - [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_SAVE) - (clobber (reg:SI T0_REGNUM)) - (clobber (reg:SI T1_REGNUM))] + [(match_parallel 1 "gpr_save_operation" + [(unspec_volatile [(match_operand 0 "const_int_operand")] + UNSPECV_GPR_SAVE)])] "" { return riscv_output_gpr_save (INTVAL (operands[0])); }) diff --git a/gcc/testsuite/gcc.target/riscv/pr95252.c b/gcc/testsuite/gcc.target/riscv/pr95252.c new file mode 100644 index 0000000..0366c08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr95252.c @@ -0,0 +1,47 @@ +/* PR target/95252 */ +/* { dg-options "-O3 -funroll-loops -msave-restore" } */ +/* { dg-do run } */ + +int a[6], b = 1, d, e; +long long c; +static int f = 1; + +void +fn1 (int p1) +{ + b = (b >> 1) & (1 ^ a[(1 ^ p1) & 5]); +} + +void +fn2 () +{ + b = (b >> 1) & (1 ^ a[(b ^ 1) & 1]); + fn1 (c >> 1 & 5); + fn1 (c >> 2 & 5); + fn1 (c >> 4 & 5); + fn1 (c >> 8 & 5); +} + +int +main () +{ + int i, j; + for (; d;) + { + for (; e;) + fn2 (); + f = 0; + } + for (i = 0; i < 8; i++) + { + if (f) + i = 9; + for (j = 0; j < 7; j++) + fn2 (); + } + + if (b != 0) + __builtin_abort (); + + return 0; +} From patchwork Wed Jun 10 08:08:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 1306635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=iNBgxDgo; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49hfkd0wgrz9sRR for ; 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Wed, 10 Jun 2020 01:08:15 -0700 (PDT) Received: from gamma16.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id b140sm11920633pfb.119.2020.06.10.01.08.14 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Jun 2020 01:08:14 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com Subject: [PATCH 2/2] RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern. Date: Wed, 10 Jun 2020 01:08:10 -0700 Message-Id: <1591776490-381147-2-git-send-email-kito.cheng@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591776490-381147-1-git-send-email-kito.cheng@sifive.com> References: <1591776490-381147-1-git-send-email-kito.cheng@sifive.com> X-Spam-Status: No, score=-16.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_output_gpr_save): Remove. * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Update value. * config/riscv/riscv.c (riscv_output_gpr_save): Remove. * config/riscv/riscv.md (gpr_save): Update output asm pattern. --- gcc/config/riscv/riscv-protos.h | 1 - gcc/config/riscv/riscv-sr.c | 2 +- gcc/config/riscv/riscv.c | 16 +--------------- gcc/config/riscv/riscv.md | 2 +- 4 files changed, 3 insertions(+), 18 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 9cda6a8..358224a 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -53,7 +53,6 @@ extern rtx riscv_subword (rtx, bool); extern bool riscv_split_64bit_move_p (rtx, rtx); extern void riscv_split_doubleword_move (rtx, rtx); extern const char *riscv_output_move (rtx, rtx); -extern const char *riscv_output_gpr_save (unsigned); extern const char *riscv_output_return (); #ifdef RTX_CODE extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); diff --git a/gcc/config/riscv/riscv-sr.c b/gcc/config/riscv/riscv-sr.c index b8fe9d0..9af50ef 100644 --- a/gcc/config/riscv/riscv-sr.c +++ b/gcc/config/riscv/riscv-sr.c @@ -115,7 +115,7 @@ riscv_sr_match_prologue (rtx_insn **body) && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC_VOLATILE && (GET_CODE (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == CONST_INT) - && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 2) + && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 0) return insn; return NULL; diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 715c263..0d58f32 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3951,20 +3951,6 @@ riscv_restore_reg (rtx reg, rtx mem) RTX_FRAME_RELATED_P (insn) = 1; } -/* Return the code to invoke the GPR save routine. */ - -const char * -riscv_output_gpr_save (unsigned mask) -{ - static char s[32]; - unsigned n = riscv_save_libcall_count (mask); - - ssize_t bytes = snprintf (s, sizeof (s), "call\tt0,__riscv_save_%u", n); - gcc_assert ((size_t) bytes < sizeof (s)); - - return s; -} - /* For stack frames that can't be allocated with a single ADDI instruction, compute the best value to initially allocate. It must at a minimum allocate enough space to spill the callee-saved registers. If TARGET_RVC, @@ -5197,7 +5183,7 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) RTVEC_ELT (vec, 0) = gen_rtx_UNSPEC_VOLATILE (VOIDmode, - gen_rtvec (1, GEN_INT (frame->mask)), UNSPECV_GPR_SAVE); + gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE); for (int i = 1; i < veclen; ++i) { diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d9028c5..36012ad 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2445,7 +2445,7 @@ [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_SAVE)])] "" - { return riscv_output_gpr_save (INTVAL (operands[0])); }) + "call\tt0,__riscv_save_%0") (define_insn "gpr_restore" [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_RESTORE)]