From patchwork Thu May 21 17:48:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 1295508 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=mX0Tp9zE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49Scb33Z21z9sPF for ; Fri, 22 May 2020 03:50:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728903AbgEURuG (ORCPT ); Thu, 21 May 2020 13:50:06 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57762 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730254AbgEURsl (ORCPT ); Thu, 21 May 2020 13:48:41 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZWk052539; Thu, 21 May 2020 12:48:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590083315; bh=oP5/4iAxad86JB5Vq5xypRCcIfd0uO0QCRiPzAP7S7Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mX0Tp9zEAxKflpHQSBLhIGx9kQfkTko2hobicymaj2s/XyROUc51DgxJZnounruN3 8elPPqBJ7zSD0rrM24fRVYy8kyrvhi8Uwkvy+LYfgL6ZKd+8tCPJcZ2kzg7jSjqNAd 0HY4Qu0tEKR5zwtFEkIQHeq2yZUpZJ1FUt7pm6bE= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZPP120116; Thu, 21 May 2020 12:48:35 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 May 2020 12:48:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 May 2020 12:48:35 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZeJ038639; Thu, 21 May 2020 12:48:35 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [RFC PATCH net-next 1/4] dt-bindings: net: Add tx and rx internal delays Date: Thu, 21 May 2020 12:48:31 -0500 Message-ID: <20200521174834.3234-2-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521174834.3234-1-dmurphy@ti.com> References: <20200521174834.3234-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org tx-internal-delays and rx-internal-delays are a common setting for RGMII capable devices. These properties are used when the phy-mode or phy-controller is set to rgmii-id, rgmii-rxid or rgmii-txid. These modes indicate to the controller that the PHY will add the internal delay for the connection. Signed-off-by: Dan Murphy --- .../bindings/net/ethernet-controller.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index ac471b60ed6a..3f25066c339c 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -143,6 +143,20 @@ properties: Specifies the PHY management type. If auto is set and fixed-link is not specified, it uses MDIO for management. + rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable RX internal delays. This property is only + used when the phy-mode or phy-connection-type is rgmii-id or rgmii-rxid. + + tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for + PHY's that have configurable TX internal delays. This property is only + used when the phy-mode or phy-connection-type is rgmii-id or rgmii-txid. + fixed-link: allOf: - if: From patchwork Thu May 21 17:48:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 1295485 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=lQGQKAtK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49ScYs3z3Wz9sPF for ; Fri, 22 May 2020 03:49:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730339AbgEURsq (ORCPT ); Thu, 21 May 2020 13:48:46 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57764 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730255AbgEURsm (ORCPT ); Thu, 21 May 2020 13:48:42 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZA5052544; Thu, 21 May 2020 12:48:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590083315; bh=qos1fvvu633d2pJTPbu/Q+SMdAvpHI/AStqQHTvDHV4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lQGQKAtK8lOBuDLUfD5EgxeYzMYT4cRuYyHrSqYkqta51mfcxR+K+cxoMSfqr692E vd0pOQ+nBtdXADm6N4HhYbYYMiLa8SrSFiumd9KzjNme0JwIoKl9MbmUvtQB0+YypR B8a5AV6fN+bw+TWDkYnL8uz9MBWsfAh1kZ7ugEIg= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04LHmZXC128922 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 21 May 2020 12:48:35 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 May 2020 12:48:35 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 May 2020 12:48:35 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZhf026281; Thu, 21 May 2020 12:48:35 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [RFC PATCH net-next 2/4] net: phy: Add a helper to return the index for of the internal delay Date: Thu, 21 May 2020 12:48:32 -0500 Message-ID: <20200521174834.3234-3-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521174834.3234-1-dmurphy@ti.com> References: <20200521174834.3234-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add a helper function that will return the index in the array for the passed in internal delay value. The helper requires the array, size and delay value. The helper will then return the index for the exact match or return the index for the index to the closest smaller value. Signed-off-by: Dan Murphy --- drivers/net/phy/phy_device.c | 45 ++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 2 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 7481135d27ab..40f53b379d2b 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2661,6 +2661,51 @@ void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause) } EXPORT_SYMBOL(phy_get_pause); +/** + * phy_get_delay_index - returns the index of the internal delay + * @phydev: phy_device struct + * @delay_values: array of delays the PHY supports + * @size: the size of the delay array + * @delay: the delay to be looked up + * + * Returns the index within the array of internal delay passed in. + */ +int phy_get_delay_index(struct phy_device *phydev, int *delay_values, int size, + int delay) +{ + int i; + + if (size <= 0) + return -EINVAL; + + if (delay <= delay_values[0]) + return 0; + + if (delay > delay_values[size - 1]) + return size - 1; + + for (i = 0; i < size; i++) { + if (delay == delay_values[i]) + return i; + + /* Find an approximate index by looking up the table */ + if (delay > delay_values[i - 1] && + delay < delay_values[i]) { + if (delay - delay_values[i - 1] < delay_values[i] - delay) + return i - 1; + else + return i; + } + + } + + phydev_err(phydev, "error finding internal delay index for %d\n", + delay); + + return -EINVAL; +} +EXPORT_SYMBOL(phy_get_delay_index); + static bool phy_drv_supports_irq(struct phy_driver *phydrv) { return phydrv->config_intr && phydrv->ack_interrupt; diff --git a/include/linux/phy.h b/include/linux/phy.h index 467aa8bf9f64..78b7b77f9a67 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1406,6 +1406,8 @@ void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); bool phy_validate_pause(struct phy_device *phydev, struct ethtool_pauseparam *pp); void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); +int phy_get_delay_index(struct phy_device *phydev, int *delay_values, + int size, int delay); void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, bool *tx_pause, bool *rx_pause); From patchwork Thu May 21 17:48:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 1295509 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=nZH6NxmB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49Scb95Vwlz9sSc for ; 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Thu, 21 May 2020 12:48:36 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 May 2020 12:48:35 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 May 2020 12:48:35 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZSY058993; Thu, 21 May 2020 12:48:35 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [RFC PATCH net-next 3/4] dt-bindings: net: Add RGMII internal delay for DP83869 Date: Thu, 21 May 2020 12:48:33 -0500 Message-ID: <20200521174834.3234-4-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521174834.3234-1-dmurphy@ti.com> References: <20200521174834.3234-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add the internal delay values into the header and update the binding with the internal delay properties. Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ti,dp83869.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 5b69ef03bbf7..b2547b43e103 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -64,6 +64,20 @@ properties: Operational mode for the PHY. If this is not set then the operational mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values + rx-internal-delay: + $ref: "#/properties/rx-internal-delay" + description: Delay is in pico seconds + enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000 ] + default: 2000 + + tx-internal-delay: + $ref: "#/properties/tx-internal-delay" + description: Delay is in pico seconds + enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000 ] + default: 2000 + required: - reg @@ -80,5 +94,7 @@ examples: ti,op-mode = ; ti,max-output-impedance = "true"; ti,clk-output-sel = ; + rx-internal-delay = <2000>; + tx-internal-delay = <2000>; }; }; From patchwork Thu May 21 17:48:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 1295478 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=p0rg/9Fa; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49ScYY6qGdz9sSc for ; Fri, 22 May 2020 03:48:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730354AbgEURss (ORCPT ); Thu, 21 May 2020 13:48:48 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38412 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730265AbgEURsn (ORCPT ); Thu, 21 May 2020 13:48:43 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04LHma6E018706; Thu, 21 May 2020 12:48:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590083316; bh=FdcDNpk5is//NHRdgScD3PLoepWGfgG9j0F9KO2fZPI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=p0rg/9FapKM5+O6vkzskwQdcJXxpvZ64Uy3EFIZUuwFHtQSAL523C5qR/bB8fWVDD dyJYVKPLVY+vTE1ZXWlnZ0mfxzKDXuTqslJaaUDnzwN7lCiRZj/TdwQsXjsteA5ljr qqSN1jyMo3vLHNw461n6KH8U8YW9WP7fcuTIVZMc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmajo120142; Thu, 21 May 2020 12:48:36 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 21 May 2020 12:48:36 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 21 May 2020 12:48:36 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04LHmZ24082172; Thu, 21 May 2020 12:48:36 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [RFC PATCH net-next 4/4] net: dp83869: Add RGMII internal delay configuration Date: Thu, 21 May 2020 12:48:34 -0500 Message-ID: <20200521174834.3234-5-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200521174834.3234-1-dmurphy@ti.com> References: <20200521174834.3234-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add RGMII internal delay configuration for Rx and Tx. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83869.c | 101 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index cfb22a21a2e6..40c34fefffe4 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -99,6 +99,14 @@ #define DP83869_OP_MODE_MII BIT(5) #define DP83869_SGMII_RGMII_BRIDGE BIT(6) +/* RGMIIDCTL bits */ +#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 +#define DP83869_RGMII_CLK_DELAY_INV 0 + +static int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, + 2000, 2250, 2500, 2750, 3000, 3250, + 3500, 3750, 4000}; + enum { DP83869_PORT_MIRRORING_KEEP, DP83869_PORT_MIRRORING_EN, @@ -108,6 +116,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + u32 rx_id_delay; + u32 tx_id_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -182,6 +192,7 @@ static int dp83869_of_init(struct phy_device *phydev) struct dp83869_private *dp83869 = phydev->priv; struct device *dev = &phydev->mdio.dev; struct device_node *of_node = dev->of_node; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); int ret; if (!of_node) @@ -232,6 +243,26 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + dp83869->rx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "rx-internal-delay", + &dp83869->rx_id_delay); + if (!ret && dp83869->rx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "rx-internal-delay value of %u out of range\n", + dp83869->rx_id_delay); + return -EINVAL; + } + + dp83869->tx_id_delay = DP83869_RGMII_CLK_DELAY_INV; + ret = of_property_read_u32(of_node, "tx-internal-delay", + &dp83869->tx_id_delay); + if (!ret && dp83869->tx_id_delay > dp83869_internal_delay[delay_size]) { + phydev_err(phydev, + "tx-internal-delay value of %u out of range\n", + dp83869->tx_id_delay); + return -EINVAL; + } + return ret; } #else @@ -270,6 +301,29 @@ static int dp83869_configure_rgmii(struct phy_device *phydev, return ret; } +static int dp83869_verify_rgmii_cfg(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + + /* RX delay *must* be specified if internal delay of RX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && + dp83869->rx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); + return -EINVAL; + } + + /* TX delay *must* be specified if internal delay of TX is used. */ + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && + dp83869->tx_id_delay == DP83869_RGMII_CLK_DELAY_INV) { + phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); + return -EINVAL; + } + + return 0; +} + static int dp83869_configure_mode(struct phy_device *phydev, struct dp83869_private *dp83869) { @@ -371,6 +425,12 @@ static int dp83869_config_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; int ret, val; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); + int delay = 0; + + ret = dp83869_verify_rgmii_cfg(phydev); + if (ret) + return ret; ret = dp83869_configure_mode(phydev, dp83869); if (ret) @@ -394,6 +454,47 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, val); + + if (dp83869->rx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->rx_id_delay); + if (val < 0) + return val; + + delay |= val; + } + + if (dp83869->tx_id_delay) { + val = phy_get_delay_index(phydev, + &dp83869_internal_delay[0], + delay_size, + dp83869->tx_id_delay); + if (val < 0) + return val; + + delay |= val << DP83869_RGMII_TX_CLK_DELAY_SHIFT; + } + + phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + delay); + } + return ret; }