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Fri, 15 May 2020 11:20:32 +0000 (GMT) From: Marek Szyprowski To: u-boot@lists.denx.de Cc: Marek Szyprowski , Matthias Brugger , Tom Rini , Sylwester Nawrocki , marex@denx.de, bmeng.cn@gmail.com, nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, b.zolnierkie@samsung.com Subject: [RFC PATCH v2 1/2] arm: provide a function for boards init code to modify MMU virtual-physical map Date: Fri, 15 May 2020 13:20:15 +0200 Message-Id: <20200515112016.24522-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200515112016.24522-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfSxVcRjH93POueeg206X5Ql5uVu2NGTYzhJlSztrzfqrNRYOzi5xL7uX W9gkxs2dMC+lq7z9EdHtEomMidYtVySztHldavNWjWpCLccZ/fd5vs/3+X63334UJrtHOFIJ qlRereKS5BIbvOPV7xEvlNkbefzzrBvTWmkimIrCKGZiI59gjC+nSGY5/wZiasvmCabD0CBh BpZ1BPOrvQMxFaVtJLPSU0CetmWrskdxttrwGme7DFMku9jXRLJvJzsRW9TehFhT+zjOtlky L1DhNifj+KQELa/2CY62ibd8y7NKqXG59jBnGs9GW6BH1hTQ/pBbNyLRIxtKRjci+L6eh4nD DwSDf4xIHNYQdD/SWe2eNH+ZJgSW0Q0I5puP7V3k1lTtLCS0L+hX9BKB7WmAjeLxnSSMbrSC NV0VKSzsaCW8mWrCBMbpIzC4XoAEltJBYNx8SohtrtDc0rftoShrOhgmx3BRfkBC0bKTIAN9 BnQ5maJsB4vmdlJkZ7CUFeJCLdC5COaGjaQ4FCIYy6lEoisQJoc3JEIQRh8F03MfUQ6B0aUe XMzfDxMrBwQZ28bSjjuYKEvhZr5MdHuAwfx4r/bFu/eYyCwUfSgmxOcZQDDebSRKkKvhf1kt Qk3IgU/TKBW8xk/FX/XWcEpNmkrhHZusfIK2/4zlr/lnJ+rdiulHNIXk+6SzGb2RMoLTatKV /QgoTG4vDTN1R8qkcVx6Bq9OjlKnJfGafuRE4XIHqV/9wmUZreBS+USeT+HVu1srytoxG901 K7yzz94O4zyX1mdqh7QtFxcR13AwNyDF/VRWQETrfdPM+XKldjU6tD7Cxd2tesVhoKTlSkyg KuQjpl5F9xmduajZ9vCn8roUlOUWN/fVK3HeApf8J+sdLHBroVi7OeRx6Fy1l74mKPVEV4F7 eOj16lL+2Rzm6lwhIUpi5bgmnvP1xNQa7h9tJx5GLwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xe7qM1fviDE6e4rLYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFlMnbWa3eLu3k92B22N2w0UW j3mzTrB47Jx1l93j1YFV7B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GWcft/KVDBfrmJl0z2WBsY/El2M nBwSAiYSq5/dY+1i5OIQEljKKDF370Z2iISMxMlpDawQtrDEn2tdbBBFnxgltp+7xwaSYBMw lOh62wVmiwhISPzqv8oIUsQssIlJ4tLeBWAJYYFsiUP3mllAbBYBVYlTPzoZQWxeAVuJtb+3 Qm2Ql1i94QBzFyMHB6eAncSdy2DlQgL5En/vLWCbwMi3gJFhFaNIamlxbnpusaFecWJucWle ul5yfu4mRmDgbzv2c/MOxksbgw8xCnAwKvHwPqjaFyfEmlhWXJl7iFGCg1lJhNdv/e44Id6U xMqq1KL8+KLSnNTiQ4ymQDdNZJYSTc4HRmVeSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS 1OzU1ILUIpg+Jg5OqQZGrW9q1deNk7ftjLuslDuDzybCjOeE3Ys75XeCntdO3JW8ZL7618Ws AeKv5AWZ579JrlbnON0vfv2qnjAz0/r6eI0r8dkpB9n51oZ65k52XJVnVne5K6f17/1JR769 6HWo/dbxd6KAbO/Z0PvG2+52FE38sHw1rz3zZ2WnyL6p+7XFnmVYbc9SYinOSDTUYi4qTgQA ViSOhpICAAA= X-CMS-MailID: 20200515112033eucas1p29c631060556949761d0c7c06c2088374 X-Msg-Generator: CA X-RootMTR: 20200515112033eucas1p29c631060556949761d0c7c06c2088374 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200515112033eucas1p29c631060556949761d0c7c06c2088374 References: <71b88bb9-7bfd-cb33-59b8-052c08ed33fa@suse.com> <20200515112016.24522-1-m.szyprowski@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Provide a function for setting arbitrary virtual-physical MMU mapping for the given region. Signed-off-by: Marek Szyprowski --- arch/arm/include/asm/mmu.h | 8 ++++++++ arch/arm/include/asm/system.h | 11 +++++++++++ arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------ 3 files changed, 37 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/mmu.h diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000..fe3d793 --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead..5b9f31c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -573,6 +573,17 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * Change the virt/phys mapping and cache settings for a region. + * + * \param virt virtual start address of memory region to change + * \param phys physical address for the memory region to set + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** * Change the cache settings for a region. * * \param start start address of memory region to change diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d2096..84ddad3 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -24,7 +24,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -36,7 +37,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -45,13 +46,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -70,8 +76,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned @@ -86,6 +92,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, mmu_page_table_flush(startpt, stoppt); } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} + __weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; From patchwork Fri May 15 11:20:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 1291054 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=kzB8gWg2; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49NmFR1Pcjz9sTC for ; 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Fri, 15 May 2020 11:20:33 +0000 (GMT) From: Marek Szyprowski To: u-boot@lists.denx.de Cc: Marek Szyprowski , Matthias Brugger , Tom Rini , Sylwester Nawrocki , marex@denx.de, bmeng.cn@gmail.com, nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, b.zolnierkie@samsung.com Subject: [RFC PATCH v2 2/2] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Fri, 15 May 2020 13:20:16 +0200 Message-Id: <20200515112016.24522-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200515112016.24522-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djP87pM1fviDO5e57HYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFlMnbWa3eLu3k92B22N2w0UW j3mzTrB47Jx1l93j1YFV7B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGW8 XTaFsWC1SMWWPQ9ZGhi/CXQxcnJICJhItP9Zz9rFyMUhJLCCUeLGyjYWCOcLo8TUSdPZQaqE BD4zSry4LwrTcfrWY2aIouWMEj86ulnhOs7tmc0GUsUmYCjR9bYLzBYRkJD41X+VEaSIWWAF k8Tn9tlgY4UFMiV6rk8BK2IRUJXY0dMIFucVsJXo2dDPCLFOXmL1hgNA6zg4OAXsJO5cBjtP QmAZu8TFTeeYIWpcJFofL2CDsIUlXh3fwg5hy0j83zmfCaKhmVHi4bm17BBOD6PE5aYZUBus Je6c+8UGsoFZQFNi/S59iLCjxMQ5DYwgYQkBPokbbwVBwsxA5qRt05khwrwSHW1CENVqErOO r4Nbe/DCJajTPCS+X1rGDgmgw4wSGx/9YZ3AKD8LYdkCRsZVjOKppcW56anFxnmp5XrFibnF pXnpesn5uZsYganm9L/jX3cw7vuTdIhRgINRiYf3QdW+OCHWxLLiytxDjBIczEoivH7rd8cJ 8aYkVlalFuXHF5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwOixdWOUs3CC 8WTHLWsznV8f0jz6v6Mt9JjkzdU3OrkcTISuam9PjXifWyKt89mn5fPb/SyHWlW+NttV3H0m vEdw/VUN/jlun474tlxocDvp9O13YsfLY7zeZ6rF78/2eB3Vsd7a0E7nj9sUkwwutpjgG1v/ c8x7JlT7/OGah5YxN/lTXPnbipRYijMSDbWYi4oTAT5qAQIxAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xe7qM1fviDFo+61lsnLGe1WJqT7zF jV9trBZrj9xlt3jT1shosWDyE1aLbbOWs1kcftPOavFtyzZGi6mTNrNbvN3bye7A7TG74SKL x7xZJ1g8ds66y+7x6sAqdo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DLeLpvCWLBapGLLnocsDYzfBLoY OTkkBEwkTt96zNzFyMUhJLCUUeLz8p1sEAkZiZPTGlghbGGJP9e62CCKPjFKXFp1CCzBJmAo 0fW2C6xBREBC4lf/VUaQImaBTUwSl/YuAEsIC6RLHD05jx3EZhFQldjR0whm8wrYSvRs6GeE 2CAvsXrDAaAzODg4Bewk7lxmAQkLCeRL/L23gG0CI98CRoZVjCKppcW56bnFRnrFibnFpXnp esn5uZsYgYG/7djPLTsYu94FH2IU4GBU4uE1mLo3Tog1say4MvcQowQHs5IIr9/63XFCvCmJ lVWpRfnxRaU5qcWHGE2BbprILCWanA+MyrySeENTQ3MLS0NzY3NjMwslcd4OgYMxQgLpiSWp 2ampBalFMH1MHJxSDYwZS4/6fE7a7Cxwc0vHEYW/zAwBAgVLrqclXP679HCKTeMOw9bncivZ dFiTt8Vl7JOtilD+naR3qkXl/NrnRT+uFzzm6go4WHhV3PDtdce6xP8K5kfXxLmqRv+aNCXa 1cdY/ZCPUp1XvVvj0yk2RhK/RNWKttsyMr2e6+y068Xa65MvPHfNq1diKc5INNRiLipOBACy xJLEkgIAAA== X-CMS-MailID: 20200515112033eucas1p1cd20ecf4b87ae37a056eadb87b5b48be X-Msg-Generator: CA X-RootMTR: 20200515112033eucas1p1cd20ecf4b87ae37a056eadb87b5b48be X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200515112033eucas1p1cd20ecf4b87ae37a056eadb87b5b48be References: <71b88bb9-7bfd-cb33-59b8-052c08ed33fa@suse.com> <20200515112016.24522-1-m.szyprowski@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 6 ++++++ arch/arm/mach-bcm283x/init.c | 14 ++++++++++++++ include/configs/rpi.h | 5 +++++ 4 files changed, 26 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1bf89db 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,10 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#include +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..4b9c831 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,20 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 0); +} + void enable_caches(void) { dcache_enable(); diff --git a/include/configs/rpi.h b/include/configs/rpi.h index b53a4b6..7da2cff 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -63,6 +63,11 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M #endif +#ifdef CONFIG_ARMV7_LPAE +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 2 +#endif + /* Devices */ /* GPIO */ #define CONFIG_BCM2835_GPIO