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Tue, 12 May 2020 13:18:06 +0000 (GMT) From: Marek Szyprowski To: u-boot@lists.denx.de Cc: Marek Szyprowski , Matthias Brugger , Tom Rini , Sylwester Nawrocki , marex@denx.de, bmeng.cn@gmail.com, nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, b.zolnierkie@samsung.com Subject: [RFC PATCH 1/2] arm: provide a function for boards init code to modify MMU virtual-physical map Date: Tue, 12 May 2020 15:17:45 +0200 Message-Id: <20200512131746.22797-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200512131746.22797-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsWy7djP87r8i3bFGXz/KmGxccZ6VoupPfEW N361sVqsPXKX3eJNWyOjxYLJT1gtts1azmZx+E07q8W3LdsYLaZO2sxu8XZvJ7sDt8fshoss HvNmnWDx2DnrLrvHqwOr2D3O3tnB6NG3ZRWjx/otV1k8Np+uDuCI4rJJSc3JLEst0rdL4Mr4 vKWNseCNXMX9u/PZGxh3S3YxcnJICJhIdN9vZ+9i5OIQEljBKLHwyxtGCOcLo8SfG3OhMp8Z JfaeXcEI07L522pWiMRyRon2+0fZ4Vre3f/OAlLFJmAo0fW2iw3EFhGQkPjVfxVsLrPACiaJ z+2z2UESwgJZEn0fr4KNZRFQlTi68SsziM0rYCvx/9p5doh18hKrNxwAi3MK2EmcPnqNCWSQ hMAydomzW69C3eQi8fTZK1YIW1ji1fEtUM0yEqcn97BANDQzSjw8t5YdwulhlLjcNAOq21ri zrlfQLdyAN2nKbF+lz5E2FGiZ8NNFpCwhACfxI23giBhZiBz0rbpzBBhXomONiGIajWJWcfX wa09eOESM4TtIdH0+i00hA4zSiw+28QygVF+FsKyBYyMqxjFU0uLc9NTi43zUsv1ihNzi0vz 0vWS83M3MQLTzel/x7/uYNz3J+kQowAHoxIPb0T9rjgh1sSy4srcQ4wSHMxKIrwtmTvjhHhT EiurUovy44tKc1KLDzFKc7AoifMaL3oZKySQnliSmp2aWpBaBJNl4uCUamA0FmfhSvR+0qn4 fppsSamZUbCJigP7j6XfZ/pdn8CWOfNlGINTT7LVuYSDjGePTYsMXXTsgIPUwV9qQkKqezdt z/yV+n9/mLTJyf3Rrw5efuyWujPC5b+CA/fNTevdP4XlGdVvjueSrdtgqsCULjEruomPa4b/ /fR2p0Bzj0V/7SSc9xy2na3EUpyRaKjFXFScCABRSGygMwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42I5/e/4PV2+RbviDB4csrDYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFlMnbWa3eLu3k92B22N2w0UW j3mzTrB47Jx1l93j1YFV7B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GV83tLGWPBGruL+3fnsDYy7JbsY OTkkBEwkNn9bzdrFyMUhJLCUUWLpjwtsEAkZiZPTGlghbGGJP9e62CCKPjFKXPl2hR0kwSZg KNH1tgusQURAQuJX/1VGkCJmgU1MEpf2LgBLCAtkSOzuOQ7WwCKgKnF041dmEJtXwFbi/7Xz 7BAb5CVWbzgAFucUsJM4ffQaE4gtJJAvseLpJaYJjHwLGBlWMYqklhbnpucWG+oVJ+YWl+al 6yXn525iBIb+tmM/N+9gvLQx+BCjAAejEg8vQ+2uOCHWxLLiytxDjBIczEoivC2ZO+OEeFMS K6tSi/Lji0pzUosPMZoCHTWRWUo0OR8Yl3kl8YamhuYWlobmxubGZhZK4rwdAgdjhATSE0tS s1NTC1KLYPqYODilGhgX6v1dbsvR/bvb5lUAp0761jXZ74t22im+S3/Ypc1cKRDyd+VjRrE8 lz1bZ3+P4Du545/FwTyl9+2dG3Q3t0Xs0Oftjfwscln05r2lUs90L/Vciy6f0dDB6Dw34IvN nNjQwya3jGerr9m0oSv3UD2/bUpAogJTlv/SG87zNL5s2hh664175g4lluKMREMt5qLiRAB6 fjJzkwIAAA== X-CMS-MailID: 20200512131806eucas1p1c093915ecfeda5da49cc8d944b7801a8 X-Msg-Generator: CA X-RootMTR: 20200512131806eucas1p1c093915ecfeda5da49cc8d944b7801a8 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200512131806eucas1p1c093915ecfeda5da49cc8d944b7801a8 References: <71b88bb9-7bfd-cb33-59b8-052c08ed33fa@suse.com> <20200512131746.22797-1-m.szyprowski@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Provide a function for setting arbitrary virtual-physical MMU mapping for the given region. Signed-off-by: Marek Szyprowski --- arch/arm/include/asm/mmu.h | 8 ++++++++ arch/arm/include/asm/system.h | 18 ++++++++++++++++-- arch/arm/lib/cache-cp15.c | 18 ++++++++++++------ 3 files changed, 36 insertions(+), 8 deletions(-) create mode 100644 arch/arm/include/asm/mmu.h diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h new file mode 100644 index 0000000..fe3d793 --- /dev/null +++ b/arch/arm/include/asm/mmu.h @@ -0,0 +1,8 @@ +#ifndef __ASM_ARM_MMU_H +#define __ASM_ARM_MMU_H + +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + +#endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 81ccead..a513f4a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -573,14 +573,28 @@ s32 psci_features(u32 function_id, u32 psci_fid); void save_boot_params_ret(void); /** + * Change the virt/phys mapping and cache settings for a region. + * + * \param virt virtual start address of memory region to change + * \param phys physical address for the memory region to set + * \param size size of memory region to change + * \param option dcache option to select + */ +void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, + size_t size, enum dcache_option option); + +/** * Change the cache settings for a region. * * \param start start address of memory region to change * \param size size of memory region to change * \param option dcache option to select */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); +static inline void mmu_set_region_dcache_behaviour(phys_addr_t start, + size_t size, enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} #ifdef CONFIG_SYS_NONCACHED_MEMORY void noncached_init(void); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d2096..7c14d1d 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -24,7 +24,8 @@ __weak void arm_init_domains(void) { } -void set_section_dcache(int section, enum dcache_option option) +static void set_section_phys(int section, phys_addr_t phys, + enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -36,7 +37,7 @@ void set_section_dcache(int section, enum dcache_option option) #endif /* Add the page offset */ - value |= ((u32)section << MMU_SECTION_SHIFT); + value |= phys; /* Add caching bits */ value |= option; @@ -45,13 +46,18 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } +void set_section_dcache(int section, enum dcache_option option) +{ + set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option); +} + __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) { debug("%s: Warning: not implemented\n", __func__); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, + size_t size, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE u64 *page_table = (u64 *)gd->arch.tlb_addr; @@ -70,8 +76,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); #endif - for (upto = start; upto < end; upto++) - set_section_dcache(upto, option); + for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE) + set_section_phys(upto, phys, option); /* * Make sure range is cache line aligned From patchwork Tue May 12 13:17:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 1288432 X-Patchwork-Delegate: matthias.bgg@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 header.s=mail20170921 header.b=hF9lU2CD; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49Lyzv3fxWz9sRR for ; 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Tue, 12 May 2020 13:18:06 +0000 (GMT) From: Marek Szyprowski To: u-boot@lists.denx.de Cc: Marek Szyprowski , Matthias Brugger , Tom Rini , Sylwester Nawrocki , marex@denx.de, bmeng.cn@gmail.com, nsaenzjulienne@suse.de, sjg@chromium.org, jh80.chung@samsung.com, b.zolnierkie@samsung.com Subject: [RFC PATCH 2/2] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit) Date: Tue, 12 May 2020 15:17:46 +0200 Message-Id: <20200512131746.22797-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200512131746.22797-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djPc7r8i3bFGbRNsbLYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFlMnbWa3eLu3k92B22N2w0UW j3mzTrB47Jx1l93j1YFV7B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGW8 XTaFsWC1SMWWPQ9ZGhi/CXQxcnJICJhInN19kg3EFhJYwSix4iF/FyMXkP2FUeL75/vMEInP jBLLOo1hGlZ23GWCKFrOKHH7xFYWuI6ju/eBjWITMJToetsFZosISEj86r/KCFLELLCCSeJz +2x2kISwQJrEquNvwIpYBFQljt5oZAKxeQVsJf5t/8YKsU5eYvWGA2BncArYSZw+eg1stYTA MnaJ7teboIpcJE7emMoCYQtLvDq+hR3ClpE4PbmHBaKhmVHi4bm17BBOD6PE5aYZjBBV1hJ3 zv0COoMD6D5NifW79CHCjhJTW6axgoQlBPgkbrwVBAkzA5mTtk1nhgjzSnS0CUFUq0nMOr4O bu3BC5eYIWwPifffDzNDQugwMISWTmGdwCg/C2HZAkbGVYziqaXFuempxYZ5qeV6xYm5xaV5 6XrJ+bmbGIGp5vS/4592MH69lHSIUYCDUYmHl6F2V5wQa2JZcWXuIUYJDmYlEd6WzJ1xQrwp iZVVqUX58UWlOanFhxilOViUxHmNF72MFRJITyxJzU5NLUgtgskycXBKNTDG75ebqXD7lqXC bhFN9laXt9yTk0zOOnnKm/rET1X+/mlX7NptCY4GdQebzqSdN1Tv2ra6VfNZpt51haLqmQLG e9fIlbacC1ouW6y6Sm39I97IvtodYbOvs+Zx9GXOCrNYsbKD6W6Qm/mt0LfPqgNVl+SW+Mz8 ZbfIVMFy/WaGnnrFI8/e/FJiKc5INNRiLipOBAC3cAn/MQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42I5/e/4PV3+RbviDC7OVLTYOGM9q8XUnniL G7/aWC3WHrnLbvGmrZHRYsHkJ6wW22YtZ7M4/Kad1eLblm2MFlMnbWa3eLu3k92B22N2w0UW j3mzTrB47Jx1l93j1YFV7B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GW8XTaFsWC1SMWWPQ9ZGhi/CXQx cnJICJhIrOy4y9TFyMUhJLCUUWLrvnesEAkZiZPTGqBsYYk/17rYIIo+MUqcXjUXLMEmYCjR 9RYkwckhIiAh8av/KiNIEbPAJiaJS3sXgCWEBVIk+lsnMYLYLAKqEkdvNDKB2LwCthL/tn+D 2iAvsXrDAWYQm1PATuL00WtgNUIC+RIrnl5imsDIt4CRYRWjSGppcW56brGRXnFibnFpXrpe cn7uJkZg6G879nPLDsaud8GHGAU4GJV4eCPqd8UJsSaWFVfmHmKU4GBWEuFtydwZJ8SbklhZ lVqUH19UmpNafIjRFOioicxSosn5wLjMK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5Ykpqd mlqQWgTTx8TBKdXAeO78wSP3wkx72tL333zILGZ/R3Hz7RlPv5/6MEPl4/FZ+4q/7Nzltazg xH5H5WW7VubLVJluebsnSercBMMJPavjJDnnn+G5nswzRb184oHdivsElvG7LdzhtfzhhHkq W1udpu82n/NEcFXitna/PUKtKvPOidnZ8VadDclO/dXSe+P1ZLMgcSUlluKMREMt5qLiRACs U4MWkwIAAA== X-CMS-MailID: 20200512131807eucas1p23959715b10a4e7ab36b60fd9791dae87 X-Msg-Generator: CA X-RootMTR: 20200512131807eucas1p23959715b10a4e7ab36b60fd9791dae87 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200512131807eucas1p23959715b10a4e7ab36b60fd9791dae87 References: <71b88bb9-7bfd-cb33-59b8-052c08ed33fa@suse.com> <20200512131746.22797-1-m.szyprowski@samsung.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski --- arch/arm/mach-bcm283x/Kconfig | 1 + arch/arm/mach-bcm283x/include/mach/base.h | 6 ++++++ arch/arm/mach-bcm283x/init.c | 14 ++++++++++++++ include/configs/rpi.h | 5 +++++ 4 files changed, 26 insertions(+) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 00419bf..bcb7f1d 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -36,6 +36,7 @@ config BCM2711_32B select BCM2711 select ARMV7_LPAE select CPU_V7A + select PHYS_64BIT config BCM2711_64B bool "Broadcom BCM2711 SoC 64-bit support" diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h index c4ae398..1bf89db 100644 --- a/arch/arm/mach-bcm283x/include/mach/base.h +++ b/arch/arm/mach-bcm283x/include/mach/base.h @@ -8,4 +8,10 @@ extern unsigned long rpi_bcm283x_base; +#ifdef CONFIG_ARMV7_LPAE +#include +#define phys_to_virt addrmap_phys_to_virt +#define virt_to_phys addrmap_virt_to_phys +#endif + #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 6a748da..4b9c831 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -145,6 +145,20 @@ int mach_cpu_init(void) } #ifdef CONFIG_ARMV7_LPAE +#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL +#include + +void init_addr_map(void) +{ + mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + DCACHE_OFF); + addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, + BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 0); +} + void enable_caches(void) { dcache_enable(); diff --git a/include/configs/rpi.h b/include/configs/rpi.h index b53a4b6..7da2cff 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -63,6 +63,11 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M #endif +#ifdef CONFIG_ARMV7_LPAE +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 2 +#endif + /* Devices */ /* GPIO */ #define CONFIG_BCM2835_GPIO