From patchwork Tue May 5 14:02:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283659 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=QPBVrk4u; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhKr4XV6z9sSk for ; Wed, 6 May 2020 00:04:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729316AbgEEODI (ORCPT ); Tue, 5 May 2020 10:03:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729087AbgEEODG (ORCPT ); Tue, 5 May 2020 10:03:06 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49214C061A10 for ; Tue, 5 May 2020 07:03:06 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id x25so2445589wmc.0 for ; Tue, 05 May 2020 07:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sewIQrOfMSMCFki5vvjbKoo8BkZz8WZa7NzooTrVnts=; b=QPBVrk4u8bJ1lyN89axq0pdEKOmmpYRibOzYW9nIG6R7g/9gJVFV6ctaT8iBdUKdvE UKqVm24R87Z+G6t4c+xieFb5HnHqsm9PsnsbYdN0/IyxhMLLe4qWBFTpRY3TR43BUQcJ HzgxxM2cfl7MZ1UnQnpI7YpljOD+ekvKio1Vrf5ofqLNPTGwEXk969k4GdrLGfJE+YI6 PN4xsD86VY0ZuN1aQ79VgYNhb+8eTQmmtA4T1F5cgaoJYzI/3CliI4iabK5wwv0kUU9r 2Y7kIDZwYPSIG28sAGkYE+hzu8hM25jTiyicyfN9DUB/qeO+jSjC8pHYvFRah7uIc5ph Y2Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sewIQrOfMSMCFki5vvjbKoo8BkZz8WZa7NzooTrVnts=; b=mo4u7kEAvueD4sz/wIAeSrFNviN1GrzFDGhEEUS74TZPA4HjUFYY9w1xMGJXc2G0lT g1I0cMJCS8HmWl+/TY5ZpbGKbtlrj9dSrDsZtdNBKFhUBYcZUhqMMgDEdwChDQ2eYRnn +GJePBh1YFrZ+OozLIjn0oCR55TRqskzdoglSZo7N4S6XWX3Kb+BELnyIUrO5O1L1DeR rqUbI3BkK9TQDniaFdEpI2uOgVpUKiHUO1RSOVDBDgkLaZbyFXA5N7N6nWIRLEeRx1Hr Fk5of/ruqFTqpbjJo8lLCa6MtCHxOfGTlZmCjNA7POl5bxhdlU91rWz+fVNt6jSy1BUa gg5w== X-Gm-Message-State: AGi0Pub+eXfyjZzVUrYWFOxT0FEOGB6wat+NM5/vlpEvLls/fsqcKeAS 62/n+uoOUI02q4BdGJKAP8Tfrw== X-Google-Smtp-Source: APiQypKH83ab6otRmwy18VhA5GKakhCU3ceSapgu6ZcYgX3DVNjT64ntS3hfln0YNJ+gri577CJFIA== X-Received: by 2002:a1c:f609:: with SMTP id w9mr3451354wmc.123.1588687385015; Tue, 05 May 2020 07:03:05 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:04 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 01/11] dt-bindings: add a binding document for MediaTek PERICFG controller Date: Tue, 5 May 2020 16:02:21 +0200 Message-Id: <20200505140231.16600-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski This adds a binding document for the PERICFG controller present on MediaTek SoCs. For now the only variant supported is 'mt8516-pericfg'. Signed-off-by: Bartosz Golaszewski --- .../arm/mediatek/mediatek,pericfg.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml new file mode 100644 index 000000000000..74b2a6173ffb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Peripheral Configuration Controller + +maintainers: + - Bartosz Golaszewski + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,pericfg + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pericfg: pericfg@10003050 { + compatible = "mediatek,mt8516-pericfg", "syscon"; + reg = <0 0x10003050 0 0x1000>; + }; From patchwork Tue May 5 14:02:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283648 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=exa1u54L; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhJd25qHz9sP7 for ; Wed, 6 May 2020 00:03:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729336AbgEEODL (ORCPT ); Tue, 5 May 2020 10:03:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729247AbgEEODI (ORCPT ); Tue, 5 May 2020 10:03:08 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BA9DC061A10 for ; Tue, 5 May 2020 07:03:08 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id g12so2468290wmh.3 for ; Tue, 05 May 2020 07:03:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1RBYv7clwofuc4RomuNetMbXz5K8VN7BlCrpLgWGuKQ=; b=exa1u54LNh7NcTBkr9fjj1LtLgzCEkb41a3/XAcPpRhDL8uYlIw1yKBcaC3npPnAq+ iNlvvzM/LMlufPMoM4dQZJ662snagyOfwpwmeJEqzq61YYz64HYeJRj+t1eanmoFGCCm ddLdtP3LKdxRSHIxe+vrvt/nhHYJVAn1o3UPfgDEWejxezv/4+QjsbqAvxgBe7whd+5j 77G9QNzigkGdn3zaHrl1amKuP74s0sgTujd8o+/gAP4984gyy9fEV9GjDIQFQWbcI7X3 11cm8fOu0E7dE+1WWNOwcnos+18bfhkHGHvtTqVQaqq7TSYiyOSef5MYIBHFOkOkZSnf cUQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1RBYv7clwofuc4RomuNetMbXz5K8VN7BlCrpLgWGuKQ=; b=dUQ8cRdqOT6HHdk+DxFwdzvfgvmtUqqwHlALKfIm4ht0ZV0VUWbbVBlHQVU4ucZR3P vsvvrbRwI+peDTS0zIlFxlv8BEg9Q3dO7ojx6OtLLzfGjdbRliJdMXyyessOA5lUc8B1 0wFn3nsBh1Y78k70hrWh2vyckWJHotG9NkNXRf215SfxwKswk2PYxrT4opX7oFSvhqZK bpDPl8xMAizzt1aecpt+X1uwQXWjLn+VWoj/vxAt9YRdJbQFqcXM1B7XzfsGN9THFMWs skeiSQ+V64OZb4vElr+3gOOjr6a3NYWWd7G8Vg+OaEo1r41h+Ho/F352JzE4tm3LWcZu wHuw== X-Gm-Message-State: AGi0PubQ25IyOnsgHJvpuGmkSBXvpzBcctPwfXMKg8xU8p/lLmtu3p/N XN6Tes9XTnEhuiC7pbPlHY8JFg== X-Google-Smtp-Source: APiQypKyODJ/h2tkRj/3s4Rn7dN4YkXrc4seYlCWxagOZmnAKutgDsCqy57VDKSasTPAC6+hVxwWqw== X-Received: by 2002:a1c:9c0a:: with SMTP id f10mr3688664wme.139.1588687386996; Tue, 05 May 2020 07:03:06 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:06 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 02/11] dt-bindings: new: add yaml bindings for MediaTek Ethernet MAC Date: Tue, 5 May 2020 16:02:22 +0200 Message-Id: <20200505140231.16600-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski This adds yaml DT bindings for the MediaTek Ethernet MAC present on the mt8* family of SoCs. Signed-off-by: Bartosz Golaszewski --- .../bindings/net/mediatek,eth-mac.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml new file mode 100644 index 000000000000..7682fe9d8109 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mediatek,eth-mac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Ethernet MAC Controller + +maintainers: + - Bartosz Golaszewski + +description: + This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. + It's compliant with 802.3 standards and supports half- and full-duplex + modes with flow-control as well as CRC offloading and VLAN tags. + +properties: + compatible: + enum: + - mediatek,mt8516-eth + - mediatek,mt8518-eth + - mediatek,mt8175-eth + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + additionalItems: false + items: + - const: core + - const: reg + - const: trans + + mediatek,pericfg: + $ref: /schemas/types.yaml#definitions/phandle + description: + Phandle to the device containing the PERICFG register range. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - mediatek,pericfg + - phy-handle + +examples: + - | + #include + #include + + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0 0x11180000 0 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; + }; From patchwork Tue May 5 14:02:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283658 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; 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[2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:07 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 03/11] net: ethernet: mediatek: rename Kconfig prompt Date: Tue, 5 May 2020 16:02:23 +0200 Message-Id: <20200505140231.16600-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski We'll soon by adding a second MediaTek Ethernet driver so modify the Kconfig prompt. Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/mediatek/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig index 4968352ba188..5079b8090f16 100644 --- a/drivers/net/ethernet/mediatek/Kconfig +++ b/drivers/net/ethernet/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only config NET_VENDOR_MEDIATEK - bool "MediaTek ethernet driver" + bool "MediaTek devices" depends on ARCH_MEDIATEK || SOC_MT7621 || SOC_MT7620 ---help--- If you have a Mediatek SoC with ethernet, say Y. From patchwork Tue May 5 14:02:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283650 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=ezkHqFr+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhJj0jdtz9sSk for ; Wed, 6 May 2020 00:03:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729357AbgEEODP (ORCPT ); Tue, 5 May 2020 10:03:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729338AbgEEODL (ORCPT ); Tue, 5 May 2020 10:03:11 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEA7FC0610D5 for ; Tue, 5 May 2020 07:03:10 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id z6so2491754wml.2 for ; Tue, 05 May 2020 07:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=75HMiSxkO2iGkQyQ4GVIN4XRI1pdsKTRs1XUFo380Tg=; b=ezkHqFr+hwvoCUtODTn4bBFeBlly8HWvJiblO2xXxesyL1/DLZmDW9fWmLJy7I2RQr z4/XNFhycXjhViK/BtzNr49/HW22OGYzoaHSo6ikn+HA9TUGYGli4gQkHpqtEr2bTpYA yLqoD0FHi+vSoCHjSuXExIZJhGpSCZTAG0sV4/ATtjgUJmbj1QRCYqjecaYdkoQzH5+V 8JoTWUO+/cc22OXSb3qfzo0V8+qGZc1XoFvMhJN3sR80zAAuS6l5SlPTJ5F5tMVyWHcn v3iKjJkQoYARwNCRLfmlHgh7MJVBQOH4mgE7mBdrIK5lphaZhbbBqRK6JZ4soEZ+4q0N QkcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=75HMiSxkO2iGkQyQ4GVIN4XRI1pdsKTRs1XUFo380Tg=; b=Pv0UOAjuBxe7PvPo5SFRbH2+qlYVCIDyJi18CQcnTt1msB9A+e3gKYP5xkbaB9erU6 BlNf+eekv57YbC0NQIKS54Z9J1xtwGJsAIciZjDsoLFn5GhXfqpUJKSDe/zINamti9yF qk6GznmEuhWcA4MWYz7v6FtFmUtFhbWX5Cf1ZEIuWsrF9F5Zw6bfzQa0ESSAbzKIgQbT 5jL4MDMIN/gJqcw65nkhhXQ+rQLCnhwYCTv6jyrfr6kkdZYPrh7TPkZjWzMElZEub4yX tT63tAt6smCYVd1dBprJLgYH7UJ/dPAs9RqO9mgiOZ/Ly8z+P0RbkfnEGAiwchNz58d+ 2nsQ== X-Gm-Message-State: AGi0PuZg+oqkCli6pUzrsNElpDD8Idlhsg5OLE4xiSuhpICqwtUZRG2E nGCxmAO2CD8VSrsqy5zI0C9yvQ== X-Google-Smtp-Source: APiQypInGXnY7PvS5QaUhdwBc8tu5ppIGoSSB01va3t8HjUU2Ty34gk2vT4nfcEtZEackOyvGp/6MQ== X-Received: by 2002:a1c:a7c2:: with SMTP id q185mr3740385wme.42.1588687389697; Tue, 05 May 2020 07:03:09 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:09 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 04/11] net: ethernet: mediatek: remove unnecessary spaces from Makefile Date: Tue, 5 May 2020 16:02:24 +0200 Message-Id: <20200505140231.16600-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski The Makefile formatting in the kernel tree usually doesn't use tabs, so remove them before we add a second driver. Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/mediatek/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile index 2d8362f9341b..3362fb7ef859 100644 --- a/drivers/net/ethernet/mediatek/Makefile +++ b/drivers/net/ethernet/mediatek/Makefile @@ -3,5 +3,5 @@ # Makefile for the Mediatek SoCs built-in ethernet macs # -obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o +obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o From patchwork Tue May 5 14:02:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283657 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=GDxtZasc; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhKX0Q6Qz9sT1 for ; Wed, 6 May 2020 00:04:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729462AbgEEOD7 (ORCPT ); Tue, 5 May 2020 10:03:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729342AbgEEODN (ORCPT ); Tue, 5 May 2020 10:03:13 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78F1BC061A41 for ; Tue, 5 May 2020 07:03:12 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id h4so2433438wmb.4 for ; Tue, 05 May 2020 07:03:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XzPWSx814wcuOT9NHWlCidvd/g1LktIvgEhNgxHiB+I=; b=GDxtZascuF3VlQT4m8Y6A1NkqjEZJvqBKtGLerb8p0fVRxeFRWzsMAW/5kQknif1ol QbdmDFCp8Mm2vnHZsZ3ljrAqdFInnVvc5tKZPRq0UtbxKz1LZzSwBH2EST0Pj3gT1b8c h9MdIkBbk4f2IccDCFRiwKmEBA+jjiL96/9D+qaMGQOTRwtWJawUr2fPysWASK4UBcTb qaT4zA2gWzkLAbQET4wIE3RVpXzAknkEoA1mk5kfb9c18lSq6eC79m7KDyfNVK2iDXGr mFHe23qvpwQEcQVze2B+B+8DL+ADNtS4Zqm07JpzqaF8kdRW50BzHgDtIEVZTIjtKOLC nvWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XzPWSx814wcuOT9NHWlCidvd/g1LktIvgEhNgxHiB+I=; b=F+6261zhs0p4MjxHGaky1CMvJ+oE9Yd+WMKTYUXRJuXt5LXMwmWRH66now2OLNTP9H R/uEAnKEj91rF4CHtDneqbuHhWk2CMcHZd/Sv7dgX/mRrY4cPvLGyR1bJSFpoQN/RuIo +ivPP2iDQpU0DTHMHDrJNINl7Ini6+T1MUW3BGCzOnkmeZGE2S/iNPbDiQVqYqapl72L NUYQM6sFflqSOtFcRS7QK2d1NYYWAecNg7AZkjyWNncjtYxdSeA/t578oJVb2qT7UfqC uMO58Wr7MeUd/akxUBNsq+nIzAj9n+NuFuKFhDCc5OA6xvN/tI8xnREjNe2Uv1L5w6mP zaoQ== X-Gm-Message-State: AGi0PuY78VV2kuvvfBfaptEG6/RhFYh3UVtFQchPEyuqdVZ077tyX1On tmh1Tx4sBb8S0fvgKkVJAtG6IzagXbI= X-Google-Smtp-Source: APiQypLyQEevQilQF8OGTKaO4x0GDcOOIERMs4KyEuSeUMTmGpGiba4gEr4LNVjh4GeSyFodlYbUjw== X-Received: by 2002:a1c:ed04:: with SMTP id l4mr3707524wmh.93.1588687391128; Tue, 05 May 2020 07:03:11 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:10 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 05/11] net: core: provide devm_register_netdev() Date: Tue, 5 May 2020 16:02:25 +0200 Message-Id: <20200505140231.16600-6-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski Provide devm_register_netdev() - a device resource managed variant of register_netdev(). This new helper will only work for net_device structs that have a parent device assigned and are devres managed too. Signed-off-by: Bartosz Golaszewski --- include/linux/netdevice.h | 4 ++++ net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++ net/ethernet/eth.c | 1 + 3 files changed, 53 insertions(+) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 130a668049ab..433bd5ca2efc 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1515,6 +1515,8 @@ struct net_device_ops { * @IFF_FAILOVER_SLAVE: device is lower dev of a failover master device * @IFF_L3MDEV_RX_HANDLER: only invoke the rx handler of L3 master device * @IFF_LIVE_RENAME_OK: rename is allowed while device is up and running + * @IFF_IS_DEVRES: this structure was allocated dynamically and is managed by + * devres */ enum netdev_priv_flags { IFF_802_1Q_VLAN = 1<<0, @@ -1548,6 +1550,7 @@ enum netdev_priv_flags { IFF_FAILOVER_SLAVE = 1<<28, IFF_L3MDEV_RX_HANDLER = 1<<29, IFF_LIVE_RENAME_OK = 1<<30, + IFF_IS_DEVRES = 1<<31, }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -4206,6 +4209,7 @@ struct net_device *alloc_netdev_mqs(int sizeof_priv, const char *name, count) int register_netdev(struct net_device *dev); +int devm_register_netdev(struct net_device *ndev); void unregister_netdev(struct net_device *dev); /* General hardware address lists handling functions */ diff --git a/net/core/dev.c b/net/core/dev.c index 522288177bbd..99db537c9468 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9519,6 +9519,54 @@ int register_netdev(struct net_device *dev) } EXPORT_SYMBOL(register_netdev); +struct netdevice_devres { + struct net_device *ndev; +}; + +static void devm_netdev_release(struct device *dev, void *this) +{ + struct netdevice_devres *res = this; + + unregister_netdev(res->ndev); +} + +/** + * devm_register_netdev - resource managed variant of register_netdev() + * @ndev: device to register + * + * This is a devres variant of register_netdev() for which the unregister + * function will be call automatically when the parent device of ndev + * is detached. + */ +int devm_register_netdev(struct net_device *ndev) +{ + struct netdevice_devres *dr; + int ret; + + /* struct net_device itself must be devres managed. */ + BUG_ON(!(ndev->priv_flags & IFF_IS_DEVRES)); + /* struct net_device must have a parent device - it will be the device + * managing this resource. + */ + BUG_ON(!ndev->dev.parent); + + dr = devres_alloc(devm_netdev_release, sizeof(*dr), GFP_KERNEL); + if (!dr) + return -ENOMEM; + + ret = register_netdev(ndev); + if (ret) { + devres_free(dr); + return ret; + } + + dr->ndev = ndev; + devres_add(ndev->dev.parent, dr); + + return 0; +} +EXPORT_SYMBOL(devm_register_netdev); + int netdev_refcnt_read(const struct net_device *dev) { int i, refcnt = 0; diff --git a/net/ethernet/eth.c b/net/ethernet/eth.c index c8b903302ff2..ce9b5e576f20 100644 --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c @@ -423,6 +423,7 @@ struct net_device *devm_alloc_etherdev_mqs(struct device *dev, int sizeof_priv, *dr = netdev; devres_add(dev, dr); + netdev->priv_flags |= IFF_IS_DEVRES; return netdev; } From patchwork Tue May 5 14:02:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283656 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; 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[2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:11 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 06/11] net: ethernet: mtk-eth-mac: new driver Date: Tue, 5 May 2020 16:02:26 +0200 Message-Id: <20200505140231.16600-7-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski This adds the driver for the MediaTek Ethernet MAC used on the MT8* SoC family. For now we only support full-duplex. Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/mediatek/Kconfig | 6 + drivers/net/ethernet/mediatek/Makefile | 1 + drivers/net/ethernet/mediatek/mtk_eth_mac.c | 1476 +++++++++++++++++++ 3 files changed, 1483 insertions(+) create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_mac.c diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig index 5079b8090f16..5c3793076765 100644 --- a/drivers/net/ethernet/mediatek/Kconfig +++ b/drivers/net/ethernet/mediatek/Kconfig @@ -14,4 +14,10 @@ config NET_MEDIATEK_SOC This driver supports the gigabit ethernet MACs in the MediaTek SoC family. +config NET_MEDIATEK_MAC + tristate "MediaTek Ethernet MAC support" + select PHYLIB + help + This driver supports the ethernet IP on MediaTek MT85** SoCs. + endif #NET_VENDOR_MEDIATEK diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile index 3362fb7ef859..f7f5638943a0 100644 --- a/drivers/net/ethernet/mediatek/Makefile +++ b/drivers/net/ethernet/mediatek/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o +obj-$(CONFIG_NET_MEDIATEK_MAC) += mtk_eth_mac.o diff --git a/drivers/net/ethernet/mediatek/mtk_eth_mac.c b/drivers/net/ethernet/mediatek/mtk_eth_mac.c new file mode 100644 index 000000000000..e6e796e65228 --- /dev/null +++ b/drivers/net/ethernet/mediatek/mtk_eth_mac.c @@ -0,0 +1,1476 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 MediaTek Corporation + * Copyright (c) 2020 BayLibre SAS + * + * Author: Bartosz Golaszewski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_MAC_DRVNAME "mtk_eth_mac" +#define MTK_MAC_VERSION "1.0" + +#define MTK_MAC_WAIT_TIMEOUT 300 +#define MTK_MAC_MAX_FRAME_SIZE 1514 +#define MTK_MAC_SKB_ALIGNMENT 16 +#define MTK_MAC_NAPI_WEIGHT 64 +#define MTK_MAC_HASHTABLE_MC_LIMIT 256 +#define MTK_MAC_HASHTABLE_SIZE_MAX 512 + +static const char *const mtk_mac_clk_names[] = { "core", "reg", "trans" }; +#define MTK_MAC_NCLKS ARRAY_SIZE(mtk_mac_clk_names) + +/* PHY Control Register 0 */ +#define MTK_MAC_REG_PHY_CTRL0 0x0000 +#define MTK_MAC_BIT_PHY_CTRL0_WTCMD BIT(13) +#define MTK_MAC_BIT_PHY_CTRL0_RDCMD BIT(14) +#define MTK_MAC_BIT_PHY_CTRL0_RWOK BIT(15) +#define MTK_MAC_MSK_PHY_CTRL0_PREG GENMASK(12, 8) +#define MTK_MAC_OFF_PHY_CTRL0_PREG 8 +#define MTK_MAC_MSK_PHY_CTRL0_RWDATA GENMASK(31, 16) +#define MTK_MAC_OFF_PHY_CTRL0_RWDATA 16 + +/* PHY Control Register 1 */ +#define MTK_MAC_REG_PHY_CTRL1 0x0004 +#define MTK_MAC_BIT_PHY_CTRL1_LINK_ST BIT(0) +#define MTK_MAC_BIT_PHY_CTRL1_AN_EN BIT(8) +#define MTK_MAC_OFF_PHY_CTRL1_FORCE_SPD 9 +#define MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_10M 0x00 +#define MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_100M 0x01 +#define MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_1000M 0x02 +#define MTK_MAC_BIT_PHY_CTRL1_FORCE_DPX BIT(11) +#define MTK_MAC_BIT_PHY_CTRL1_FORCE_FC_RX BIT(12) +#define MTK_MAC_BIT_PHY_CTRL1_FORCE_FC_TX BIT(13) + +/* MAC Configuration Register */ +#define MTK_MAC_REG_MAC_CFG 0x0008 +#define MTK_MAC_OFF_MAC_CFG_IPG 10 +#define MTK_MAC_VAL_MAC_CFG_IPG_96BIT GENMASK(4, 0) +#define MTK_MAC_BIT_MAC_CFG_MAXLEN_1522 BIT(16) +#define MTK_MAC_BIT_MAC_CFG_AUTO_PAD BIT(19) +#define MTK_MAC_BIT_MAC_CFG_CRC_STRIP BIT(20) +#define MTK_MAC_BIT_MAC_CFG_VLAN_STRIP BIT(22) +#define MTK_MAC_BIT_MAC_CFG_NIC_PD BIT(31) + +/* Flow-Control Configuration Register */ +#define MTK_MAC_REG_FC_CFG 0x000c +#define MTK_MAC_BIT_FC_CFG_BP_EN BIT(7) +#define MTK_MAC_BIT_FC_CFG_UC_PAUSE_DIR BIT(8) +#define MTK_MAC_OFF_FC_CFG_SEND_PAUSE_TH 16 +#define MTK_MAC_VAL_FC_CFG_SEND_PAUSE_TH_2K 0x800 + +/* ARL Configuration Register */ +#define MTK_MAC_REG_ARL_CFG 0x0010 +#define MTK_MAC_BIT_ARL_CFG_HASH_ALG BIT(0) +#define MTK_MAC_BIT_ARL_CFG_MISC_MODE BIT(4) + +/* MAC High and Low Bytes Registers */ +#define MTK_MAC_REG_MY_MAC_H 0x0014 +#define MTK_MAC_REG_MY_MAC_L 0x0018 + +/* Hash Table Control Register */ +#define MTK_MAC_REG_HASH_CTRL 0x001c +#define MTK_MAC_MSK_HASH_CTRL_HASH_BIT_ADDR GENMASK(8, 0) +#define MTK_MAC_BIT_HASH_CTRL_HASH_BIT_DATA BIT(12) +#define MTK_MAC_BIT_HASH_CTRL_ACC_CMD BIT(13) +#define MTK_MAC_BIT_HASH_CTRL_CMD_START BIT(14) +#define MTK_MAC_BIT_HASH_CTRL_BIST_EN BIT(31) + +/* TX DMA Control Register */ +#define MTK_MAC_REG_TX_DMA_CTRL 0x0034 +#define MTK_MAC_BIT_TX_DMA_CTRL_START BIT(0) +#define MTK_MAC_BIT_TX_DMA_CTRL_STOP BIT(1) +#define MTK_MAC_BIT_TX_DMA_CTRL_RESUME BIT(2) + +/* RX DMA Control Register */ +#define MTK_MAC_REG_RX_DMA_CTRL 0x0038 +#define MTK_MAC_BIT_RX_DMA_CTRL_START BIT(0) +#define MTK_MAC_BIT_RX_DMA_CTRL_STOP BIT(1) +#define MTK_MAC_BIT_RX_DMA_CTRL_RESUME BIT(2) + +/* DMA Address Registers */ +#define MTK_MAC_REG_TX_DPTR 0x003c +#define MTK_MAC_REG_RX_DPTR 0x0040 +#define MTK_MAC_REG_TX_BASE_ADDR 0x0044 +#define MTK_MAC_REG_RX_BASE_ADDR 0x0048 + +/* Interrupt Status Register */ +#define MTK_MAC_REG_INT_STS 0x0050 +#define MTK_MAC_REG_INT_STS_PORT_STS_CHG BIT(2) +#define MTK_MAC_REG_INT_STS_MIB_CNT_TH BIT(3) +#define MTK_MAC_BIT_INT_STS_FNRC BIT(6) +#define MTK_MAC_BIT_INT_STS_TNTC BIT(8) + +/* Interrupt Mask Register */ +#define MTK_MAC_REG_INT_MASK 0x0054 +#define MTK_MAC_BIT_INT_MASK_FNRC BIT(6) + +/* Misc. Config Register */ +#define MTK_MAC_REG_TEST1 0x005c +#define MTK_MAC_BIT_TEST1_RST_HASH_MBIST BIT(31) + +/* Extended Configuration Register */ +#define MTK_MAC_REG_EXT_CFG 0x0060 +#define MTK_MAC_OFF_EXT_CFG_SND_PAUSE_RLS 16 +#define MTK_MAC_VAL_EXT_CFG_SND_PAUSE_RLS_1K 0x400 + +/* EthSys Configuration Register */ +#define MTK_MAC_REG_SYS_CONF 0x0094 +#define MTK_MAC_BIT_MII_PAD_OUT_ENABLE BIT(0) +#define MTK_MAC_BIT_EXT_MDC_MODE BIT(1) +#define MTK_MAC_BIT_SWC_MII_MODE BIT(2) + +/* MAC Clock Configuration Register */ +#define MTK_MAC_REG_MAC_CLK_CONF 0x00ac +#define MTK_MAC_MSK_MAC_CLK_CONF GENMASK(7, 0) +#define MTK_MAC_BIT_CLK_DIV_10 0x0a + +/* Counter registers. */ +#define MTK_MAC_REG_C_RXOKPKT 0x0100 +#define MTK_MAC_REG_C_RXOKBYTE 0x0104 +#define MTK_MAC_REG_C_RXRUNT 0x0108 +#define MTK_MAC_REG_C_RXLONG 0x010c +#define MTK_MAC_REG_C_RXDROP 0x0110 +#define MTK_MAC_REG_C_RXCRC 0x0114 +#define MTK_MAC_REG_C_RXARLDROP 0x0118 +#define MTK_MAC_REG_C_RXVLANDROP 0x011c +#define MTK_MAC_REG_C_RXCSERR 0x0120 +#define MTK_MAC_REG_C_RXPAUSE 0x0124 +#define MTK_MAC_REG_C_TXOKPKT 0x0128 +#define MTK_MAC_REG_C_TXOKBYTE 0x012c +#define MTK_MAC_REG_C_TXPAUSECOL 0x0130 +#define MTK_MAC_REG_C_TXRTY 0x0134 +#define MTK_MAC_REG_C_TXSKIP 0x0138 +#define MTK_MAC_REG_C_TX_ARP 0x013c +#define MTK_MAC_REG_C_RX_RERR 0x01d8 +#define MTK_MAC_REG_C_RX_UNI 0x01dc +#define MTK_MAC_REG_C_RX_MULTI 0x01e0 +#define MTK_MAC_REG_C_RX_BROAD 0x01e4 +#define MTK_MAC_REG_C_RX_ALIGNERR 0x01e8 +#define MTK_MAC_REG_C_TX_UNI 0x01ec +#define MTK_MAC_REG_C_TX_MULTI 0x01f0 +#define MTK_MAC_REG_C_TX_BROAD 0x01f4 +#define MTK_MAC_REG_C_TX_TIMEOUT 0x01f8 +#define MTK_MAC_REG_C_TX_LATECOL 0x01fc +#define MTK_MAC_REG_C_RX_LENGTHERR 0x0214 +#define MTK_MAC_REG_C_RX_TWIST 0x0218 + +/* Ethernet CFG Control */ +#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 +#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) + +/* Represents the actual structure of descriptors used by the MAC. We can + * reuse the same structure for both TX and RX - the layout is the same, only + * the flags differ slightly. + */ +struct mtk_mac_ring_desc { + /* Contains both the status flags as well as packet length. */ + u32 status; + u32 data_ptr; + u32 vtag; + u32 reserved; +} __aligned(4) __packed; + +#define MTK_MAC_DESC_MSK_LEN GENMASK(15, 0) +#define MTK_MAC_DESC_BIT_RX_CRCE BIT(24) +#define MTK_MAC_DESC_BIT_RX_OSIZE BIT(25) +#define MTK_MAC_DESC_BIT_INT BIT(27) +#define MTK_MAC_DESC_BIT_LS BIT(28) +#define MTK_MAC_DESC_BIT_FS BIT(29) +#define MTK_MAC_DESC_BIT_EOR BIT(30) +#define MTK_MAC_DESC_BIT_COWN BIT(31) + +/* Helper structure for storing data read from/written to descriptors in order + * to limit reads from/writes to DMA memory. + */ +struct mtk_mac_ring_desc_data { + unsigned int len; + unsigned int flags; + dma_addr_t dma_addr; + struct sk_buff *skb; +}; + +#define MTK_MAC_RING_NUM_DESCS 128 +#define MTK_MAC_NUM_TX_DESCS MTK_MAC_RING_NUM_DESCS +#define MTK_MAC_NUM_RX_DESCS MTK_MAC_RING_NUM_DESCS +#define MTK_MAC_NUM_DESCS_TOTAL (MTK_MAC_RING_NUM_DESCS * 2) +#define MTK_MAC_DMA_SIZE \ + (MTK_MAC_NUM_DESCS_TOTAL * sizeof(struct mtk_mac_ring_desc)) + +struct mtk_mac_ring { + struct mtk_mac_ring_desc *descs; + struct sk_buff *skbs[MTK_MAC_RING_NUM_DESCS]; + unsigned int head; + unsigned int tail; + unsigned int count; +}; + +struct mtk_mac_priv { + struct regmap *regs; + struct regmap *pericfg; + + struct clk_bulk_data clks[MTK_MAC_NCLKS]; + + void *ring_base; + struct mtk_mac_ring_desc *descs_base; + dma_addr_t dma_addr; + struct mtk_mac_ring tx_ring; + struct mtk_mac_ring rx_ring; + struct work_struct tx_work; + + struct mii_bus *mii; + struct napi_struct napi; + + struct device_node *phy_node; + phy_interface_t phy_intf; + struct phy_device *phydev; + unsigned int link; + int speed; + int duplex; + + /* Protects against concurrent descriptor access. */ + spinlock_t lock; + unsigned long lock_flags; + + struct rtnl_link_stats64 stats; +}; + +static struct net_device *mtk_mac_get_netdev(struct mtk_mac_priv *priv) +{ + char *ptr = (char *)priv; + + return (struct net_device *)(ptr - ALIGN(sizeof(struct net_device), + NETDEV_ALIGN)); +} + +static struct device *mtk_mac_get_dev(struct mtk_mac_priv *priv) +{ + struct net_device *ndev = mtk_mac_get_netdev(priv); + + return ndev->dev.parent; +} + +static const struct regmap_config mtk_mac_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static void mtk_mac_ring_init(struct mtk_mac_ring *ring, + struct mtk_mac_ring_desc *descs, + unsigned int start_count) +{ + memset(ring, 0, sizeof(*ring)); + ring->descs = descs; + ring->head = 0; + ring->tail = 0; + ring->count = start_count; +} + +static int mtk_mac_ring_pop_tail(struct mtk_mac_ring *ring, + struct mtk_mac_ring_desc_data *desc_data) +{ + struct mtk_mac_ring_desc *desc = &ring->descs[ring->tail]; + unsigned int status; + + dma_rmb(); + status = desc->status; + + if (!(status & MTK_MAC_DESC_BIT_COWN)) + return -1; + + desc_data->len = status & MTK_MAC_DESC_MSK_LEN; + desc_data->flags = status & ~MTK_MAC_DESC_MSK_LEN; + desc_data->dma_addr = desc->data_ptr; + desc_data->skb = ring->skbs[ring->tail]; + + desc->data_ptr = 0; + desc->status = MTK_MAC_DESC_BIT_COWN; + if (status & MTK_MAC_DESC_BIT_EOR) + desc->status |= MTK_MAC_DESC_BIT_EOR; + + dma_wmb(); + + ring->tail = (ring->tail + 1) % MTK_MAC_RING_NUM_DESCS; + ring->count--; + + return 0; +} + +static void mtk_mac_ring_push_head(struct mtk_mac_ring *ring, + struct mtk_mac_ring_desc_data *desc_data, + unsigned int flags) +{ + struct mtk_mac_ring_desc *desc = &ring->descs[ring->head]; + unsigned int status; + + dma_rmb(); + status = desc->status; + + ring->skbs[ring->head] = desc_data->skb; + desc->data_ptr = desc_data->dma_addr; + + status |= desc_data->len; + if (flags) + status |= flags; + desc->status = status; + + dma_wmb(); + desc->status &= ~MTK_MAC_DESC_BIT_COWN; + + ring->head = (ring->head + 1) % MTK_MAC_RING_NUM_DESCS; + ring->count++; +} + +static void mtk_mac_ring_push_head_rx(struct mtk_mac_ring *ring, + struct mtk_mac_ring_desc_data *desc_data) +{ + mtk_mac_ring_push_head(ring, desc_data, 0); +} + +static void mtk_mac_ring_push_head_tx(struct mtk_mac_ring *ring, + struct mtk_mac_ring_desc_data *desc_data) +{ + static const unsigned int flags = MTK_MAC_DESC_BIT_FS | + MTK_MAC_DESC_BIT_LS | + MTK_MAC_DESC_BIT_INT; + + mtk_mac_ring_push_head(ring, desc_data, flags); +} + +static bool mtk_mac_ring_full(struct mtk_mac_ring *ring) +{ + return ring->count == MTK_MAC_RING_NUM_DESCS; +} + +static bool mtk_mac_ring_descs_available(struct mtk_mac_ring *ring) +{ + return ring->count > 0; +} + +static void mtk_mac_lock(struct mtk_mac_priv *priv) +{ + spin_lock_irqsave(&priv->lock, priv->lock_flags); +} + +static void mtk_mac_unlock(struct mtk_mac_priv *priv) +{ + spin_unlock_irqrestore(&priv->lock, priv->lock_flags); +} + +static dma_addr_t mtk_mac_dma_map_rx(struct mtk_mac_priv *priv, + struct sk_buff *skb) +{ + struct device *dev = mtk_mac_get_dev(priv); + + /* Data pointer for the RX DMA descriptor must be aligned to 4N + 2. */ + return dma_map_single(dev, skb_tail_pointer(skb) - 2, + skb_tailroom(skb), DMA_FROM_DEVICE); +} + +static void mtk_mac_dma_unmap_rx(struct mtk_mac_priv *priv, + struct mtk_mac_ring_desc_data *desc_data) +{ + struct device *dev = mtk_mac_get_dev(priv); + + dma_unmap_single(dev, desc_data->dma_addr, + skb_tailroom(desc_data->skb), DMA_FROM_DEVICE); +} + +static dma_addr_t mtk_mac_dma_map_tx(struct mtk_mac_priv *priv, + struct sk_buff *skb) +{ + struct device *dev = mtk_mac_get_dev(priv); + + return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); +} + +static void mtk_mac_dma_unmap_tx(struct mtk_mac_priv *priv, + struct mtk_mac_ring_desc_data *desc_data) +{ + struct device *dev = mtk_mac_get_dev(priv); + + return dma_unmap_single(dev, desc_data->dma_addr, + desc_data->len, DMA_TO_DEVICE); +} + +static void mtk_mac_nic_disable_pd(struct mtk_mac_priv *priv) +{ + regmap_update_bits(priv->regs, MTK_MAC_REG_MAC_CFG, + MTK_MAC_BIT_MAC_CFG_NIC_PD, 0); +} + +static void mtk_mac_intr_unmask_all(struct mtk_mac_priv *priv) +{ + regmap_write(priv->regs, MTK_MAC_REG_INT_MASK, 0); +} + +static void mtk_mac_intr_mask_all(struct mtk_mac_priv *priv) +{ + regmap_write(priv->regs, MTK_MAC_REG_INT_MASK, ~0); +} + +static unsigned int mtk_mac_intr_read_and_clear(struct mtk_mac_priv *priv) +{ + unsigned int val; + + regmap_read(priv->regs, MTK_MAC_REG_INT_STS, &val); + regmap_write(priv->regs, MTK_MAC_REG_INT_STS, val); + + return val; +} + +static void mtk_mac_dma_init(struct mtk_mac_priv *priv) +{ + struct mtk_mac_ring_desc *desc; + unsigned int val; + int i; + + priv->descs_base = (struct mtk_mac_ring_desc *)priv->ring_base; + + for (i = 0; i < MTK_MAC_NUM_DESCS_TOTAL; i++) { + desc = &priv->descs_base[i]; + + memset(desc, 0, sizeof(*desc)); + desc->status = MTK_MAC_DESC_BIT_COWN; + if ((i == MTK_MAC_NUM_TX_DESCS - 1) || + (i == MTK_MAC_NUM_DESCS_TOTAL - 1)) + desc->status |= MTK_MAC_DESC_BIT_EOR; + } + + mtk_mac_ring_init(&priv->tx_ring, priv->descs_base, 0); + mtk_mac_ring_init(&priv->rx_ring, + priv->descs_base + MTK_MAC_NUM_TX_DESCS, + MTK_MAC_NUM_RX_DESCS); + + /* Set DMA pointers. */ + val = (unsigned int)priv->dma_addr; + regmap_write(priv->regs, MTK_MAC_REG_TX_BASE_ADDR, val); + regmap_write(priv->regs, MTK_MAC_REG_TX_DPTR, val); + + val += sizeof(struct mtk_mac_ring_desc) * MTK_MAC_NUM_TX_DESCS; + regmap_write(priv->regs, MTK_MAC_REG_RX_BASE_ADDR, val); + regmap_write(priv->regs, MTK_MAC_REG_RX_DPTR, val); +} + +static void mtk_mac_dma_start(struct mtk_mac_priv *priv) +{ + regmap_update_bits(priv->regs, MTK_MAC_REG_TX_DMA_CTRL, + MTK_MAC_BIT_TX_DMA_CTRL_START, + MTK_MAC_BIT_TX_DMA_CTRL_START); + regmap_update_bits(priv->regs, MTK_MAC_REG_RX_DMA_CTRL, + MTK_MAC_BIT_RX_DMA_CTRL_START, + MTK_MAC_BIT_RX_DMA_CTRL_START); +} + +static void mtk_mac_dma_stop(struct mtk_mac_priv *priv) +{ + regmap_write(priv->regs, MTK_MAC_REG_TX_DMA_CTRL, + MTK_MAC_BIT_TX_DMA_CTRL_STOP); + regmap_write(priv->regs, MTK_MAC_REG_RX_DMA_CTRL, + MTK_MAC_BIT_RX_DMA_CTRL_STOP); +} + +static void mtk_mac_dma_disable(struct mtk_mac_priv *priv) +{ + int i; + + mtk_mac_dma_stop(priv); + + /* Take back all descriptors. */ + for (i = 0; i < MTK_MAC_NUM_DESCS_TOTAL; i++) + priv->descs_base[i].status |= MTK_MAC_DESC_BIT_COWN; +} + +static void mtk_mac_dma_resume_rx(struct mtk_mac_priv *priv) +{ + regmap_update_bits(priv->regs, MTK_MAC_REG_RX_DMA_CTRL, + MTK_MAC_BIT_RX_DMA_CTRL_RESUME, + MTK_MAC_BIT_RX_DMA_CTRL_RESUME); +} + +static void mtk_mac_dma_resume_tx(struct mtk_mac_priv *priv) +{ + regmap_update_bits(priv->regs, MTK_MAC_REG_TX_DMA_CTRL, + MTK_MAC_BIT_TX_DMA_CTRL_RESUME, + MTK_MAC_BIT_TX_DMA_CTRL_RESUME); +} + +static void mtk_mac_set_mac_addr(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + u8 *mac_addr = ndev->dev_addr; + unsigned int high, low; + + high = mac_addr[0] << 8 | mac_addr[1] << 0; + low = mac_addr[2] << 24 | mac_addr[3] << 16 | + mac_addr[4] << 8 | mac_addr[5]; + + regmap_write(priv->regs, MTK_MAC_REG_MY_MAC_H, high); + regmap_write(priv->regs, MTK_MAC_REG_MY_MAC_L, low); +} + +static void mtk_mac_reset_counters(struct mtk_mac_priv *priv) +{ + static const unsigned int counter_regs[] = { + MTK_MAC_REG_C_RXOKPKT, + MTK_MAC_REG_C_RXOKBYTE, + MTK_MAC_REG_C_RXRUNT, + MTK_MAC_REG_C_RXLONG, + MTK_MAC_REG_C_RXDROP, + MTK_MAC_REG_C_RXCRC, + MTK_MAC_REG_C_RXARLDROP, + MTK_MAC_REG_C_RXVLANDROP, + MTK_MAC_REG_C_RXCSERR, + MTK_MAC_REG_C_RXPAUSE, + MTK_MAC_REG_C_TXOKPKT, + MTK_MAC_REG_C_TXOKBYTE, + MTK_MAC_REG_C_TXPAUSECOL, + MTK_MAC_REG_C_TXRTY, + MTK_MAC_REG_C_TXSKIP, + MTK_MAC_REG_C_TX_ARP, + MTK_MAC_REG_C_RX_RERR, + MTK_MAC_REG_C_RX_UNI, + MTK_MAC_REG_C_RX_MULTI, + MTK_MAC_REG_C_RX_BROAD, + MTK_MAC_REG_C_RX_ALIGNERR, + MTK_MAC_REG_C_TX_UNI, + MTK_MAC_REG_C_TX_MULTI, + MTK_MAC_REG_C_TX_BROAD, + MTK_MAC_REG_C_TX_TIMEOUT, + MTK_MAC_REG_C_TX_LATECOL, + MTK_MAC_REG_C_RX_LENGTHERR, + MTK_MAC_REG_C_RX_TWIST, + }; + + unsigned int i, val; + + for (i = 0; i < ARRAY_SIZE(counter_regs); i++) + regmap_read(priv->regs, counter_regs[i], &val); +} + +static void mtk_mac_update_stat(struct mtk_mac_priv *priv, + unsigned int reg, u64 *stat) +{ + unsigned int val; + + regmap_read(priv->regs, reg, &val); + *stat += val; +} + +/* Try to get as many stats as possible from the internal registers instead + * of tracking them ourselves. + */ +static void mtk_mac_update_stats(struct mtk_mac_priv *priv) +{ + struct rtnl_link_stats64 *stats = &priv->stats; + + /* OK packets and bytes. */ + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXOKPKT, &stats->rx_packets); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_TXOKPKT, &stats->tx_packets); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXOKBYTE, &stats->rx_bytes); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_TXOKBYTE, &stats->tx_bytes); + + /* RX & TX multicast. */ + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RX_MULTI, &stats->multicast); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_TX_MULTI, &stats->multicast); + + /* Collisions. */ + mtk_mac_update_stat(priv, MTK_MAC_REG_C_TXPAUSECOL, &stats->collisions); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_TX_LATECOL, &stats->collisions); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXRUNT, &stats->collisions); + + /* RX Errors. */ + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RX_LENGTHERR, + &stats->rx_length_errors); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXLONG, &stats->rx_over_errors); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXCRC, &stats->rx_crc_errors); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RX_ALIGNERR, + &stats->rx_frame_errors); + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RXDROP, &stats->rx_fifo_errors); + /* Sum of the general RX error counter + all of the above. */ + mtk_mac_update_stat(priv, MTK_MAC_REG_C_RX_RERR, &stats->rx_errors); + stats->rx_errors += stats->rx_length_errors; + stats->rx_errors += stats->rx_over_errors; + stats->rx_errors += stats->rx_crc_errors; + stats->rx_errors += stats->rx_frame_errors; + stats->rx_errors += stats->rx_fifo_errors; +} + +static struct sk_buff *mtk_mac_alloc_skb(struct net_device *ndev) +{ + uintptr_t tail, offset; + struct sk_buff *skb; + + skb = dev_alloc_skb(MTK_MAC_MAX_FRAME_SIZE); + if (!skb) + return NULL; + + /* Align to 16 bytes. */ + tail = (uintptr_t)skb_tail_pointer(skb); + if (tail & (MTK_MAC_SKB_ALIGNMENT - 1)) { + offset = tail & (MTK_MAC_SKB_ALIGNMENT - 1); + skb_reserve(skb, MTK_MAC_SKB_ALIGNMENT - offset); + } + + /* Ensure 16-byte alignment of the skb pointer: eth_type_trans() will + * extract the Ethernet header (14 bytes) so we need two more bytes. + */ + skb_reserve(skb, 2); + + return skb; +} + +static int mtk_mac_prepare_rx_skbs(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct mtk_mac_ring *ring = &priv->rx_ring; + struct device *dev = mtk_mac_get_dev(priv); + struct mtk_mac_ring_desc *desc; + struct sk_buff *skb; + dma_addr_t dma_addr; + int i; + + for (i = 0; i < MTK_MAC_NUM_RX_DESCS; i++) { + skb = mtk_mac_alloc_skb(ndev); + if (!skb) + return -ENOMEM; + + dma_addr = mtk_mac_dma_map_rx(priv, skb); + if (dma_mapping_error(dev, dma_addr)) { + dev_kfree_skb(skb); + return -ENOMEM; + } + + desc = &ring->descs[i]; + desc->data_ptr = dma_addr; + desc->status |= skb_tailroom(skb) & MTK_MAC_DESC_MSK_LEN; + desc->status &= ~MTK_MAC_DESC_BIT_COWN; + ring->skbs[i] = skb; + } + + ring->count = MTK_MAC_NUM_RX_DESCS; + + return 0; +} + +/* All processing for TX and RX happens in the napi poll callback. */ +static irqreturn_t mtk_mac_handle_irq(int irq, void *data) +{ + struct mtk_mac_priv *priv; + struct net_device *ndev; + unsigned int status; + + ndev = data; + priv = netdev_priv(ndev); + + if (netif_running(ndev)) { + mtk_mac_intr_mask_all(priv); + status = mtk_mac_intr_read_and_clear(priv); + + /* RX Complete */ + if (status & MTK_MAC_BIT_INT_STS_FNRC) + napi_schedule(&priv->napi); + + /* TX Complete */ + if (status & MTK_MAC_BIT_INT_STS_TNTC) + schedule_work(&priv->tx_work); + + /* One of the counter reached 0x8000000 */ + if (status & MTK_MAC_REG_INT_STS_MIB_CNT_TH) { + mtk_mac_update_stats(priv); + mtk_mac_reset_counters(priv); + } + + mtk_mac_intr_unmask_all(priv); + } + + return IRQ_HANDLED; +} + +static void mtk_mac_free_rx_skbs(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct mtk_mac_ring *ring = &priv->rx_ring; + struct mtk_mac_ring_desc_data desc_data; + struct mtk_mac_ring_desc *desc; + int i; + + for (i = 0; i < MTK_MAC_NUM_RX_DESCS; i++) { + desc = &ring->descs[i]; + + if (!desc->data_ptr) + continue; + + desc_data.dma_addr = desc->data_ptr; + desc_data.skb = ring->skbs[i]; + + mtk_mac_dma_unmap_rx(priv, &desc_data); + dev_kfree_skb(desc_data.skb); + } +} + +static void mtk_mac_free_tx_skbs(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct mtk_mac_ring *ring = &priv->tx_ring; + struct mtk_mac_ring_desc_data desc_data; + struct mtk_mac_ring_desc *desc; + int i; + + for (i = 0; i < MTK_MAC_NUM_TX_DESCS; i++) { + desc = &ring->descs[i]; + + if (!desc->data_ptr) + continue; + + desc_data.dma_addr = desc->data_ptr; + desc_data.len = desc->status & MTK_MAC_DESC_MSK_LEN; + desc_data.skb = ring->skbs[i]; + + mtk_mac_dma_unmap_tx(priv, &desc_data); + dev_kfree_skb(desc_data.skb); + } +} + +static void mtk_mac_phy_config(struct mtk_mac_priv *priv) +{ + unsigned int val; + + if (priv->speed == SPEED_1000) + val = MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_1000M; + else if (priv->speed == SPEED_100) + val = MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_100M; + else + val = MTK_MAC_VAL_PHY_CTRL1_FORCE_SPD_10M; + val <<= MTK_MAC_OFF_PHY_CTRL1_FORCE_SPD; + + val |= MTK_MAC_BIT_PHY_CTRL1_AN_EN; + val |= MTK_MAC_BIT_PHY_CTRL1_FORCE_FC_RX; + val |= MTK_MAC_BIT_PHY_CTRL1_FORCE_FC_TX; + /* Only full-duplex supported for now. */ + val |= MTK_MAC_BIT_PHY_CTRL1_FORCE_DPX; + + regmap_write(priv->regs, MTK_MAC_REG_PHY_CTRL1, val); +} + +static void mtk_mac_adjust_link(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct phy_device *phydev = priv->phydev; + bool new_state = false; + + if (phydev->link) { + if (!priv->link) { + priv->link = phydev->link; + new_state = true; + } + + if (priv->speed != phydev->speed) { + priv->speed = phydev->speed; + new_state = true; + } + } else { + if (priv->link) { + priv->link = phydev->link; + new_state = true; + } + } + + if (new_state) { + if (phydev->link) + mtk_mac_phy_config(priv); + phy_print_status(ndev->phydev); + } +} + +static void mtk_mac_init_config(struct mtk_mac_priv *priv) +{ + unsigned int val; + + val = (MTK_MAC_BIT_MII_PAD_OUT_ENABLE | + MTK_MAC_BIT_EXT_MDC_MODE | + MTK_MAC_BIT_SWC_MII_MODE); + + regmap_write(priv->regs, MTK_MAC_REG_SYS_CONF, val); + regmap_update_bits(priv->regs, MTK_MAC_REG_MAC_CLK_CONF, + MTK_MAC_MSK_MAC_CLK_CONF, + MTK_MAC_BIT_CLK_DIV_10); +} + +static void mtk_mac_set_mode_rmii(struct mtk_mac_priv *priv) +{ + regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, + MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, + MTK_PERICFG_BIT_NIC_CFG_CON_RMII); +} + +static int mtk_mac_enable(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + unsigned int val; + int ret; + + mtk_mac_nic_disable_pd(priv); + mtk_mac_intr_mask_all(priv); + mtk_mac_dma_stop(priv); + netif_carrier_off(ndev); + + mtk_mac_set_mac_addr(ndev); + + /* Configure the MAC */ + val = MTK_MAC_VAL_MAC_CFG_IPG_96BIT; + val <<= MTK_MAC_OFF_MAC_CFG_IPG; + val |= MTK_MAC_BIT_MAC_CFG_MAXLEN_1522; + val |= MTK_MAC_BIT_MAC_CFG_AUTO_PAD; + val |= MTK_MAC_BIT_MAC_CFG_CRC_STRIP; + regmap_write(priv->regs, MTK_MAC_REG_MAC_CFG, val); + + /* Configure flow control */ + val = MTK_MAC_VAL_FC_CFG_SEND_PAUSE_TH_2K; + val <<= MTK_MAC_OFF_FC_CFG_SEND_PAUSE_TH; + val |= MTK_MAC_BIT_FC_CFG_BP_EN; + val |= MTK_MAC_BIT_FC_CFG_UC_PAUSE_DIR; + regmap_write(priv->regs, MTK_MAC_REG_FC_CFG, val); + + /* Set SEND_PAUSE_RLS to 1K */ + val = MTK_MAC_VAL_EXT_CFG_SND_PAUSE_RLS_1K; + val <<= MTK_MAC_OFF_EXT_CFG_SND_PAUSE_RLS; + regmap_write(priv->regs, MTK_MAC_REG_EXT_CFG, val); + + /* Reset all counters */ + mtk_mac_reset_counters(priv); + + /* Enable Hash Table BIST and reset it */ + regmap_update_bits(priv->regs, MTK_MAC_REG_HASH_CTRL, + MTK_MAC_BIT_HASH_CTRL_BIST_EN, + MTK_MAC_BIT_HASH_CTRL_BIST_EN); + regmap_update_bits(priv->regs, MTK_MAC_REG_TEST1, + MTK_MAC_BIT_TEST1_RST_HASH_MBIST, + MTK_MAC_BIT_TEST1_RST_HASH_MBIST); + + /* Setup the hashing algorithm */ + regmap_update_bits(priv->regs, MTK_MAC_REG_ARL_CFG, + MTK_MAC_BIT_ARL_CFG_HASH_ALG | + MTK_MAC_BIT_ARL_CFG_MISC_MODE, 0); + + /* Don't strip VLAN tags */ + regmap_update_bits(priv->regs, MTK_MAC_REG_MAC_CFG, + MTK_MAC_BIT_MAC_CFG_VLAN_STRIP, 0); + + /* Setup DMA */ + mtk_mac_dma_init(priv); + + ret = mtk_mac_prepare_rx_skbs(ndev); + if (ret) + goto err_out; + + /* Request the interrupt */ + ret = request_irq(ndev->irq, mtk_mac_handle_irq, + IRQF_TRIGGER_FALLING, ndev->name, ndev); + if (ret) + goto err_free_skbs; + + napi_enable(&priv->napi); + + mtk_mac_intr_read_and_clear(priv); + mtk_mac_intr_unmask_all(priv); + + /* Connect to and start PHY */ + priv->phydev = of_phy_connect(ndev, priv->phy_node, + mtk_mac_adjust_link, 0, priv->phy_intf); + if (!priv->phydev) { + netdev_err(ndev, "failed to connect to PHY\n"); + goto err_free_irq; + } + + mtk_mac_dma_start(priv); + phy_start(priv->phydev); + netif_start_queue(ndev); + + return 0; + +err_free_irq: + free_irq(ndev->irq, ndev); +err_free_skbs: + mtk_mac_free_rx_skbs(ndev); +err_out: + return ret; +} + +static void mtk_mac_disable(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + + netif_stop_queue(ndev); + napi_disable(&priv->napi); + mtk_mac_intr_mask_all(priv); + mtk_mac_dma_disable(priv); + mtk_mac_intr_read_and_clear(priv); + phy_stop(priv->phydev); + phy_disconnect(priv->phydev); + free_irq(ndev->irq, ndev); + mtk_mac_free_rx_skbs(ndev); + mtk_mac_free_tx_skbs(ndev); +} + +static int mtk_mac_netdev_open(struct net_device *ndev) +{ + return mtk_mac_enable(ndev); +} + +static int mtk_mac_netdev_stop(struct net_device *ndev) +{ + mtk_mac_disable(ndev); + + return 0; +} + +static int mtk_mac_netdev_ioctl(struct net_device *ndev, + struct ifreq *req, int cmd) +{ + if (!netif_running(ndev)) + return -EINVAL; + + return phy_mii_ioctl(ndev->phydev, req, cmd); +} + +static int mtk_mac_netdev_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct mtk_mac_ring *ring = &priv->tx_ring; + struct device *dev = mtk_mac_get_dev(priv); + struct mtk_mac_ring_desc_data desc_data; + + if (skb->len > MTK_MAC_MAX_FRAME_SIZE) + goto err_drop_packet; + + desc_data.dma_addr = mtk_mac_dma_map_tx(priv, skb); + if (dma_mapping_error(dev, desc_data.dma_addr)) + goto err_drop_packet; + + desc_data.skb = skb; + desc_data.len = skb->len; + + mtk_mac_lock(priv); + mtk_mac_ring_push_head_tx(ring, &desc_data); + + if (mtk_mac_ring_full(ring)) + netif_stop_queue(ndev); + mtk_mac_unlock(priv); + + mtk_mac_dma_resume_tx(priv); + + return NETDEV_TX_OK; + +err_drop_packet: + dev_kfree_skb(skb); + ndev->stats.tx_dropped++; + return NETDEV_TX_BUSY; +} + +static int mtk_mac_tx_complete(struct mtk_mac_priv *priv) +{ + struct mtk_mac_ring *ring = &priv->tx_ring; + struct mtk_mac_ring_desc_data desc_data; + int ret; + + ret = mtk_mac_ring_pop_tail(ring, &desc_data); + if (ret) + return ret; + + mtk_mac_dma_unmap_tx(priv, &desc_data); + dev_kfree_skb_irq(desc_data.skb); + + return 0; +} + +static void mtk_mac_tx_work(struct work_struct *work) +{ + struct mtk_mac_priv *priv; + struct mtk_mac_ring *ring; + struct net_device *ndev; + bool wake = false; + int ret; + + priv = container_of(work, struct mtk_mac_priv, tx_work); + ndev = mtk_mac_get_netdev(priv); + ring = &priv->tx_ring; + + for (;;) { + mtk_mac_lock(priv); + + if (!mtk_mac_ring_descs_available(ring)) { + mtk_mac_unlock(priv); + break; + } + + ret = mtk_mac_tx_complete(priv); + mtk_mac_unlock(priv); + if (ret) + break; + + wake = true; + } + + if (wake) + netif_wake_queue(ndev); +} + +static void mtk_mac_netdev_get_stats64(struct net_device *ndev, + struct rtnl_link_stats64 *stats) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + + mtk_mac_update_stats(priv); + + memcpy(stats, &priv->stats, sizeof(*stats)); +} + +static void mtk_mac_set_hashbit(struct mtk_mac_priv *priv, + unsigned int hash_addr) +{ + unsigned int val; + + val = hash_addr & MTK_MAC_MSK_HASH_CTRL_HASH_BIT_ADDR; + val |= MTK_MAC_BIT_HASH_CTRL_ACC_CMD; + val |= MTK_MAC_BIT_HASH_CTRL_CMD_START; + val |= MTK_MAC_BIT_HASH_CTRL_BIST_EN; + val |= MTK_MAC_BIT_HASH_CTRL_HASH_BIT_DATA; + + regmap_write(priv->regs, MTK_MAC_REG_HASH_CTRL, val); +} + +static void mtk_mac_set_rx_mode(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct netdev_hw_addr *hw_addr; + unsigned int hash_addr, i; + + if (ndev->flags & IFF_PROMISC) { + regmap_update_bits(priv->regs, MTK_MAC_REG_ARL_CFG, + MTK_MAC_BIT_ARL_CFG_MISC_MODE, + MTK_MAC_BIT_ARL_CFG_MISC_MODE); + } else if (netdev_mc_count(ndev) > MTK_MAC_HASHTABLE_MC_LIMIT || + ndev->flags & IFF_ALLMULTI) { + for (i = 0; i < MTK_MAC_HASHTABLE_SIZE_MAX; i++) + mtk_mac_set_hashbit(priv, i); + } else { + netdev_for_each_mc_addr(hw_addr, ndev) { + hash_addr = (hw_addr->addr[0] & 0x01) << 8; + hash_addr += hw_addr->addr[5]; + mtk_mac_set_hashbit(priv, hash_addr); + } + } +} + +static const struct net_device_ops mtk_mac_netdev_ops = { + .ndo_open = mtk_mac_netdev_open, + .ndo_stop = mtk_mac_netdev_stop, + .ndo_start_xmit = mtk_mac_netdev_start_xmit, + .ndo_get_stats64 = mtk_mac_netdev_get_stats64, + .ndo_set_rx_mode = mtk_mac_set_rx_mode, + .ndo_do_ioctl = mtk_mac_netdev_ioctl, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +}; + +static void mtk_mac_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strlcpy(info->driver, MTK_MAC_DRVNAME, sizeof(info->driver)); + strlcpy(info->version, MTK_MAC_VERSION, sizeof(info->version)); +} + +/* TODO Add ethtool stats. */ +static const struct ethtool_ops mtk_mac_ethtool_ops = { + .get_drvinfo = mtk_mac_get_drvinfo, + .get_link = ethtool_op_get_link, + .get_link_ksettings = phy_ethtool_get_link_ksettings, + .set_link_ksettings = phy_ethtool_set_link_ksettings, +}; + +static int mtk_mac_receive_packet(struct mtk_mac_priv *priv) +{ + struct net_device *ndev = mtk_mac_get_netdev(priv); + struct mtk_mac_ring *ring = &priv->rx_ring; + struct device *dev = mtk_mac_get_dev(priv); + struct mtk_mac_ring_desc_data desc_data; + struct sk_buff *new_skb; + int ret; + + mtk_mac_lock(priv); + ret = mtk_mac_ring_pop_tail(ring, &desc_data); + mtk_mac_unlock(priv); + if (ret) + return -1; + + mtk_mac_dma_unmap_rx(priv, &desc_data); + + if ((desc_data.flags & MTK_MAC_DESC_BIT_RX_CRCE) || + (desc_data.flags & MTK_MAC_DESC_BIT_RX_OSIZE)) { + /* Error packet -> drop and reuse skb. */ + new_skb = desc_data.skb; + goto map_skb; + } + + new_skb = mtk_mac_alloc_skb(ndev); + if (!new_skb) { + netdev_err(ndev, "out of memory for skb\n"); + ndev->stats.rx_dropped++; + new_skb = desc_data.skb; + goto map_skb; + } + + skb_put(desc_data.skb, desc_data.len); + desc_data.skb->ip_summed = CHECKSUM_NONE; + desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev); + desc_data.skb->dev = ndev; + netif_receive_skb(desc_data.skb); + +map_skb: + desc_data.dma_addr = mtk_mac_dma_map_rx(priv, new_skb); + if (dma_mapping_error(dev, desc_data.dma_addr)) { + dev_kfree_skb(new_skb); + netdev_err(ndev, "DMA mapping error of RX descriptor\n"); + return -ENOMEM; + } + + desc_data.len = skb_tailroom(new_skb); + desc_data.skb = new_skb; + + mtk_mac_lock(priv); + mtk_mac_ring_push_head_rx(ring, &desc_data); + mtk_mac_unlock(priv); + + return 0; +} + +static int mtk_mac_process_rx(struct mtk_mac_priv *priv, int budget) +{ + int received, ret; + + for (received = 0, ret = 0; received < budget && ret == 0; received++) + ret = mtk_mac_receive_packet(priv); + + mtk_mac_dma_resume_rx(priv); + + return received; +} + +static int mtk_mac_poll(struct napi_struct *napi, int budget) +{ + struct mtk_mac_priv *priv; + int received = 0; + + priv = container_of(napi, struct mtk_mac_priv, napi); + + received = mtk_mac_process_rx(priv, budget); + if (received < budget) + napi_complete_done(napi, received); + + return received; +} + +static void mtk_mac_mdio_rwok_clear(struct mtk_mac_priv *priv) +{ + regmap_write(priv->regs, MTK_MAC_REG_PHY_CTRL0, + MTK_MAC_BIT_PHY_CTRL0_RWOK); +} + +static int mtk_mac_mdio_rwok_wait(struct mtk_mac_priv *priv) +{ + unsigned long start = jiffies; + unsigned int val; + + for (;;) { + regmap_read(priv->regs, MTK_MAC_REG_PHY_CTRL0, &val); + if (val & MTK_MAC_BIT_PHY_CTRL0_RWOK) + break; + + udelay(10); + if (time_after(jiffies, start + MTK_MAC_WAIT_TIMEOUT)) + return -ETIMEDOUT; + } + + return 0; +} + +static int mtk_mac_mdio_read(struct mii_bus *mii, int phy_id, int regnum) +{ + struct mtk_mac_priv *priv = mii->priv; + unsigned int val, data; + int ret; + + mtk_mac_mdio_rwok_clear(priv); + + val = (regnum << MTK_MAC_OFF_PHY_CTRL0_PREG); + val &= MTK_MAC_MSK_PHY_CTRL0_PREG; + val |= MTK_MAC_BIT_PHY_CTRL0_RDCMD; + + regmap_write(priv->regs, MTK_MAC_REG_PHY_CTRL0, val); + + ret = mtk_mac_mdio_rwok_wait(priv); + if (ret) + return ret; + + regmap_read(priv->regs, MTK_MAC_REG_PHY_CTRL0, &data); + + data &= MTK_MAC_MSK_PHY_CTRL0_RWDATA; + data >>= MTK_MAC_OFF_PHY_CTRL0_RWDATA; + + return data; +} + +static int mtk_mac_mdio_write(struct mii_bus *mii, int phy_id, + int regnum, u16 data) +{ + struct mtk_mac_priv *priv = mii->priv; + unsigned int val; + + mtk_mac_mdio_rwok_clear(priv); + + val = data; + val <<= MTK_MAC_OFF_PHY_CTRL0_RWDATA; + val &= MTK_MAC_MSK_PHY_CTRL0_RWDATA; + regnum <<= MTK_MAC_OFF_PHY_CTRL0_PREG; + regnum &= MTK_MAC_MSK_PHY_CTRL0_PREG; + val |= regnum; + val |= MTK_MAC_BIT_PHY_CTRL0_WTCMD; + + regmap_write(priv->regs, MTK_MAC_REG_PHY_CTRL0, val); + + return mtk_mac_mdio_rwok_wait(priv); +} + +static int mtk_mac_mdio_init(struct net_device *ndev) +{ + struct mtk_mac_priv *priv = netdev_priv(ndev); + struct device *dev = mtk_mac_get_dev(priv); + struct device_node *of_node, *mdio_node; + int ret; + + of_node = dev->of_node; + + mdio_node = of_get_child_by_name(of_node, "mdio"); + if (!mdio_node) + return -ENODEV; + + if (!of_device_is_available(mdio_node)) { + ret = -ENODEV; + goto out_put_node; + } + + priv->mii = devm_mdiobus_alloc(dev); + if (!priv->mii) { + ret = -ENOMEM; + goto out_put_node; + } + + snprintf(priv->mii->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + priv->mii->name = "mdio"; + priv->mii->parent = dev; + priv->mii->read = mtk_mac_mdio_read; + priv->mii->write = mtk_mac_mdio_write; + priv->mii->priv = priv; + + ret = of_mdiobus_register(priv->mii, mdio_node); + +out_put_node: + of_node_put(mdio_node); + return ret; +} + +static int mtk_mac_suspend(struct device *dev) +{ + struct mtk_mac_priv *priv; + struct net_device *ndev; + + ndev = dev_get_drvdata(dev); + priv = netdev_priv(ndev); + + mtk_mac_disable(ndev); + clk_bulk_disable_unprepare(MTK_MAC_NCLKS, priv->clks); + + return 0; +} + +static int mtk_mac_resume(struct device *dev) +{ + struct mtk_mac_priv *priv; + struct net_device *ndev; + int ret; + + ndev = dev_get_drvdata(dev); + priv = netdev_priv(ndev); + + ret = clk_bulk_prepare_enable(MTK_MAC_NCLKS, priv->clks); + if (ret) + return ret; + + ret = mtk_mac_enable(ndev); + if (ret) + clk_bulk_disable_unprepare(MTK_MAC_NCLKS, priv->clks); + + return ret; +} + +static void mtk_mac_clk_disable_unprepare(void *data) +{ + struct mtk_mac_priv *priv = data; + + clk_bulk_disable_unprepare(MTK_MAC_NCLKS, priv->clks); +} + +static int mtk_mac_probe(struct platform_device *pdev) +{ + struct device_node *of_node; + struct mtk_mac_priv *priv; + struct net_device *ndev; + struct device *dev; + void __iomem *base; + int ret, i; + + dev = &pdev->dev; + of_node = dev->of_node; + + ndev = devm_alloc_etherdev(dev, sizeof(*priv)); + if (!ndev) + return -ENOMEM; + + priv = netdev_priv(ndev); + SET_NETDEV_DEV(ndev, dev); + platform_set_drvdata(pdev, ndev); + + spin_lock_init(&priv->lock); + INIT_WORK(&priv->tx_work, mtk_mac_tx_work); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* We won't be checking the return values of regmap read & write + * functions. They can only fail for mmio if there's a clock attached + * to regmap which is not the case here. + */ + priv->regs = devm_regmap_init_mmio(dev, base, + &mtk_mac_regmap_config); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->pericfg = syscon_regmap_lookup_by_phandle(of_node, + "mediatek,pericfg"); + if (IS_ERR(priv->pericfg)) { + dev_err(dev, "Failed to lookup the PERICFG syscon\n"); + return PTR_ERR(priv->pericfg); + } + + ndev->irq = platform_get_irq(pdev, 0); + if (ndev->irq < 0) + return ndev->irq; + + for (i = 0; i < MTK_MAC_NCLKS; i++) + priv->clks[i].id = mtk_mac_clk_names[i]; + ret = devm_clk_bulk_get(dev, MTK_MAC_NCLKS, priv->clks); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(MTK_MAC_NCLKS, priv->clks); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, + mtk_mac_clk_disable_unprepare, priv); + if (ret) + return ret; + + ret = of_get_phy_mode(of_node, &priv->phy_intf); + if (ret) { + return ret; + } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII) { + dev_err(dev, "unsupported phy mode: %s\n", + phy_modes(priv->phy_intf)); + return -EINVAL; + } + + priv->phy_node = of_parse_phandle(of_node, "phy-handle", 0); + if (!priv->phy_node) { + dev_err(dev, "failed to retrieve the phy handle from device tree\n"); + return -ENODEV; + } + + mtk_mac_set_mode_rmii(priv); + + dev->coherent_dma_mask = DMA_BIT_MASK(32); + dev->dma_mask = &dev->coherent_dma_mask; + priv->ring_base = dmam_alloc_coherent(dev, MTK_MAC_DMA_SIZE, + &priv->dma_addr, + GFP_KERNEL | GFP_DMA); + if (!priv->ring_base) + return -ENOMEM; + + mtk_mac_nic_disable_pd(priv); + mtk_mac_init_config(priv); + + ret = mtk_mac_mdio_init(ndev); + if (ret) + return ret; + + ret = eth_platform_get_mac_address(dev, ndev->dev_addr); + if (ret || !is_valid_ether_addr(ndev->dev_addr)) { + random_ether_addr(ndev->dev_addr); + ndev->addr_assign_type = NET_ADDR_RANDOM; + } + + ndev->netdev_ops = &mtk_mac_netdev_ops; + ndev->ethtool_ops = &mtk_mac_ethtool_ops; + + netif_napi_add(ndev, &priv->napi, mtk_mac_poll, MTK_MAC_NAPI_WEIGHT); + + return devm_register_netdev(ndev); +} + +static const struct of_device_id mtk_mac_of_match[] = { + { .compatible = "mediatek,mt8516-eth", }, + { .compatible = "mediatek,mt8518-eth", }, + { .compatible = "mediatek,mt8175-eth", }, + { } +}; +MODULE_DEVICE_TABLE(of, mtk_mac_of_match); + +static SIMPLE_DEV_PM_OPS(mtk_mac_pm_ops, + mtk_mac_suspend, mtk_mac_resume); + +static struct platform_driver mtk_mac_driver = { + .driver = { + .name = MTK_MAC_DRVNAME, + .pm = &mtk_mac_pm_ops, + .of_match_table = of_match_ptr(mtk_mac_of_match), + }, + .probe = mtk_mac_probe, +}; +module_platform_driver(mtk_mac_driver); + +MODULE_AUTHOR("Bartosz Golaszewski "); +MODULE_DESCRIPTION("Mediatek Ethernet MAC Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue May 5 14:02:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283652 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; 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[2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:13 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 07/11] ARM64: dts: mediatek: add pericfg syscon to mt8516.dtsi Date: Tue, 5 May 2020 16:02:27 +0200 Message-Id: <20200505140231.16600-8-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski This adds support for the PERICFG register range as a syscon. This will soon be used by the MediaTek Ethernet MAC driver for NIC configuration. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 2f8adf042195..8cedaf74ae86 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -191,6 +191,11 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; + pericfg: pericfg@10003050 { + compatible = "mediatek,mt8516-pericfg", "syscon"; + reg = <0 0x10003050 0 0x1000>; + }; + apmixedsys: apmixedsys@10018000 { compatible = "mediatek,mt8516-apmixedsys", "syscon"; reg = <0 0x10018000 0 0x710>; From patchwork Tue May 5 14:02:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283655 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=cVzH1dPG; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhKD0D30z9sSW for ; Wed, 6 May 2020 00:03:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729441AbgEEODn (ORCPT ); Tue, 5 May 2020 10:03:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729369AbgEEODR (ORCPT ); Tue, 5 May 2020 10:03:17 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A8DBC061A41 for ; Tue, 5 May 2020 07:03:16 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id k1so2911962wrx.4 for ; Tue, 05 May 2020 07:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cLB08H4ZIlTMzvj5hInDPm3tTNq7mk/XtYoMNSk6v2w=; b=cVzH1dPGpMqAXPxKb2+d0LSY7/HTueVOi2Sdclc1d5WFXroNiTnCGax06ZRUzUzxBC BUh3y57hEA0QKHn0p8LMuwuIGxUcGlnDrT6dMvKvVo8CknIBmfP+WtMUK/RXkzf+hQAd CG7wMuCkKOANszSzqBn9jqXq1Ze5auYS7lGvNg5z+nbF8yG827NVgpPaFCp8YOAnKKI0 h6VO7RNUL3pV+so74edRAnGDHHHcdwfPC6u++KxWTUZe+FCdgfTpNkF93LmwoywsYj/K gYxW4eQvxZ3fbG8FUAlWnbR/kU00rYU8f+Gn2FKmBkWJv/OV0h6bhhfiL4fJ8mrEn4a6 vcng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cLB08H4ZIlTMzvj5hInDPm3tTNq7mk/XtYoMNSk6v2w=; b=WEuLxz64xomAnbwc6dXERoS7dcXLIK4FPRpB5iGhKYVoYVp1Nk0/ZPyJ186n9c94EW NVilrCQBo7F/pXOq0ovMXv0w+b9qbWbsmtX6nkkREcYcWFp/tPwkczGspF9I1Kvixwcs sUVwh59ewrCDIONo9P6k3ncruQ+X2AaqyUPpZhJPK5sxYCZhIu+NK2UuE9by3+lwDZxH oasf3cHvXUGqwDU1PLppkZDUGjkxhPvzwzEdevj3ubEOZodYeJnVAiPiaMEs1vHV13sL gqjLd3m0bLY5Ld9V6sBZ4sd1emCLt8+x/Az3jHc4ihAkRaDJ0urNre0gb45j0GJ2e72Y jy/g== X-Gm-Message-State: AGi0Pub+mvweqAabDgn9mNrhgNZ7Wi3yiIa4tp0xQOKMN0hbjhQLJyxi ird/mbzgk/9pfcURQN9AaDQErw== X-Google-Smtp-Source: APiQypLYiuxJLzQGcByYdRNRqjThYrVDv5Mb46r0e9HU0s7k3vsW2WSb3TSlR7LGVUwNfPWr1XlEkg== X-Received: by 2002:a5d:4043:: with SMTP id w3mr3951385wrp.266.1588687395284; Tue, 05 May 2020 07:03:15 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:14 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 08/11] ARM64: dts: mediatek: add the ethernet node to mt8516.dtsi Date: Tue, 5 May 2020 16:02:28 +0200 Message-Id: <20200505140231.16600-9-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski Add the Ethernet MAC node to mt8516.dtsi. This defines parameters common to all the boards based on this SoC. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 8cedaf74ae86..89af661e7f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -406,6 +406,18 @@ mmc2: mmc@11170000 { status = "disabled"; }; + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0 0x11180000 0 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + rng: rng@1020c000 { compatible = "mediatek,mt8516-rng", "mediatek,mt7623-rng"; From patchwork Tue May 5 14:02:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283653 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=LQwCci65; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhK30L1Rz9sT4 for ; Wed, 6 May 2020 00:03:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729392AbgEEODV (ORCPT ); Tue, 5 May 2020 10:03:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729379AbgEEODS (ORCPT ); Tue, 5 May 2020 10:03:18 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46A4FC0610D6 for ; Tue, 5 May 2020 07:03:18 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id j5so2110535wrq.2 for ; Tue, 05 May 2020 07:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1qePp19LiRiOBXtccpgQ+eI6GUOhz0auoBWQ11adkXY=; b=LQwCci65NzZKH7S/k3KLNL9uDqCmT0NhL3+vr0FbsT08zlA7KCjEKKJA3sZtnf2+C9 MgO3OOfj1iU8OOWJHAIFg37vsHsbgcG/ty8jsHreNlysA9n/Au6JLGB7Xxv750eTBgT+ Sl+iLzCZd3APUglRO82tTPfZvQVLMJ3uavNHAqLe/avFh/YZADgXqEMvzVqRopDktCy2 JBbLkT1YWVum/i0H4xsIcA/O3SnOtyCQ72Fc/9gVx/ow94+06PK5wjuMsmA86t5vb78a f1BNH1aOQZ6Kmm6CjzEh853K5kHs/8DpEoorye+0Q8Vxs8MX0SzFaarHH6cmphLUotuV jc4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1qePp19LiRiOBXtccpgQ+eI6GUOhz0auoBWQ11adkXY=; b=IAMrHl82xwHT04549uulUQFrwzRh52EgiY0vuv6a3nwvNWZKoc2vOOPYE1y3J+mQCf qlHgHj77chxGjKBq6YeuHrRk+09oTycbhHhpa4IZ2vp6Lm5gO1d91sLwclO+DcgKEfoA zZqlX/+NYwdNXL+8QnhL8qj7RieYF826QMguDoeceLV/P2uJ4bTM3c7AmW0tZZTd//TL E9vO8AkFr8oh6XqdG3cQ8y3MXVIQfzL/X6ntqaYBiMxoDzeYLQ1XtpTXkOxV6+VnCNEI 8cicNSOKWS+VESWB5CgrA1bE2YuNx5vXApdpXlVwWqNiC0LLQhJw4l+TW+HVH7QOL8Gb DSIw== X-Gm-Message-State: AGi0PuYRhbK2b2dZh3TPXPNGxXDLIGWZu7pvUQUr7Lc1P4Er4+X8KF/e Ji5RYpFdwRhm2ZdquklW93qt6Q== X-Google-Smtp-Source: APiQypKqTKjLTaeehBmyF8ZBLt7Ztsq7bEei0OsGAye1X2D3s2hQaZgytBvFg7WpUlAYtX37tEZNHw== X-Received: by 2002:adf:ab5c:: with SMTP id r28mr3827494wrc.384.1588687396984; Tue, 05 May 2020 07:03:16 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:16 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 09/11] ARM64: dts: mediatek: add an alias for ethernet0 for pumpkin boards Date: Tue, 5 May 2020 16:02:29 +0200 Message-Id: <20200505140231.16600-10-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski Add the ethernet0 alias for ethernet so that u-boot can find this node and fill in the MAC address. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index a31093d7142b..97d9b000c37e 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -9,6 +9,7 @@ / { aliases { serial0 = &uart0; + ethernet0 = ðernet; }; chosen { From patchwork Tue May 5 14:02:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283654 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=lSlyl4mO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhK4600Jz9sTC for ; Wed, 6 May 2020 00:03:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729428AbgEEODg (ORCPT ); Tue, 5 May 2020 10:03:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729389AbgEEODU (ORCPT ); Tue, 5 May 2020 10:03:20 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02EF2C061A41 for ; Tue, 5 May 2020 07:03:20 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id z6so2492480wml.2 for ; Tue, 05 May 2020 07:03:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KiLRpfO6b7G+PZFXWrA65hqZV6E46x1U4Qg5U0775pc=; b=lSlyl4mOElbeeStRAJ4CWke7R4swrfRTDDvLBAB45QOvM4+7cfviB8IS+q8YjTZ9ER J/ERsLiOQHNV1mTXN3jPp9K18esFG4ne5yM9GcYpMm01CSVnE/W734lRVikO4BAQNJfp NIJ0jLuZD/AMpS3Co94mCUYYzA7Mbr3GSRHF0qswguqdE/7M72H1HNornTVQfgBDvMBf J2lJdqjGdfJQJZaUMRQJG+LjJd44f4bKZ6cbr2NR816aGdFW5ioRRvqPprprQr5Q4qDe 0CAUeW3L2CkjgSaKgHc1XyVKlBJjesE4lOuflOL1uJe3/07Mw43PRohiyBdxf3FGLcgj LT/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KiLRpfO6b7G+PZFXWrA65hqZV6E46x1U4Qg5U0775pc=; b=Y/7JYutjsYIB0frKG+9ONLJEJ/jUwqiguP/09xlRtrlCdY2qJK/KZGe4YwmWs1Nfox LvMtkVF6Hf8J+Hxj/xD8qg8Guo6z3ulaWUbx9hnzfO9iBcoMPGway90cEp0pp5Vl1lr/ THsXddOHMXSxRgv3uj9skSPiAblZTOc3XTLNqhqs041w4ui+ScBbfyZl19Gok/Q93LIj QN96Idr5gmWa98GhzcAZoJbeg16/HoHb/iWRu+fDSUrw6qqsYJ3isGdGLSIVNj7la7m3 acD96tFdCknayJaqWkkVLsudoBy0kBFOK/9X2yV+0iF2qZgDM0VABLPxNNMIL+jibMLz 31mA== X-Gm-Message-State: AGi0PuaSOxuvNpPOEaV5q8ud+l6ncPUgjpZBiXU0FqwHTCwCMZBXO8f3 fJXInMENObmpuOaV5Ea0HiOpbQ== X-Google-Smtp-Source: APiQypKwmZMdeEmUAzcUU4K0jiEpe5kHCS1F6NfZ1/9dSidf/8PeL2h2zvcjETlSxePjjPJCHSUbNA== X-Received: by 2002:a1c:9c0a:: with SMTP id f10mr3689658wme.139.1588687398732; Tue, 05 May 2020 07:03:18 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:18 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 10/11] ARM64: dts: mediatek: add ethernet pins for pumpkin boards Date: Tue, 5 May 2020 16:02:30 +0200 Message-Id: <20200505140231.16600-11-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski Setup the pin control for the Ethernet MAC. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 97d9b000c37e..4b1d5f69aba6 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -219,4 +219,19 @@ gpio_mux_int_n_pin { bias-pull-up; }; }; + + ethernet_pins_default: ethernet { + pins_ethernet { + pinmux = , + , + , + , + , + , + , + , + , + ; + }; + }; }; From patchwork Tue May 5 14:02:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 1283651 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bgdev-pl.20150623.gappssmtp.com header.i=@bgdev-pl.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=b1g+w8Bb; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49GhJy2MB5z9sT4 for ; Wed, 6 May 2020 00:03:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729422AbgEEOD3 (ORCPT ); Tue, 5 May 2020 10:03:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729396AbgEEODW (ORCPT ); Tue, 5 May 2020 10:03:22 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70633C0610D6 for ; Tue, 5 May 2020 07:03:21 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id l18so2873166wrn.6 for ; Tue, 05 May 2020 07:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nZF4M1Ryr6CWnpRgUMWuRsLTKn/UHmWXZ3+MZTEjA0A=; b=b1g+w8BbUfw1KBw5K5flqcpokPuwWxqpurh2OtOPaunuRCeznQpZQlwP/WmuzoQgod CFSP4OiPt1lnEwVmBbNmoJbW8Lp9A94lN6aZgEgid2Id63oLBylgAseWNbdxn6jtSsYR E/Fc3NnZWPVr75Zc4iI18RNGT0JBcgshtWeyJ7ygIa2DncTH6eFWRlYLO+juQ1IJuzRg qq/R2tbLKwU0DYSzilgyEMuOgD9YzdMBKR7ZxLdG9s7DBdX+mipCe+CicuEcioBHW8Pl SLJzfUoWzzS0YBpfZIcrkuLP4G1MO1KO2GPMW7SFg0Od6O4NZwujxJubuNCjSksjEPFg B38Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nZF4M1Ryr6CWnpRgUMWuRsLTKn/UHmWXZ3+MZTEjA0A=; b=uBDtOyTWCCgG3uY/jPPBR6rMBtdmNvQqXkSaxfi62w4nPCLg7twZlTQjJbo4I/ecn5 9zMWV7ySun31fp3Ts3S5deDCnYhDwojSie3eTYgT89HHL1E7q2xVraCt0iRyzM/TEUu/ MwAHz3AsQ38sGTLo3oAxdPOVEyHo/EhXiU1/4v9OFxfuGV5HKqW07tYyaQNpET89CTc/ KTZCwrRTAjLW2rFUbHnAnW7yibVxouBQJM9haq5CarTU82/MTXVO/BIsAHFOhDD/Iqah NJvU7VD+ssTeGz3cl+LBR0EL7ATt1sh28wJBLtOYDnFrxCW1C7ZUCpHx5wdjrV9QKZ7F b9lA== X-Gm-Message-State: AGi0PuZXYSwcsDQEVU6YfeZCvBUy6Pdu6xHFVVu0mI0gufVRzr/mezu6 kwaqowqXkagWB2Dqc1qBOaKANg== X-Google-Smtp-Source: APiQypKSn8NhwYdJ0V9/oJPNixCPyhQzeTO3N+zmykXTaq3hm8BpCPa3gRNfEdcvq21s3N2xigB8/Q== X-Received: by 2002:adf:e905:: with SMTP id f5mr3949344wrm.409.1588687400189; Tue, 05 May 2020 07:03:20 -0700 (PDT) Received: from localhost.localdomain (lfbn-nic-1-65-232.w2-15.abo.wanadoo.fr. [2.15.156.232]) by smtp.gmail.com with ESMTPSA id c190sm4075755wme.4.2020.05.05.07.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 07:03:19 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , "David S . Miller" , Matthias Brugger , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Jakub Kicinski , Arnd Bergmann , Fabien Parent Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 11/11] ARM64: dts: mediatek: enable ethernet on pumpkin boards Date: Tue, 5 May 2020 16:02:31 +0200 Message-Id: <20200505140231.16600-12-brgl@bgdev.pl> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200505140231.16600-1-brgl@bgdev.pl> References: <20200505140231.16600-1-brgl@bgdev.pl> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bartosz Golaszewski Add remaining properties to the ethernet node and enable it. Signed-off-by: Bartosz Golaszewski --- .../boot/dts/mediatek/pumpkin-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 4b1d5f69aba6..dfceffe6950a 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -167,6 +167,24 @@ &uart0 { status = "okay"; }; +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins_default>; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &usb0 { status = "okay"; dr_mode = "peripheral";