From patchwork Thu Dec 7 23:05:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 845902 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="BzhECA5A"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ytB0s5679z9s84 for ; Fri, 8 Dec 2017 10:05:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752228AbdLGXFs (ORCPT ); Thu, 7 Dec 2017 18:05:48 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:33431 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752366AbdLGXFr (ORCPT ); Thu, 7 Dec 2017 18:05:47 -0500 Received: by mail-pf0-f196.google.com with SMTP id y89so5824274pfk.0 for ; Thu, 07 Dec 2017 15:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:cc:from:to; bh=qgNwwWsCVay1W1ts/qGaOHFGbz79BjbsYxYgTbL6ZaY=; b=BzhECA5As6KtZjZXP61/a0gwAF+WIth2dWD3opIZsD3iZLH3M+aaq0p3O2OyyAFc8U QA9n5kn/X+IrOCG2sI8hqLfbM58jR1N7LG0MMHuQEfhdhvEay2qbuqNjByGPiCH7JM3W mgmXX5fpCPv3quEwuBj2xnXrpUHVLh1ByB5r4Qwqe/FO02sI4sL7IGimyOXUJKvhuVAe KiVytx9wsC4ehT8hl1a70AaVIxySHVwrZ+CIWxf91o7o4ZK46n6KxN8mqjJpDgWI2lOB VmIrwwSbIXpNNsUoS1r0ofiFXWUCOqzm3E0CZrRzH9odE2+K7GthhpHihjICUTh/hOoI OOTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=qgNwwWsCVay1W1ts/qGaOHFGbz79BjbsYxYgTbL6ZaY=; b=gRgEFUP/SjMm6/Zat76V3sM/jewn52A8/JIr06VqPXfieuGUvUBvq1ZE/QLJw2NBOA Y+fUhIj76SV894e8zF52xgjJjc3qbkbQxK+2thbiYiLc+1NSi06JR8ak3tkLZDfR4J/L bCFnGU9oj/W6inJgioJCDZjpL/p7LDiKkXitItQa12IT3XRYB+2AgQvFB8jfiSc8B9DF 1KGq/4sre8bY5bdmU4ZNluTmE8REhlSdyeCN/Qezf/TScc9JlzwSkWRx+/BDuZTsuf0q l9xFVm7XZzJkm8sYxljhiAZolpGP1R0oMX1MgWoN5I6hW3xW5kS//aKILhxIy5wmgK9K MADg== X-Gm-Message-State: AJaThX7pWU4M13jZYtJH4HgfUjhsUT3EoIIDbHQwLEuQYNknQY5iwQiq oKmPP+8QFVi3ZT72xjEXgr559UjsycwvIw== X-Google-Smtp-Source: AGs4zMbmOiow95OMsofy4g+usCvQj1/OE98NcQA0UUrzCgK6x6RBkEOHTnCNvB2Ed+f9Yr87GGxS0A== X-Received: by 10.99.95.203 with SMTP id t194mr26927830pgb.161.1512687946459; Thu, 07 Dec 2017 15:05:46 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id u12sm12297361pfi.87.2017.12.07.15.05.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Dec 2017 15:05:45 -0800 (PST) Subject: [PATCH v2] dt-bindings: Add an enable method to RISC-V Date: Thu, 7 Dec 2017 15:05:23 -0800 Message-Id: <20171207230523.29798-1-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 Cc: devicetree@vger.kernel.org, patches@groups.riscv.org, linux-kernel@vger.kernel.org, Palmer Dabbelt From: Palmer Dabbelt To: robh+dt@kernel.org, mark.rutland@arm.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop. Future systems may have an explicit mechanism for putting a CPU to sleep, so we're standardizing the device tree entry for when that happens. We're not defining a spin-table based interface to the firmware, as the plan is to handle this entirely within the kernel instead. CC: Mark Rutland Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..68f88eacc594 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,15 @@ described below. Value type: Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: optional + Value type: + Definition: When absent, default is either "always-disabled" + "always-enabled", depending on the current state + of the CPU. + Must be one of: + * "always-disabled": This CPU cannot be enabled. + * "always-enabled": This CPU cannot be disabled. Example: SiFive Freedom U540G Development Kit ---------------------------------------------