From patchwork Tue Apr 21 21:51:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274538 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=MfxqZ/BP; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496HNS1nJqz9sSJ for ; Wed, 22 Apr 2020 07:52:20 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 780AF804CD; Tue, 21 Apr 2020 23:52:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="MfxqZ/BP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0343C80574; Tue, 21 Apr 2020 23:52:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa2.hgst.iphmx.com (esa2.hgst.iphmx.com [68.232.143.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 63FB18047E for ; Tue, 21 Apr 2020 23:52:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=wdc.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=prvs=37371f929=atish.patra@wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1587505925; x=1619041925; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=k4qFrHuYAYh5pbsYPnJdsS+fpvdTMax4hCk8g4dc9Is=; b=MfxqZ/BP8nJlqLcbj/RXB/4m3bG6Y5eFv9ocZ+7jBzU/8lT4KjL5fejS 0uylP0biCjKZOFIsony7uH7hAghUQmsKVrBxcbSjdU0/GagJosBqb5Qig RX2ZiKwWz54JdulNWzi8aAqBicdSvJOoGaD6MBTH4D0Jt+b/7xGW8y8oC oerTHKfzZtCGVcnxnWhOA11sOeOSsFjT3oX/K516CPO6TbTjCfVRzdmP0 sX4AR9poDHWG9N4eFvMYZN5KDn6Az8Zm1OuI83pkymuuYnrzuLp1EmGtx h9yyJyG0d0X1BGX4TuQUa19n/+6FBj0LPIQHdkyW81xSmGxY0+/V3/sJG Q==; IronPort-SDR: Clo+ya8BWbrvhgV2Vu/9VV9iHiDJ09Hyc6AVSZJL9hg+Wj/Zr9Tz4iYX76OhyO0/Itf9kFIGer O9QtBGJmemxkDiGOW2QPuPuFGEqeFb7dZRH4ZufMlneWbRjMgw3innsJV5vaEKyvg8jGdmBcBZ 4M4/W4DmxUvTijib8jsNRQ+B1UNVqHC0XxdVDE4RdasP8PVhpHuuiURRVGSBzB3y3AvSEQJ0ST Ej1a2eJph33vKDJVPrXH6mHw7yWf8/pvqU2W6U29fxZgZ6Jeabxo5SvuGB3ZbaDbwkKtECsqmb lR0= X-IronPort-AV: E=Sophos;i="5.72,411,1580745600"; d="scan'208";a="238294906" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 05:52:15 +0800 IronPort-SDR: 9g+lExZoxmpfMCSISbIOKFGzLljasIq35OFQiepJ2S0HUGbGGlktXoSuyp0P1gW4hr1nO3QmVv 7QzV1ZfmNs1yDjOsOyj7uRRS0hW3s8DeA= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 14:42:52 -0700 IronPort-SDR: rmn0VtfiEz+gcqWW1g7nwQ3BTT6fEkC1BB9+QWJMSb924myFQ0Ear9DxOhQw/0xyrupClg6u1H 4uO2EWj2xeHw== WDCIronportException: Internal Received: from bwg3rc2.ad.shared (HELO yoda.hgst.com) ([10.86.56.48]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Apr 2020 14:52:01 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Anup Patel , Bin Meng , Lukas Auer , Rick Chen , palmer@dabbelt.com Subject: [PATCH] riscv: Move all SMP related SBI calls to SBI_v01 Date: Tue, 21 Apr 2020 14:51:57 -0700 Message-Id: <20200421215157.440457-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled. There is no point in supporting SMP related (IPI and fences) SBI calls when SBI_V02 is enabled. Modify all the SMP related SBI calls to be defined only for SBI_V01. Signed-off-by: Atish Patra Reviewed-by: Bin Meng --- arch/riscv/include/asm/sbi.h | 5 ++--- arch/riscv/lib/sbi.c | 37 ++++++++++++++++++------------------ 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3595ee8bf7ee..453cb5cec5eb 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -106,8 +106,6 @@ void sbi_console_putchar(int ch); int sbi_console_getchar(void); void sbi_clear_ipi(void); void sbi_shutdown(void); -#endif -void sbi_set_timer(uint64_t stime_value); void sbi_send_ipi(const unsigned long *hart_mask); void sbi_remote_fence_i(const unsigned long *hart_mask); void sbi_remote_sfence_vma(const unsigned long *hart_mask, @@ -117,7 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start, unsigned long size, unsigned long asid); - +#endif +void sbi_set_timer(uint64_t stime_value); int sbi_probe_extension(int ext); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 7bdf071dbbe5..993597e33db1 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -39,6 +39,23 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, return ret; } +/** + * sbi_set_timer() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. + * + * Return: None + */ +void sbi_set_timer(uint64_t stime_value) +{ +#if __riscv_xlen == 32 + sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, + stime_value >> 32, 0, 0, 0, 0); +#else + sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, + 0, 0, 0, 0, 0); +#endif +} + #ifdef CONFIG_SBI_V01 /** @@ -86,25 +103,6 @@ void sbi_shutdown(void) sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } -#endif /* CONFIG_SBI_V01 */ - -/** - * sbi_set_timer() - Program the timer for next timer event. - * @stime_value: The value after which next timer event should fire. - * - * Return: None - */ -void sbi_set_timer(uint64_t stime_value) -{ -#if __riscv_xlen == 32 - sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, - stime_value >> 32, 0, 0, 0, 0); -#else - sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, - 0, 0, 0, 0, 0); -#endif -} - /** * sbi_send_ipi() - Send an IPI to any hart. * @hart_mask: A cpu mask containing all the target harts. @@ -185,3 +183,4 @@ int sbi_probe_extension(int extid) return -ENOTSUPP; } +#endif /* CONFIG_SBI_V01 */