From patchwork Tue Apr 21 18:14:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274457 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=J/GmQfOB; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496BZK2TNJz9sSJ for ; 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d="scan'208";a="135816941" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 02:15:14 +0800 IronPort-SDR: HYqbvdxmPqz0/Jjsl4cNvUu8EeNntz1gHbmFw4If/cSsnDOtHHZMXw8heL/7qlyS3r9EF00lzP O2TPExhHGF9uBvm6hloaIZIAhGGd+z1xU= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 11:05:33 -0700 IronPort-SDR: fMkDL1Hu+Wo3jZxstuHQNPjU6mb9Kgny381drBqkf9CdsKKuuIOi5f2BKkvHWwelNY0JWizadU Pwrbch9KtaHg== WDCIronportException: Internal Received: from usa001638.ad.shared (HELO yoda.hgst.com) ([10.86.55.248]) by uls-op-cesaip01.wdc.com with ESMTP; 21 Apr 2020 11:15:15 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Rick Chen , Bin Meng , Heinrich Schuchardt , Anup Patel , Lukas Auer , palmer@dabbelt.com Subject: [PATCH v7 1/6] riscv: Add boot hartid to device tree Date: Tue, 21 Apr 2020 11:14:59 -0700 Message-Id: <20200421181504.415822-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200421181504.415822-1-atish.patra@wdc.com> References: <20200421181504.415822-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Linux booting protocol mandates that register "a0" contains the hartid. However, U-Boot can not pass the hartid via a0 during standard UEFI protocol. DT nodes are commonly used to pass such information to the OS. Add a DT node under chosen node to indicate the boot hartid. EFI stub in Linux kernel will parse this node and pass it to the real kernel in "a0" before jumping to it. Signed-off-by: Atish Patra Reviewed-by: Rick Chen Reviewed-by: Bin Meng Tested-by: Heinrich Schuchardt Tested-by: Bin Meng --- arch/riscv/lib/bootm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index fad16901c5f2..87cadad5016d 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -28,6 +28,28 @@ __weak void board_quiesce_devices(void) int arch_fixup_fdt(void *blob) { +#ifdef CONFIG_EFI_LOADER + int err; + u32 size; + int chosen_offset; + + size = fdt_totalsize(blob); + err = fdt_open_into(blob, blob, size + 32); + if (err < 0) { + printf("Device Tree can't be expanded to accommodate new node"); + return err; + } + chosen_offset = fdt_path_offset(blob, "/chosen"); + if (chosen_offset < 0) { + err = fdt_add_subnode(blob, 0, "chosen"); + if (err < 0) { + printf("chosen node can not be added\n"); + return err; + } + } + /* Overwrite the boot-hartid as U-Boot is the last stage BL */ + fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart); +#endif return 0; } From patchwork Tue Apr 21 18:15:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274460 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=N+crW2IO; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496Bb94qpWz9sSJ for ; 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d="scan'208";a="135816945" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 02:15:15 +0800 IronPort-SDR: JScZJDgB/lzPk+eGhlFLfafRGmrmvG+a0blAn0uEcnVKvrhaBR3cepNAYReRXaz87u7HroPucO Z+/PtxfHJYQc6Iev3U/q9iblJePczkqS4= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 11:05:33 -0700 IronPort-SDR: at1u8SQrxhf2HDAbmIntjnooTmdp5AgtPpOa2FaXLGGKCXomACwnMrFUOdh7hP5pmc42JwCU2/ /6Nj5eyaY0cQ== WDCIronportException: Internal Received: from usa001638.ad.shared (HELO yoda.hgst.com) ([10.86.55.248]) by uls-op-cesaip01.wdc.com with ESMTP; 21 Apr 2020 11:15:16 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Bin Meng , Anup Patel , Lukas Auer , Heinrich Schuchardt , Rick Chen , palmer@dabbelt.com Subject: [PATCH v7 2/6] fdtdec: Fix boundary check Date: Tue, 21 Apr 2020 11:15:00 -0700 Message-Id: <20200421181504.415822-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200421181504.415822-1-atish.patra@wdc.com> References: <20200421181504.415822-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In U-Boot, the reserved memory end address is considered as a inclusive address. This notion is followed while adding a reserved memory node to the DT. For example: end_address = start_address + size - 1 Follow the same notion and fix the end address computation while checking for existing nodes. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng --- lib/fdtdec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9ecfa2a2d743..460f0d250b4d 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1311,7 +1311,8 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, continue; } - if (addr == carveout->start && (addr + size) == carveout->end) { + if (addr == carveout->start && (addr + size - 1) == + carveout->end) { if (phandlep) *phandlep = fdt_get_phandle(blob, node); return 0; From patchwork Tue Apr 21 18:15:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274463 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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d="scan'208";a="135816948" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 02:15:15 +0800 IronPort-SDR: 1ZcBpMceLYs75orOJ2GypiZbpPB9nQNHEFTxBm8pFMtb+6CO2iYsAecVe7wyqgPNu5WT3Ubzyu gtrY/XamzrKcfhei3ozy32Y573u6/Xoec= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 11:05:34 -0700 IronPort-SDR: hXX7ACrWGpUSXJBJUCK+MrnqGAj8xhdkZMT+lCcyuZ7UhVKqW1vmID0g/TY5fmHNw+dRbNNSCQ y8DYZX3D07sQ== WDCIronportException: Internal Received: from usa001638.ad.shared (HELO yoda.hgst.com) ([10.86.55.248]) by uls-op-cesaip01.wdc.com with ESMTP; 21 Apr 2020 11:15:16 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Bin Meng , Anup Patel , Lukas Auer , Heinrich Schuchardt , Rick Chen , palmer@dabbelt.com Subject: [PATCH v7 3/6] riscv: Provide a mechanism to fix DT for reserved memory Date: Tue, 21 Apr 2020 11:15:01 -0700 Message-Id: <20200421181504.415822-4-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200421181504.415822-1-atish.patra@wdc.com> References: <20200421181504.415822-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean In RISC-V, M-mode software can reserve physical memory regions by setting appropriate physical memory protection (PMP) csr. As the PMP csr are accessible only in M-mode, S-mode U-Boot can not read this configuration directly. However, M-mode software can pass this information via reserved-memory node in device tree so that S-mode software can access this information. This patch provides a framework to copy to the reserved-memory node from one DT to another. This will be used to update the DT used by U-Boot and the DT passed to the next stage OS. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/cpu/start.S | 1 + arch/riscv/include/asm/global_data.h | 1 + arch/riscv/include/asm/u-boot-riscv.h | 2 + arch/riscv/lib/Makefile | 1 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/fdt_fixup.c | 102 ++++++++++++++++++++++++++ 6 files changed, 108 insertions(+) create mode 100644 arch/riscv/lib/fdt_fixup.c diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 1cedbef6cfaf..f408e41ab9dc 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -121,6 +121,7 @@ call_board_init_f_0: jal board_init_f_init_reserve + SREG s1, GD_FIRMWARE_FDT_ADDR(gp) /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index e0875ebf8f9d..2eb14815bcf0 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -17,6 +17,7 @@ /* Architecture-specific global data */ struct arch_global_data { long boot_hart; /* boot hart id */ + phys_addr_t firmware_fdt_addr; #ifdef CONFIG_SIFIVE_CLINT void __iomem *clint; /* clint base address */ #endif diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h index 49febd588102..543a1688db8f 100644 --- a/arch/riscv/include/asm/u-boot-riscv.h +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -17,5 +17,7 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); void board_quiesce_devices(void); +int riscv_board_reserved_mem_fixup(void *fdt); +int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt); #endif /* _U_BOOT_RISCV_H_ */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index bd7b2c4d162b..b5e93244e0ec 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -24,6 +24,7 @@ obj-y += reset.o obj-y += setjmp.o obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o +obj-y += fdt_fixup.o # For building EFI apps CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index 4fa4fd371473..7301c1b98e23 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,6 +14,7 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); + DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); #ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); #endif diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c new file mode 100644 index 000000000000..1fce41490973 --- /dev/null +++ b/arch/riscv/lib/fdt_fixup.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Western Digital Corporation or its affiliates + * + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * riscv_fdt_copy_resv_mem_node() - Copy reserve memory node entry + * @src: Pointer to the source device tree from which reserved memory node + * needs to be copied. + * @dst: Pointer to the destination device tree to which reserved memory node + * needs to be copied. + * + * Return: 0 on success or if source doesn't have reserved memory node. + * Error if copy process failed. + */ +int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) +{ + u32 phandle; + struct fdt_memory pmp_mem; + fdt_addr_t addr; + fdt_size_t size; + int offset, node, err, rmem_offset; + bool nomap = true; + char basename[32] = {0}; + int bname_len; + int max_len = sizeof(basename); + const char *name; + char *temp; + + offset = fdt_path_offset(src, "/reserved-memory"); + if (offset < 0) { + printf("No reserved memory region found in source FDT\n"); + return 0; + } + + fdt_for_each_subnode(node, src, offset) { + name = fdt_get_name(src, node, NULL); + + addr = fdtdec_get_addr_size_auto_noparent(src, node, + "reg", 0, &size, + false); + if (addr == FDT_ADDR_T_NONE) { + debug("failed to read address/size for %s\n", name); + continue; + } + strncpy(basename, name, max_len); + temp = strchr(basename, '@'); + if (temp) { + bname_len = strnlen(basename, max_len) - strnlen(temp, + max_len); + *(basename + bname_len) = '\0'; + } + pmp_mem.start = addr; + pmp_mem.end = addr + size - 1; + err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, + &phandle); + if (err < 0) { + printf("failed to add reserved memory: %d\n", err); + return err; + } + if (!fdt_getprop(src, node, "no-map", NULL)) + nomap = false; + if (nomap) { + rmem_offset = fdt_node_offset_by_phandle(dst, phandle); + fdt_setprop_empty(dst, rmem_offset, "no-map"); + } + } + + return 0; +} + +/** + * riscv_board_reserved_mem_fixup() - Fix up reserved memory node for a board + * @fdt: Pointer to the device tree in which reserved memory node needs to be + * added. + * + * In RISC-V, any board compiled with OF_SEPARATE needs to copy the reserved + * memory node from the device tree provided by the firmware to the device tree + * used by U-Boot. This is a common function that individual board fixup + * functions can invoke. + * + * Return: 0 on success or error otherwise. + */ +int riscv_board_reserved_mem_fixup(void *fdt) +{ + int err; + void *src_fdt_addr; + + src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0); + err = riscv_fdt_copy_resv_mem_node(src_fdt_addr, fdt); + if (err < 0) + return err; + + return 0; +} From patchwork Tue Apr 21 18:15:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274461 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; 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Enable OF_BOARD_FIXUP to update the DT with reserved-memory node. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/lib/fdt_fixup.c | 15 +++++++++++++++ configs/sifive_fu540_defconfig | 1 + 2 files changed, 16 insertions(+) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 1fce41490973..af12e484db9b 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -100,3 +100,18 @@ int riscv_board_reserved_mem_fixup(void *fdt) return 0; } + +#ifdef CONFIG_OF_BOARD_FIXUP +int board_fix_fdt(void *fdt) +{ + int err; + + err = riscv_board_reserved_mem_fixup(fdt); + if (err < 0) { + printf("failed to fixup DT for reserved memory: %d\n", err); + return err; + } + + return 0; +} +#endif diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 6d61e6c960ee..f805aacc7afd 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -9,6 +9,7 @@ CONFIG_FIT=y CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y From patchwork Tue Apr 21 18:15:03 2020 Content-Type: text/plain; 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In that case, the reserved-memory node needs to be copied to the DT passed to the OS. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/lib/bootm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 87cadad5016d..8ff8db6bf533 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -28,8 +28,8 @@ __weak void board_quiesce_devices(void) int arch_fixup_fdt(void *blob) { -#ifdef CONFIG_EFI_LOADER int err; +#ifdef CONFIG_EFI_LOADER u32 size; int chosen_offset; @@ -50,6 +50,12 @@ int arch_fixup_fdt(void *blob) /* Overwrite the boot-hartid as U-Boot is the last stage BL */ fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart); #endif + + /* Copy the reserved-memory node to the DT used by OS */ + err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob); + if (err < 0) + return err; + return 0; } From patchwork Tue Apr 21 18:15:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1274462 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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d="scan'208";a="135816955" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Apr 2020 02:15:16 +0800 IronPort-SDR: 970XndC/3U8Hl8M82HmNIor0wdzRQZS/bzhp7iQl03zRvXnQHWo5fUiO8tASj5jFXkcgnAW2yI hckMojyUpfaBIDqpCvph6mM+OEV19uttM= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2020 11:05:35 -0700 IronPort-SDR: BFQPSVPN2O6EZaXYksq98euaeF4AVxwZiFVtYD4OtTwHthnspkw3p/J77ghx8ei/tq532e0OCp EdP79TMfSANg== WDCIronportException: Internal Received: from usa001638.ad.shared (HELO yoda.hgst.com) ([10.86.55.248]) by uls-op-cesaip01.wdc.com with ESMTP; 21 Apr 2020 11:15:17 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Bin Meng , Anup Patel , Lukas Auer , Heinrich Schuchardt , Rick Chen , palmer@dabbelt.com Subject: [PATCH v7 6/6] riscv: Move all fdt fixups together Date: Tue, 21 Apr 2020 11:15:04 -0700 Message-Id: <20200421181504.415822-7-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200421181504.415822-1-atish.patra@wdc.com> References: <20200421181504.415822-1-atish.patra@wdc.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Keep all the fdt fixups together for better code management. Signed-off-by: Atish Patra Reviewed-by: Bin Meng --- arch/riscv/lib/bootm.c | 33 --------------------------------- arch/riscv/lib/fdt_fixup.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 8ff8db6bf533..0d06095da11a 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -26,39 +26,6 @@ __weak void board_quiesce_devices(void) { } -int arch_fixup_fdt(void *blob) -{ - int err; -#ifdef CONFIG_EFI_LOADER - u32 size; - int chosen_offset; - - size = fdt_totalsize(blob); - err = fdt_open_into(blob, blob, size + 32); - if (err < 0) { - printf("Device Tree can't be expanded to accommodate new node"); - return err; - } - chosen_offset = fdt_path_offset(blob, "/chosen"); - if (chosen_offset < 0) { - err = fdt_add_subnode(blob, 0, "chosen"); - if (err < 0) { - printf("chosen node can not be added\n"); - return err; - } - } - /* Overwrite the boot-hartid as U-Boot is the last stage BL */ - fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart); -#endif - - /* Copy the reserved-memory node to the DT used by OS */ - err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob); - if (err < 0) - return err; - - return 0; -} - /** * announce_and_cleanup() - Print message and prepare for kernel boot * diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index af12e484db9b..20e0759f135b 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -115,3 +115,36 @@ int board_fix_fdt(void *fdt) return 0; } #endif + +int arch_fixup_fdt(void *blob) +{ + int err; +#ifdef CONFIG_EFI_LOADER + u32 size; + int chosen_offset; + + size = fdt_totalsize(blob); + err = fdt_open_into(blob, blob, size + 32); + if (err < 0) { + printf("Device Tree can't be expanded to accommodate new node"); + return err; + } + chosen_offset = fdt_path_offset(blob, "/chosen"); + if (chosen_offset < 0) { + err = fdt_add_subnode(blob, 0, "chosen"); + if (err < 0) { + printf("chosen node can not be added\n"); + return err; + } + } + /* Overwrite the boot-hartid as U-Boot is the last stage BL */ + fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart); +#endif + + /* Copy the reserved-memory node to the DT used by OS */ + err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob); + if (err < 0) + return err; + + return 0; +}