From patchwork Fri Apr 17 11:43:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1272198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=otTGev+v; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 493Z3t6b1Yz9sSc for ; Fri, 17 Apr 2020 21:43:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730471AbgDQLnh (ORCPT ); Fri, 17 Apr 2020 07:43:37 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41232 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730267AbgDQLng (ORCPT ); Fri, 17 Apr 2020 07:43:36 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhTIb117964; Fri, 17 Apr 2020 06:43:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1587123809; bh=Cap1tvbqaDFf7dgKUHyGKcKtjUQTmukHG8tZAX/s2I0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=otTGev+vcIDAJcC6cIkmbRV6RQCAViQT9rBqHgBCj67pBDFTSVLzPO4b+i5ruKkLq RyBrFnNYv5cgnDpzXryefWZ371u9FNaTdGWyyisD2LNLFD3t8WMatzR2tqiOPdEoj5 myCd1nCcTnZPMG2aJXReedyRV6/+RZkIv6MxYndg= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03HBhTcp004830 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Apr 2020 06:43:29 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 17 Apr 2020 06:43:29 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 17 Apr 2020 06:43:29 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhN9o088610; Fri, 17 Apr 2020 06:43:27 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Andrew Murray CC: , , Subject: [PATCH v2 1/4] dt-bindings: PCI: cadence: Deprecate inbound/outbound specific bindings Date: Fri, 17 Apr 2020 17:13:19 +0530 Message-ID: <20200417114322.31111-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417114322.31111-1-kishon@ti.com> References: <20200417114322.31111-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Deprecate cdns,max-outbound-regions and cdns,no-bar-match-nbits for host mode as both these could be derived from "ranges" and "dma-ranges" property. "cdns,max-outbound-regions" property would still be required for EP mode. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/cdns,cdns-pcie-ep.yaml | 2 +- .../bindings/pci/cdns,cdns-pcie-host.yaml | 3 +-- .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 25 +++++++++++++++++++ .../bindings/pci/cdns-pcie-host.yaml | 10 ++++++++ .../devicetree/bindings/pci/cdns-pcie.yaml | 8 ------ 5 files changed, 37 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml index 2996f8d4777c..50ce5d79d2c7 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml @@ -10,7 +10,7 @@ maintainers: - Tom Joseph allOf: - - $ref: "cdns-pcie.yaml#" + - $ref: "cdns-pcie-ep.yaml#" - $ref: "pci-ep.yaml#" properties: diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index cabbe46ff578..84a8f095d031 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -45,8 +45,6 @@ examples: #size-cells = <2>; bus-range = <0x0 0xff>; linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; vendor-id = <0x17cd>; device-id = <0x0200>; @@ -57,6 +55,7 @@ examples: ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; #interrupt-cells = <0x1>; diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml new file mode 100644 index 000000000000..6150a7a7bdbf --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Device + +maintainers: + - Tom Joseph + +allOf: + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + +required: + - cdns,max-outbound-regions diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml index ab6e43b636ec..3d64f85aeb39 100644 --- a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml @@ -14,6 +14,15 @@ allOf: - $ref: "cdns-pcie.yaml#" properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + deprecated: true + cdns,no-bar-match-nbits: description: Set into the no BAR match register to configure the number of least @@ -23,5 +32,6 @@ properties: minimum: 0 maximum: 64 default: 32 + deprecated: true msi-parent: true diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml index 6887ccc339cc..02553d5e6c51 100644 --- a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml @@ -10,14 +10,6 @@ maintainers: - Tom Joseph properties: - cdns,max-outbound-regions: - description: maximum number of outbound regions - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 32 - default: 32 - phys: description: One per lane if more than one in the list. If only one PHY listed it must From patchwork Fri Apr 17 11:43:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1272200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=C2MYEEEF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 493Z403nW3z9sSb for ; Fri, 17 Apr 2020 21:43:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730483AbgDQLnn (ORCPT ); Fri, 17 Apr 2020 07:43:43 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52138 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730267AbgDQLnn (ORCPT ); Fri, 17 Apr 2020 07:43:43 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhWuR034298; Fri, 17 Apr 2020 06:43:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1587123812; bh=4p1lIn3EJMxqLcKLHJpXFBYOnV80cp+ytaLCxJxeVys=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C2MYEEEFKqUKe3M0NTM29X5sg7Ae550POv5GOnplb4TCmJXi3YFTM2SR8gWFZZ1t5 UlyBULoohP3Gy1gaFRgKWqolbwfvCq9HgwZnWWSoYQo+cZ/vH++KsIJl+1sonN/+uI 2taahmjbBnuosvLDWxxCs6ohPQB8qHKsKRvuBiqU= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhW8x079693; Fri, 17 Apr 2020 06:43:32 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 17 Apr 2020 06:43:32 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 17 Apr 2020 06:43:32 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhN9p088610; Fri, 17 Apr 2020 06:43:30 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Andrew Murray CC: , , Subject: [PATCH v2 2/4] PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property Date: Fri, 17 Apr 2020 17:13:20 +0530 Message-ID: <20200417114322.31111-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417114322.31111-1-kishon@ti.com> References: <20200417114322.31111-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits" property to configure the number of bits passed through from PCIe address to internal address in Inbound Address Translation register. However standard PCI dt-binding already defines "dma-ranges" to describe the address range accessible by PCIe controller. Parse "dma-ranges" property to configure the number of bits passed through from PCIe address to internal address in Inbound Address Translation register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 9b1c3966414b..60f912a657b9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -206,8 +206,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) struct device *dev = rc->pcie.dev; struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; + struct of_pci_range_parser parser; struct pci_host_bridge *bridge; struct list_head resources; + struct of_pci_range range; struct cdns_pcie *pcie; struct resource *res; int ret; @@ -222,8 +224,15 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) rc->max_regions = 32; of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions); - rc->no_bar_nbits = 32; - of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits); + if (!of_pci_dma_range_parser_init(&parser, np)) + if (of_pci_range_parser_one(&parser, &range)) + rc->no_bar_nbits = ilog2(range.size); + + if (!rc->no_bar_nbits) { + rc->no_bar_nbits = 32; + of_property_read_u32(np, "cdns,no-bar-match-nbits", + &rc->no_bar_nbits); + } rc->vendor_id = 0xffff; of_property_read_u16(np, "vendor-id", &rc->vendor_id); From patchwork Fri Apr 17 11:43:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1272202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=EXTd0EIW; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 493Z4B5fhMz9sSh for ; Fri, 17 Apr 2020 21:43:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730508AbgDQLnx (ORCPT ); Fri, 17 Apr 2020 07:43:53 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52148 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730267AbgDQLnx (ORCPT ); Fri, 17 Apr 2020 07:43:53 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhZZg034317; Fri, 17 Apr 2020 06:43:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1587123815; bh=6aSSBM0i5VIvjL6XkO+db3ofrSudsLQ7qzAvGhFRHCU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EXTd0EIWvC7SWpmIxLbRFkVaZUc/KPij8Qp5DOBtz8sNc6xk9pyIK18WgTBiBJf/9 McKh1rsNmh9ja64Krjyhp4MsYvZBKp/OZjwo51hXVTOUqxHoBoIJ0oY4i20iR2nJrH B5dNe1dnvLs2Cb+LrJ8VNLGS7qSqRAi4fdLlng9k= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03HBhZSL086674 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Apr 2020 06:43:35 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 17 Apr 2020 06:43:35 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 17 Apr 2020 06:43:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhN9q088610; Fri, 17 Apr 2020 06:43:32 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Andrew Murray CC: , , Subject: [PATCH v2 3/4] PCI: cadence: Remove "cdns,max-outbound-regions" DT property Date: Fri, 17 Apr 2020 17:13:21 +0530 Message-ID: <20200417114322.31111-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417114322.31111-1-kishon@ti.com> References: <20200417114322.31111-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org "cdns,max-outbound-regions" device tree property provides the maximum number of outbound regions supported by the Host PCIe controller. However the outbound regions are configured based on what is populated in the "ranges" DT property. Avoid using two properties for configuring outbound regions and use only "ranges" property instead. Signed-off-by: Kishon Vijay Abraham I Acked-by: Rob Herring --- drivers/pci/controller/cadence/pcie-cadence-host.c | 6 ------ drivers/pci/controller/cadence/pcie-cadence.h | 2 -- 2 files changed, 8 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 60f912a657b9..8f72967f298f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) for_each_of_pci_range(&parser, &range) { bool is_io; - if (r >= rc->max_regions) - break; - if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM) is_io = false; else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) @@ -221,9 +218,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) pcie = &rc->pcie; pcie->is_rc = true; - rc->max_regions = 32; - of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions); - if (!of_pci_dma_range_parser_init(&parser, np)) if (of_pci_range_parser_one(&parser, &range)) rc->no_bar_nbits = ilog2(range.size); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index a2b28b912ca4..6bd89a21bb1c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -251,7 +251,6 @@ struct cdns_pcie { * @bus_range: first/last buses behind the PCIe host controller * @cfg_base: IO mapped window to access the PCI configuration space of a * single function at a time - * @max_regions: maximum number of regions supported by the hardware * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address * translation (nbits sets into the "no BAR match" register) * @vendor_id: PCI vendor ID @@ -262,7 +261,6 @@ struct cdns_pcie_rc { struct resource *cfg_res; struct resource *bus_range; void __iomem *cfg_base; - u32 max_regions; u32 no_bar_nbits; u16 vendor_id; u16 device_id; From patchwork Fri Apr 17 11:43:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1272201 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=UQPIvFrI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 493Z4866d7z9sSh for ; Fri, 17 Apr 2020 21:43:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730498AbgDQLns (ORCPT ); Fri, 17 Apr 2020 07:43:48 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41248 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730267AbgDQLnr (ORCPT ); Fri, 17 Apr 2020 07:43:47 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhc3J117988; Fri, 17 Apr 2020 06:43:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1587123818; bh=uIHdkFGjC9VWJ1dYkQdiB11X9Q9MgdISnGvSAMPmGOk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UQPIvFrIGRIgPv38LmUwM8V77wmp2WwDQbHN9JZuruf1RVfbVejgbm7xxQ3fzFABs JoFIc7otCdR+Ko/AQkxJuulz/ZSoikmToRAh5NTZUaGK/di2EFSXq+7zxIWBeknNiB dKxHhk+FrxtWvQD+aSPT4OgSlMxHUefwodhOLi2s= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 03HBhcVh004871 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Apr 2020 06:43:38 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Fri, 17 Apr 2020 06:43:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Fri, 17 Apr 2020 06:43:38 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 03HBhN9r088610; Fri, 17 Apr 2020 06:43:35 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Andrew Murray CC: , , Subject: [PATCH v2 4/4] PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT Date: Fri, 17 Apr 2020 17:13:22 +0530 Message-ID: <20200417114322.31111-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417114322.31111-1-kishon@ti.com> References: <20200417114322.31111-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1]) defines both Vendor ID and Device ID to be 32-bits. Fix pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID properties from device tree. [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Signed-off-by: Kishon Vijay Abraham I Acked-by: Rob Herring --- drivers/pci/controller/cadence/pcie-cadence-host.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 8f72967f298f..31e67c9c88cf 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -229,10 +229,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) } rc->vendor_id = 0xffff; - of_property_read_u16(np, "vendor-id", &rc->vendor_id); + of_property_read_u32(np, "vendor-id", &rc->vendor_id); rc->device_id = 0xffff; - of_property_read_u16(np, "device-id", &rc->device_id); + of_property_read_u32(np, "device-id", &rc->device_id); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); pcie->reg_base = devm_ioremap_resource(dev, res); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 6bd89a21bb1c..df14ad002fe9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -262,8 +262,8 @@ struct cdns_pcie_rc { struct resource *bus_range; void __iomem *cfg_base; u32 no_bar_nbits; - u16 vendor_id; - u16 device_id; + u32 vendor_id; + u32 device_id; }; /**