From patchwork Wed Apr 15 16:00:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=pSWOREUi; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RtM6DLKz9sT7 for ; Thu, 16 Apr 2020 02:01:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1415140AbgDOQBZ (ORCPT ); Wed, 15 Apr 2020 12:01:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:52110 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1414829AbgDOQBV (ORCPT ); Wed, 15 Apr 2020 12:01:21 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C5CB42076A; Wed, 15 Apr 2020 16:01:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966480; bh=J8J9WMwWS0+Nqarse/8WxRYuf4GlYENWHZo2OGXUjKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pSWOREUiD0QyAT3wncvo6YXKZ7r2a12iyRZ9ucG1zxrvP1MBWnntz83T4y1ezzUBP m6h48V3XO19PG0nrXOXZNM0sho3LqIXvEk4T5g5X7O3LuFcMxIrtBQnqfK9au5fOUY bPUx8zTegC6K8zfTGs1UurAC4imBhSZEJMSaaeEA= Received: by pali.im (Postfix) id 2C50C58E; Wed, 15 Apr 2020 18:01:19 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/8] PCI: aardvark: Set controller speed from Device Tree max-link-speed Date: Wed, 15 Apr 2020 18:00:47 +0200 Message-Id: <20200415160054.951-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org bindings/pci/pci.txt defines standard DT property max-link-speed for specifying PCI gen of link. Read this property from Device Tree via of_pci_get_max_link_speed() function and use it for configuring aardvark PCI controller gen speed. Before this change aardvark PCI gen speed was configured always to hardcoded value gen2. When Device Tree does not specify max-link-speed property use by default gen3 value, maximum which aardvark PCI controller supports. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 32 ++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 2a20b649f40c..ad4f0fa57624 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -253,8 +253,30 @@ static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) } } +static void advk_pcie_setup_link_speed(struct advk_pcie *pcie, int link_speed) +{ + u32 reg; + + dev_info(&pcie->pdev->dev, "setup link speed to %d\n", link_speed); + + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~PCIE_GEN_SEL_MSK; + + if (link_speed == 3) + reg |= SPEED_GEN_3; + else if (link_speed == 2) + reg |= SPEED_GEN_2; + else + reg |= SPEED_GEN_1; + + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); +} + static void advk_pcie_setup_hw(struct advk_pcie *pcie) { + struct device *dev = &pcie->pdev->dev; + struct device_node *node = dev->of_node; + int max_link_speed; u32 reg; /* Set to Direct mode */ @@ -288,11 +310,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) PCIE_CORE_CTRL2_TD_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - /* Set GEN2 */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~PCIE_GEN_SEL_MSK; - reg |= SPEED_GEN_2; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* Set max link speed */ + max_link_speed = of_pci_get_max_link_speed(node); + if (max_link_speed <= 0 || max_link_speed > 3) + max_link_speed = 3; + advk_pcie_setup_link_speed(pcie, max_link_speed); /* Set lane X1 */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); From patchwork Wed Apr 15 16:00:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=I+6fg/CJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RtP6gk7z9sSk for ; Thu, 16 Apr 2020 02:01:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1415148AbgDOQBc (ORCPT ); Wed, 15 Apr 2020 12:01:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:52290 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1415142AbgDOQB0 (ORCPT ); Wed, 15 Apr 2020 12:01:26 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ECE3D208FE; Wed, 15 Apr 2020 16:01:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966486; bh=Whr+LkPvddPEdlzax+7iuEmKEeTaxYdFoa0JhjAYMp0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I+6fg/CJTctkQzt5X9MhH3chom+dZFcBbS3wXE82ZJD9pbWepWuch9jt7R1BpISBE 2f0wyE+t78HFjA2s5qxZAyXjFiyaLADrDwiy7r2vPTIFfIMrmrG+cj2fWNrXw+qXuo xEw9Ez+PiABBxv8f10yKG5VcEFDyL0isUG/kp4cQ= Received: by pali.im (Postfix) id 4FA4958E; Wed, 15 Apr 2020 18:01:24 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/8] dts: espressobin: Define max-link-speed for pcie0 Date: Wed, 15 Apr 2020 18:00:48 +0200 Message-Id: <20200415160054.951-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Previously aardvark PCI controller set speed to gen2. Now it reads speed from Device Tree and as default use maximal possible speed which is gen3. Because Espressobin has advertised only PCI Express 2.0 capability and previous value was gen2, define max-link-speed to 2, so there would not be any configuration change. Signed-off-by: Pali Rohár --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 42e992f9c8a5..6705618162d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -47,6 +47,7 @@ phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; + max-link-speed = <2>; }; /* J6 */ From patchwork Wed Apr 15 16:00:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271279 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=aaonqigE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492Rv10Xb2z9sT7 for ; Thu, 16 Apr 2020 02:02:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410066AbgDOQCB (ORCPT ); Wed, 15 Apr 2020 12:02:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:52436 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1415143AbgDOQB2 (ORCPT ); Wed, 15 Apr 2020 12:01:28 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8699E2137B; Wed, 15 Apr 2020 16:01:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966487; bh=qo96f8y7Ue3uthU1Q4HKKMi97vHqkzY5w+REOuqCXMQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aaonqigEYT5dMYmA3jOv/SCvtJ7IFgBOwME1O7eG4Px6MM/tN35uGtsFHQU8m3Joo cftOVLOp8D2S55eENIK9OS24i0O9f09lSVZPZ0DVH+8gMAMZUN8msOnVHrw+WoibHY mKojLMJcvI3erCXx459yhdfw86/pA8JlUeQY189E= Received: by pali.im (Postfix) id 8ECC49CC; Wed, 15 Apr 2020 18:01:25 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/8] PCI: aardvark: Start link training immediately after enabling link training Date: Wed, 15 Apr 2020 18:00:49 +0200 Message-Id: <20200415160054.951-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link training and starting link training cause that some Compex WLE900VX cards are not detected. So move code for enabling link training after PCI_PM_D3COLD_WAIT delay. This change fixes Compex WLE900VX cards detection on Turris MOX after cold boot. Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before training link") Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index ad4f0fa57624..756b31c4d20b 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -322,11 +322,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= LANE_COUNT_1; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - /* Enable link training */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg |= LINK_TRAINING_EN; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - /* Enable MSI */ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg |= PCIE_CORE_CTRL2_MSI_ENABLE; @@ -368,6 +363,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) */ msleep(PCI_PM_D3COLD_WAIT); + /* + * Do "Enable link training" and "Start link training" in a row without + * any delay between them. Adding even 100ms delay (PCI_PM_D3COLD_WAIT) + * cause that some Compex WLE900VX cards are not detected. + */ + + /* Enable link training */ + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg |= LINK_TRAINING_EN; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); /* Start link training */ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); reg |= PCIE_CORE_LINK_TRAINING; From patchwork Wed Apr 15 16:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=xzJPJVkZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RtW2hSWz9sT7 for ; Thu, 16 Apr 2020 02:01:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1415151AbgDOQBd (ORCPT ); Wed, 15 Apr 2020 12:01:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:52504 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1415145AbgDOQB2 (ORCPT ); Wed, 15 Apr 2020 12:01:28 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 418C620936; Wed, 15 Apr 2020 16:01:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966488; bh=46RjzSt2lZ7zcuoUcDDNbTHTfazol2LogceQfxy51Hs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xzJPJVkZxfwtu/a2eSdGtHTO119qdoyaejCCTJcaANPSKNcsyNk//UNMozna2NgCU f1vJxc7greQtfZUSTTd3tI+nORw6CeEItOAdA9t2MuBe3/roNbapKvpqqkpG7tZ4OF 1MQNU3Q83fYjfrQ283eHQokIIdm4FTZZ2rpOLc+k= Received: by pali.im (Postfix) id 673C058E; Wed, 15 Apr 2020 18:01:26 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 4/8] PCI: aardvark: Do not overwrite Link Status register and ASPM Control bits in Link Control register Date: Wed, 15 Apr 2020 18:00:50 +0200 Message-Id: <20200415160054.951-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Trying to overwrite or change Link Status register does not have any effect as this is read-only register. Trying to overwrite bits for Negotiated Link Width value in Link Status register does not make sense. So remove code which is doing it. In future proper change of link width can be done via Lane Count Select bits in PCIe Control 0 register. Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link Control register is wrong. There should be at least some detection if endpoint supports L0s as support for it is not mandatory. Moreover ASPM Control bits in Link Control register are controlled by pcie/aspm.c code which sets it according to system ASPM settings, immediately after aardvark driver probe callback finish. So setting these bits by aardvark driver has no long running effect. So remove code which touches ASPM L0s bits from aardvark driver and let kernel's ASPM implementation to set ASPM state properly. Some users are reporting issues that this code which unconditionally set ASPM L0s bits in Link Control register is problematic for some Intel wifi cards. And disabling that code fixes support for those cards. See e.g.: https://bugzilla.kernel.org/show_bug.cgi?id=196339 If problem with Intel wifi cards occur also after this commit then driver independent pcie/aspm.c code could be modified / hooked to not enable ASPM L0s state for affected problematic cards. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 756b31c4d20b..02c69fc9aadf 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -380,10 +380,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_pcie_wait_for_link(pcie); - reg = PCIE_CORE_LINK_L0S_ENTRY | - (1 << PCIE_CORE_LINK_WIDTH_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | PCIE_CORE_CMD_IO_ACCESS_EN | From patchwork Wed Apr 15 16:03:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=U8zu15N9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RxM2rJ6z9sTJ for ; Thu, 16 Apr 2020 02:04:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410154AbgDOQEC (ORCPT ); Wed, 15 Apr 2020 12:04:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:56642 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410141AbgDOQD7 (ORCPT ); Wed, 15 Apr 2020 12:03:59 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BBD8B21556; Wed, 15 Apr 2020 16:03:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966638; bh=1azI/ODf7w/ChnN2OTEWjI3fh/QSCsJ6Hav0dp8KUI4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U8zu15N9M/eHM+gXL+DeTLVeiuE28AuOZrQHF6S8D7gQK5kjVtysUTQSnfMafVOQs wxhqxQfCf8Hi3tJ/3GrfnzVZSv+3fEr20pi4FZOJRBgE038vudWyke3D3JXjaW3M6t naG/aiy5sF30zfcKRMRHm7jMJVR1GHEOP91X2+pQ= Received: by pali.im (Postfix) id F329858E; Wed, 15 Apr 2020 18:03:56 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 5/8] PCI: aardvark: Set final controller speed based on negotiated link speed Date: Wed, 15 Apr 2020 18:03:45 +0200 Message-Id: <20200415160348.1146-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some Compex WLE900VX gen1 cards are unstable or even not detected when aardvark PCI controller speed is set to gen2. Moreover when ASPM code tries to retrain link second time then these cards stop responding and link goes down. If aardvark PCI controller is set to gen1 then these cards work fine without any problem. Unconditionally forcing aardvark controller to gen1 speed (either via DT property max-link-speed or hardcoded value in driver itself) is not a solution as it would have performance impact for fast gen2 sata cards. To overcome this problem, try all 3 possible speeds (gen3, gen2, gen1) supported by aardvark PCI controller with respect to max-link-speed setting and after successful link training choose final controller speed based on Negotiated Link Speed from Link Status register, which should match card speed. I tested this change with Compex cards WLE200NX (pcie 1.0, gen1, ath9k), WLE900VX (pcie 1.1, gen1, ath10k) and WLE1216V5-20 (pcie 2.0, gen2, ath10k) on Turris MOX. Tomasz Maciej Nowak tested JJPlus JWX6051 (ath9k), Intel 622ANHMW, MT76 U7612E-H1 and Compex WLE1216V2-20 cards on Espressobin. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 35 +++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 02c69fc9aadf..a83bbc86e428 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -40,6 +40,7 @@ #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) #define PCIE_CORE_LINK_TRAINING BIT(5) +#define PCIE_CORE_LINK_SPEED_SHIFT 16 #define PCIE_CORE_LINK_WIDTH_SHIFT 20 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) @@ -276,7 +277,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) { struct device *dev = &pcie->pdev->dev; struct device_node *node = dev->of_node; - int max_link_speed; + int max_link_speed, neg_link_speed; u32 reg; /* Set to Direct mode */ @@ -378,7 +379,37 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= PCIE_CORE_LINK_TRAINING; advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); - advk_pcie_wait_for_link(pcie); + do { + if (advk_pcie_wait_for_link(pcie) < 0) { + max_link_speed--; + } else { + reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); + + neg_link_speed = + (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf; + dev_info(dev, "negotiated link speed %d\n", + neg_link_speed); + + if (neg_link_speed == max_link_speed) + break; + + if (neg_link_speed > 0 && neg_link_speed <= 3) + max_link_speed = neg_link_speed; + else + max_link_speed--; + } + + if (max_link_speed == 0) + break; + + /* Set new decreased max link speed */ + advk_pcie_setup_link_speed(pcie, max_link_speed); + + /* And start link training again */ + reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); + reg |= PCIE_CORE_LINK_TRAINING; + advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); + } while (1); reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | From patchwork Wed Apr 15 16:03:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271283 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=Oa/43f04; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RxN5cdtz9sTK for ; Thu, 16 Apr 2020 02:04:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410158AbgDOQEE (ORCPT ); Wed, 15 Apr 2020 12:04:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:56712 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410149AbgDOQEB (ORCPT ); Wed, 15 Apr 2020 12:04:01 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5226D21569; Wed, 15 Apr 2020 16:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966641; bh=1YUfEX82K+60B/zqLyakfZdfKZRyfg4LKtcOqbCXQzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Oa/43f04xATTEKSed4AMeN63fKk4K3aKweuLUoPUwwjQkSTtSVG7VuVXkJHNZSeAs pYfOo6c/V3czlZsEwhc72gYlkVG5Hbr46KQot3RqHzKfm6bRPIgCIWobAcdI59aUzV LQZKo/WMZLMRG0/g7B43HU4habRvHXSmk8nI4bVI= Received: by pali.im (Postfix) id 85BD258E; Wed, 15 Apr 2020 18:03:59 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 6/8] PCI: aardvark: Add support for issuing PERST via GPIO Date: Wed, 15 Apr 2020 18:03:46 +0200 Message-Id: <20200415160348.1146-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org bindings/pci/pci.txt defines standard DT property reset-gpios for specifying PERST GPIO. Read this property from Device Tree via devm_gpiod_get_from_of_node() function. As this property is optional, function may return -ENOENT. During initialization of aardvark PCI controller toggle supplied GPIO to issue PERST. Some Compex ath10k cards (e.g. WLE900VX or WLE1216) are not detected after reboot when PERST is not issued during driver initialization. And Compex WLE1216 cards need to be in reset state for at least 1ms otherwise they are not detected too. Tested on Turris MOX and after this change Compex cards are detected also after rebooting board. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 30 ++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index a83bbc86e428..6a97a3838098 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include "../pci.h" @@ -203,6 +205,7 @@ struct advk_pcie { u16 msi_msg; int root_bus_nr; struct pci_bridge_emul bridge; + struct gpio_desc *reset_gpio; }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) @@ -280,6 +283,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) int max_link_speed, neg_link_speed; u32 reg; + if (pcie->reset_gpio) { + dev_info(dev, "issuing PERST via reset GPIO for 1ms\n"); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + /* Detection of some Compex WLE1216 cards needs at least 1ms */ + mdelay(1); + gpiod_set_value_cansleep(pcie->reset_gpio, 0); + } + /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); @@ -358,7 +369,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* * PERST# signal could have been asserted by pinctrl subsystem before - * probe() callback has been called, making the endpoint going into + * probe() callback has been called or issued explicitly by reset gpio + * routine at beginning of this function, making the endpoint going into * fundamental reset. As required by PCI Express spec a delay for at * least 100ms after such a reset before link training is needed. */ @@ -1043,6 +1055,22 @@ static int advk_pcie_probe(struct platform_device *pdev) } pcie->root_bus_nr = bus->start; + /* Returns -ENOENT if reset-gpios property is not populated */ + pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, + "reset-gpios", 0, + GPIOD_OUT_LOW, + "pcie1-reset"); + if (IS_ERR(pcie->reset_gpio)) { + if (PTR_ERR(pcie->reset_gpio) == -ENOENT) { + pcie->reset_gpio = NULL; + } else { + if (PTR_ERR(pcie->reset_gpio) != -EPROBE_DEFER) + dev_err(dev, "Failed to retrieve reset GPIO (%ld)\n", + PTR_ERR(pcie->reset_gpio)); + return PTR_ERR(pcie->reset_gpio); + } + } + advk_pcie_setup_hw(pcie); advk_sw_pci_bridge_init(pcie); From patchwork Wed Apr 15 16:03:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=2Mfp0Dqs; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RxY6Yqbz9sTR for ; Thu, 16 Apr 2020 02:04:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410162AbgDOQEF (ORCPT ); Wed, 15 Apr 2020 12:04:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:56760 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410156AbgDOQED (ORCPT ); Wed, 15 Apr 2020 12:04:03 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 69D052168B; Wed, 15 Apr 2020 16:04:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966643; bh=rKE2/SNooMgmHtR2VsNRzQH+yzWux+/fvjH+XskA6QQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2Mfp0DqsTp7bB3i6hNSeX4j/pQrPGx7wb7QpBZpIuLStNEFqquwdbDr0pFE/ZFYmF JTQR+JC4ZD7f0k4POGwbDcfQcw/7T3r2FwOq42P9sa0ODFcE7jTrcM5TsuRGpZ3uf6 DoU69uPWYzbDft8cDwb8Pl7gHOhTOXM7l0KME+PM= Received: by pali.im (Postfix) id 8CD529CC; Wed, 15 Apr 2020 18:04:01 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 7/8] dts: aardvark: Route pcie reset pin to gpio function and define reset-gpios for pcie Date: Wed, 15 Apr 2020 18:03:47 +0200 Message-Id: <20200415160348.1146-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Marvell version of u-boot for Espressobin set pcie reset pin to gpio and toggle it when initializing u-boot aardvark driver. To not depend on bootloader version and state of Espressobin HW, route pcie reset pin to gpio function and define reset-gpios also in kernel. So pcie aardvark driver can trigger needed reset. Turris MOX dts file has already defined reset-gpios and configured pcie reset pin to gpio function, so unify Espressobin and Turris MOX dts files. Signed-off-by: Pali Rohár --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 4 ---- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 6705618162d5..8ad4dce280c3 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -48,6 +48,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; max-link-speed = <2>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; }; /* J6 */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index bb42d1e6a4e9..e496bd9d4737 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -128,10 +128,6 @@ }; }; -&pcie_reset_pins { - function = "gpio"; -}; - &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 000c135e39b7..7909c146eabf 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -317,7 +317,7 @@ pcie_reset_pins: pcie-reset-pins { groups = "pcie1"; - function = "pcie"; + function = "gpio"; }; pcie_clkreq_pins: pcie-clkreq-pins { From patchwork Wed Apr 15 16:03:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1271284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=N1KgN+4E; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 492RxX1kvRz9sT4 for ; Thu, 16 Apr 2020 02:04:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2410169AbgDOQEI (ORCPT ); Wed, 15 Apr 2020 12:04:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:56888 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2410164AbgDOQEG (ORCPT ); Wed, 15 Apr 2020 12:04:06 -0400 Received: from pali.im (pali.im [31.31.79.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C27002173E; Wed, 15 Apr 2020 16:04:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1586966645; bh=p7e0pThC4DsKXXmaYA9VV5ZorubQAuCZ2UJ40gakewI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N1KgN+4EjmVKgix5IBD5HuBai7EefSQYT5d8GTAOzdnnzEyvj/BCHZTzxDSTv9kme sDEmgZ2Arfex/TcUdHtGyOlrXYZNwvznynmNc75d4SfyIa99ZJDJbAxPZkwjN6vnvs amxhEUpAsg+jW83CGCh9vFZvREjPgTGyd7mnlK/U= Received: by pali.im (Postfix) id EA64758E; Wed, 15 Apr 2020 18:04:03 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Thomas Petazzoni , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Remi Pommarel , =?utf-8?q?Marek_Beh=C3=BAn?= , Tomasz Maciej Nowak , Xogium Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 8/8] PCI: aardvark: Add FIXME for code which access PCIE_CORE_CMD_STATUS_REG Date: Wed, 15 Apr 2020 18:03:48 +0200 Message-Id: <20200415160348.1146-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200415160054.951-1-pali@kernel.org> References: <20200415160054.951-1-pali@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Register PCIE_CORE_CMD_STATUS_REG is applicable only when aardvark controller is configured for Endpoint mode. Which is not the case of current kernel driver. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-aardvark.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 6a97a3838098..a1cebc734f2d 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -423,6 +423,12 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); } while (1); + /* + * FIXME: Following code which access PCIE_CORE_CMD_STATUS_REG register + * is suspicious. This register is applicable only when the PCI + * controller is configured for Endpoint mode. And not when it + * is configured for Root Complex. + */ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | PCIE_CORE_CMD_IO_ACCESS_EN |