From patchwork Thu Apr 2 11:13:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1265529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48tL8D6Vv5z9sQt for ; Thu, 2 Apr 2020 22:15:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mPvQEB+z; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48tL8D4cTGzDr41 for ; Thu, 2 Apr 2020 22:15:24 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mPvQEB+z; dkim-atps=neutral Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48tL6w5lwBzDrP8 for ; Thu, 2 Apr 2020 22:14:14 +1100 (AEDT) Received: by mail-pg1-x541.google.com with SMTP id b1so1689093pgm.8 for ; Thu, 02 Apr 2020 04:14:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rV1GfEk4e330KjqtzDc/lBSjkyBiW+kRvMfoUalXgPg=; b=mPvQEB+zxJWtNpWNkn0gyXrywj7o1ZCro6f5rpjQ+GLoKD7bEmu1AfCP61vZK5DT0b fbOq7Uuvxwkct0MBLBOFNLxiDojr2E+axTZXrqiDeDDbMOFCliCF7PzNnlcE/VPkf+Xm 1rLqRn7voRbHroCrib9QfCrRapLP1j/246l2Lqh9W9AHzrG5wg7vA8gH4K6dTGxeWFh7 tO0LT9IZTp8ox3W9sw9md56A8MZaIcNezrLEpeOrsb7qFBhRKfFfX27+GgcIgTxdFEsJ ECgUItMX78bMhJWhiicqeTfrJ6CaXurQfLXl4pMgtzSbgOaCoKYXMWQpuWqEkKG8f9aV 9ZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rV1GfEk4e330KjqtzDc/lBSjkyBiW+kRvMfoUalXgPg=; b=KiXHRw0C4o5jm6En5vt3+ywS3zPnr92s7cbWG5JOu3HEYpEYzTyfCNXLsyKpcBdape +X6BhNbHBpLBJzVN/vczluvxVG69zHEhaVmsON+tQ8IFGwDMIIv6bFJz63K3CU8mR96V 5CX9scvKkgGCbEy9bsw3YPSvaGUZPCL2ixW/vfmT18CPs1AYWR0STPaN5fENvLcbAjKe cfxyltljb5D9Yu/SWCIa4pu6Vlgnq5aHqMqFYW9U/D50xkASkQMkFwK8oo3EWoFZtWCp RvwUJ0RC5JDcuj6WoLJn0q8PFNRgSM1TSicoKrAedCFbYV+4yXq8o28QFG2P5dgN8CzR fbsw== X-Gm-Message-State: AGi0PuaDuItwDZDMqTNQMdDWF5dbyIj74OLVD88ZrZEQ/PzOrmS1ppbO QrmD5mJFFdmrR2rHXRZm2ZyJoGRwCKg= X-Google-Smtp-Source: APiQypKn1IBN+02/RLC9AB590iCYRIq9d0HR2Lx4ZflD1Z0PzRqfYBvIOgcXYTe+OEYN0Wonp3diPg== X-Received: by 2002:aa7:83c5:: with SMTP id j5mr2718520pfn.100.1585826048691; Thu, 02 Apr 2020 04:14:08 -0700 (PDT) Received: from 192-168-1-12.tpgi.com.au ([193.119.57.62]) by smtp.gmail.com with ESMTPSA id x70sm3239688pgd.37.2020.04.02.04.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 04:14:08 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 2 Apr 2020 22:13:53 +1100 Message-Id: <20200402111356.1413-1-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 Subject: [Skiboot] [PATCH 1/4] hw/xscom: Add scom infrastructure X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently the top nibble of the "part ID" is used to determine the type of a xscom_read() / xscom_write() call. This was mainly done for the benefit of PRD on P8 which would do "targeted" SCOMs to EX (core) chiplets and rely on skiboot to do find the actual scom address. Similarly, PRD also relied on this to access the SCOMs of centaur chips which are accessed via FSI on P8. On P9 PRD moved to only doing non-targeted scoms where it would only ever supply a "part ID" which was the fabric ID of the chip to be SCOMed. The centaur support was also unnecessary since OPAL didn't support any P9 systems with Centaurs. However, on future systems we will have to support memory buffer chips again so we need to expand the SCOM support to accomodate them. To do this, allow skiboot components to register a SCOM read and write() function for chip ID. This will allow us to ensure the P8 EX chiplet and Centaur SCOM code is only ever used on P8, freeing up the Part ID address space for other uses. Signed-off-by: Oliver O'Halloran --- hw/xscom.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++ include/xscom.h | 12 ++++++++ 2 files changed, 87 insertions(+) diff --git a/hw/xscom.c b/hw/xscom.c index 88e22da76424..32c813e572a6 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -580,11 +580,75 @@ void _xscom_unlock(void) unlock(&xscom_lock); } +/* sorted by the scom controller's partid */ +static LIST_HEAD(scom_list); + +int64_t scom_register(struct scom_controller *new) +{ + struct scom_controller *cur; + + list_for_each(&scom_list, cur, link) { + if (cur->part_id == new->part_id) { + prerror("Attempted to add duplicate scom, partid %x\n", + new->part_id); + return OPAL_BUSY; + } + + if (cur->part_id > new->part_id) { + list_add_before(&scom_list, &new->link, &cur->link); + return 0; + } + } + + /* if we never find a larger partid then this is the largest */ + list_add_tail(&scom_list, &new->link); + + return 0; +} + +static struct scom_controller *scom_find(uint32_t partid) +{ + struct scom_controller *cur; + + list_for_each(&scom_list, cur, link) + if (partid == cur->part_id) + return cur; + + return NULL; +} + +static int64_t scom_read(struct scom_controller *scom, uint32_t partid, + uint64_t pcbaddr, uint64_t *val) +{ + int64_t rc = scom->read(scom, partid, pcbaddr, val); + + if (rc) { + prerror("%s: to %x off: %llx rc = %lld\n", + __func__, partid, pcbaddr, rc); + } + + return rc; +} + +static int64_t scom_write(struct scom_controller *scom, uint32_t partid, + uint64_t pcbaddr, uint64_t val) +{ + int64_t rc = scom->write(scom, partid, pcbaddr, val); + + if (rc) { + prerror("%s: to %x off: %llx rc = %lld\n", + __func__, partid, pcbaddr, rc); + } + + return rc; +} + /* * External API */ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_lock) { + struct scom_controller *scom; uint32_t gcid; int rc; @@ -611,6 +675,11 @@ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_loc return OPAL_UNSUPPORTED; break; default: + /* is it one of our hacks? */ + scom = scom_find(partid); + if (scom) + return scom_read(scom, partid, pcb_addr, val); + /** * @fwts-label XSCOMReadInvalidPartID * @fwts-advice xscom_read was called with an invalid partid. @@ -652,6 +721,7 @@ opal_call(OPAL_XSCOM_READ, opal_xscom_read, 3); int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_lock) { + struct scom_controller *scom; uint32_t gcid; int rc; @@ -666,6 +736,11 @@ int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_loc gcid = xscom_decode_chiplet(partid, &pcb_addr); break; default: + /* is it one of our hacks? */ + scom = scom_find(partid); + if (scom) + return scom_write(scom, partid, pcb_addr, val); + /** * @fwts-label XSCOMWriteInvalidPartID * @fwts-advice xscom_write was called with an invalid partid. diff --git a/include/xscom.h b/include/xscom.h index 110aa8d62981..bd8bb89ac2ab 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -197,4 +197,16 @@ extern bool xscom_ok(void); extern int64_t xscom_read_cfam_chipid(uint32_t partid, uint32_t *chip_id); extern int64_t xscom_trigger_xstop(void); + +struct scom_controller { + uint32_t part_id; + void *private; + int64_t (*read)(struct scom_controller *, uint32_t chip, uint64_t reg, uint64_t *val); + int64_t (*write)(struct scom_controller *, uint32_t chip, uint64_t reg, uint64_t val); + + struct list_node link; +}; + +int64_t scom_register(struct scom_controller *new); + #endif /* __XSCOM_H */ From patchwork Thu Apr 2 11:13:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1265527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48tL7841R3z9sQt for ; Thu, 2 Apr 2020 22:14:28 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Thu, 02 Apr 2020 04:14:10 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 2 Apr 2020 22:13:54 +1100 Message-Id: <20200402111356.1413-2-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200402111356.1413-1-oohall@gmail.com> References: <20200402111356.1413-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/4] hw/centaur: Convert to use the new scom API X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently we assume any xscom_read / write targeted at a chipid with 0x8 as the top four bits is intended to be a centaur SCOM. On non-P8 platforms there is no reason to assume this so covert it to use the new struct scom_controller infrastructure. Signed-off-by: Oliver O'Halloran --- hw/centaur.c | 18 ++++++++++++++---- hw/xscom.c | 4 ---- include/centaur.h | 4 ++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/centaur.c b/hw/centaur.c index c79dd7f279d5..e9ff4197f705 100644 --- a/hw/centaur.c +++ b/hw/centaur.c @@ -307,9 +307,11 @@ static int centaur_xscom_ind_write(struct centaur_chip *centaur, return rc; } -int64_t centaur_xscom_read(uint32_t id, uint64_t pcb_addr, uint64_t *val) +static int64_t centaur_xscom_read(struct scom_controller *scom, + uint32_t id __unused, uint64_t pcb_addr, + uint64_t *val) { - struct centaur_chip *centaur = get_centaur(id); + struct centaur_chip *centaur = scom->private; int64_t rc; if (!centaur) @@ -349,9 +351,11 @@ int64_t centaur_xscom_read(uint32_t id, uint64_t pcb_addr, uint64_t *val) return rc; } -int64_t centaur_xscom_write(uint32_t id, uint64_t pcb_addr, uint64_t val) +static int64_t centaur_xscom_write(struct scom_controller *scom, + uint32_t id __unused, uint64_t pcb_addr, + uint64_t val) { - struct centaur_chip *centaur = get_centaur(id); + struct centaur_chip *centaur = scom->private; int64_t rc; if (!centaur) @@ -463,6 +467,12 @@ static bool centaur_add(uint32_t part_id, uint32_t mchip, uint32_t meng, if (!centaur_check_id(centaur)) return false; + centaur->scom.part_id = part_id; + centaur->scom.private = centaur; + centaur->scom.read = centaur_xscom_read; + centaur->scom.write = centaur_xscom_write; + scom_register(¢aur->scom); + cent_log(PR_INFO, centaur, "Found DD%x.%x chip\n", centaur->ec_level >> 4, centaur->ec_level & 0xf); diff --git a/hw/xscom.c b/hw/xscom.c index 32c813e572a6..0eda567fccf3 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -667,8 +667,6 @@ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_loc case 0: /* Normal processor chip */ gcid = partid; break; - case 8: /* Centaur */ - return centaur_xscom_read(partid, pcb_addr, val); case 4: /* EX chiplet */ gcid = xscom_decode_chiplet(partid, &pcb_addr); if (pcb_addr == 0) @@ -730,8 +728,6 @@ int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_loc case 0: /* Normal processor chip */ gcid = partid; break; - case 8: /* Centaur */ - return centaur_xscom_write(partid, pcb_addr, val); case 4: /* EX chiplet */ gcid = xscom_decode_chiplet(partid, &pcb_addr); break; diff --git a/include/centaur.h b/include/centaur.h index 9089705e56f1..9845946bbeb9 100644 --- a/include/centaur.h +++ b/include/centaur.h @@ -22,6 +22,8 @@ struct centaur_chip { uint32_t error_count; struct lock lock; + struct scom_controller scom; + /* Used by hw/p8-i2c.c */ struct list_head i2cms; }; @@ -29,8 +31,6 @@ struct centaur_chip { extern int64_t centaur_disable_sensor_cache(uint32_t part_id); extern int64_t centaur_enable_sensor_cache(uint32_t part_id); -extern int64_t centaur_xscom_read(uint32_t id, uint64_t pcb_addr, uint64_t *val) __warn_unused_result; -extern int64_t centaur_xscom_write(uint32_t id, uint64_t pcb_addr, uint64_t val) __warn_unused_result; extern void centaur_init(void); extern struct centaur_chip *get_centaur(uint32_t part_id); From patchwork Thu Apr 2 11:13:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1265528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48tL7q6P4jz9sQt for ; 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Thu, 02 Apr 2020 04:14:13 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 2 Apr 2020 22:13:55 +1100 Message-Id: <20200402111356.1413-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200402111356.1413-1-oohall@gmail.com> References: <20200402111356.1413-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/4] hdata/memory: Add support for memory-buffer mmio X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" HDAT now allows associating a set of MMIO address ranges with an MSAREA. This is to allow for exporting the MMIO register space associated with a memory-buffer chip to the hypervisor so we can wire up access to that for PRD. The DT format is similar to the old centaur memory-buffer@ nodes that we had on P8 OpenPower systems. The biggest difference is that the HDAT format allows for multiple memory ranges on each "chip" and each of these ranges may have a different register size. Cc: Klaus Heinrich Kiwi Signed-off-by: Oliver O'Halloran --- hdata/memory.c | 139 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 125 insertions(+), 14 deletions(-) mode change 100644 => 100755 hdata/memory.c diff --git a/hdata/memory.c b/hdata/memory.c old mode 100644 new mode 100755 index 6d060f7f04cf..7ce92750278f --- a/hdata/memory.c +++ b/hdata/memory.c @@ -55,10 +55,17 @@ struct HDIF_ms_area_address_range { #define PHYS_ATTR_STATUS_NOT_SAVED 0x08 #define PHYS_ATTR_STATUS_MEM_INVALID 0xff +/* Memory Controller ID for Nimbus P9 systems */ #define MS_CONTROLLER_MCBIST_ID(id) GETFIELD(PPC_BITMASK32(0, 1), id) #define MS_CONTROLLER_MCS_ID(id) GETFIELD(PPC_BITMASK32(4, 7), id) #define MS_CONTROLLER_MCA_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) +/* Memory Controller ID for P9 AXONE systems */ +#define MS_CONTROLLER_MC_ID(id) GETFIELD(PPC_BITMASK32(0, 1), id) +#define MS_CONTROLLER_MI_ID(id) GETFIELD(PPC_BITMASK32(4, 7), id) +#define MS_CONTROLLER_MCC_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) +#define MS_CONTROLLER_OMI_ID(id) GETFIELD(PPC_BITMASK32(16, 31), id) + struct HDIF_ms_area_id { __be16 id; #define MS_PTYPE_RISER_CARD 0x8000 @@ -73,6 +80,20 @@ struct HDIF_ms_area_id { __be16 share_id; } __packed; + +// FIXME: it should be 9, current HDATs are broken +#define MSAREA_IDATA_MMIO_IDX 8 +struct HDIF_ms_area_ocmb_mmio { + __be64 range_start; + __be64 range_end; + __be32 controller_id; + __be32 proc_chip_id; + __be64 hbrt_id; +#define OCMB_SCOM_8BYTE_ACCESS PPC_BIT(0) +#define OCMB_SCOM_4BYTE_ACCESS PPC_BIT(1) + __be64 flags; +} __packed; + static void append_chip_id(struct dt_node *mem, u32 id) { struct dt_property *prop; @@ -366,7 +387,7 @@ static void vpd_parse_spd(struct dt_node *dimm, const char *spd, u32 size) dt_add_property_cells(dimm, "manufacturer-id", be16_to_cpu(*vendor)); } -static void add_mca_dimm_info(struct dt_node *mca, +static void add_dimm_info(struct dt_node *parent, const struct HDIF_common_hdr *msarea) { unsigned int i, size; @@ -394,11 +415,11 @@ static void add_mca_dimm_info(struct dt_node *mca, continue; /* Use Resource ID to add dimm node */ - dimm = dt_find_by_name_addr(mca, "dimm", + dimm = dt_find_by_name_addr(parent, "dimm", be16_to_cpu(fru_id->rsrc_id)); if (dimm) continue; - dimm= dt_new_addr(mca, "dimm", be16_to_cpu(fru_id->rsrc_id)); + dimm= dt_new_addr(parent, "dimm", be16_to_cpu(fru_id->rsrc_id)); assert(dimm); dt_add_property_cells(dimm, "reg", be16_to_cpu(fru_id->rsrc_id)); @@ -439,21 +460,13 @@ static inline void dt_add_mem_reg_property(struct dt_node *node, u64 addr) dt_add_property_cells(node, "reg", addr); } -static void add_memory_controller(const struct HDIF_common_hdr *msarea, +static void add_memory_controller_p9n(const struct HDIF_common_hdr *msarea, const struct HDIF_ms_area_address_range *arange) { - uint32_t chip_id, version; + uint32_t chip_id; uint32_t controller_id, mcbist_id, mcs_id, mca_id; struct dt_node *xscom, *mcbist, *mcs, *mca; - /* - * Memory hierarchy may change between processor version. Presently - * it's only creating memory hierarchy for P9 (Nimbus) and P9P (Axone). - */ - version = PVR_TYPE(mfspr(SPR_PVR)); - if (version != PVR_TYPE_P9 && version != PVR_TYPE_P9P) - return; - chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); controller_id = be32_to_cpu(arange->controller_id); xscom = find_xscom_for_chip(chip_id); @@ -489,7 +502,103 @@ static void add_memory_controller(const struct HDIF_common_hdr *msarea, dt_add_mem_reg_property(mca, mca_id); } - add_mca_dimm_info(mca, msarea); + add_dimm_info(mca, msarea); +} + +static void add_memory_buffer_mmio(const struct HDIF_common_hdr *msarea) +{ + const struct HDIF_ms_area_ocmb_mmio *mmio; + uint64_t min_addr = ~0ull, hbrt_id = 0; + const struct HDIF_array_hdr *array; + unsigned int i, count, ranges = 0; + struct dt_node *membuf; + uint64_t *reg, *flags; + + if (be32_to_cpu(msarea->version) < 0x50) { + prlog(PR_WARNING, "MS AREA: Inconsistent MSAREA version %x for P9P system", + be32_to_cpu(msarea->version)); + return; + } + + array = HDIF_get_iarray(msarea, MSAREA_IDATA_MMIO_IDX, &count); + if (!array || count <= 0) { + prerror("MS AREA: No OCMB MMIO array at MS Area %p\n", msarea); + return; + } + + reg = zalloc(count * 2 * sizeof(*reg)); + flags = zalloc(count * sizeof(*flags)); + + /* grab the hbrt id from the first range. */ + HDIF_iarray_for_each(array, i, mmio) { + hbrt_id = be64_to_cpu(mmio->hbrt_id); + break; + } + + prlog(PR_DEBUG, "Adding memory buffer MMIO ranges for %"PRIx64"\n", + hbrt_id); + + HDIF_iarray_for_each(array, i, mmio) { + uint64_t start, end; + + if (hbrt_id != be64_to_cpu(mmio->hbrt_id)) { + prerror("HBRT ID mismatch!\n"); + continue; + } + + start = cleanup_addr(be64_to_cpu(mmio->range_start)); + end = cleanup_addr(be64_to_cpu(mmio->range_end)); + if (start < min_addr) + min_addr = start; + + prlog(PR_DEBUG, " %"PRIx64" - [%016"PRIx64"-%016"PRIx64")\n", + hbrt_id, start, end); + + reg[2 * ranges ] = cpu_to_be64(start); + reg[2 * ranges + 1] = cpu_to_be64(end - start + 1); + flags[ranges] = mmio->flags; /* both are BE */ + ranges++; + } + + membuf = dt_find_by_name_addr(dt_root, "memory-buffer", min_addr); + if (membuf) { + prerror("attempted to duplicate %s\n", membuf->name); + goto out; + } + + membuf = dt_new_addr(dt_root, "memory-buffer", min_addr); + assert(membuf); + + dt_add_property_string(membuf, "compatible", "ibm,explorer"); + dt_add_property_cells(membuf, "ibm,chip-id", hbrt_id); + + /* + * FIXME: We should probably be sorting the address ranges based + * on the starting address. + */ + dt_add_property(membuf, "reg", reg, sizeof(*reg) * 2 * ranges); + dt_add_property(membuf, "flags", flags, sizeof(*flags) * ranges); + +out: + free(flags); + free(reg); +} + +static void add_memory_controller(const struct HDIF_common_hdr *msarea, + const struct HDIF_ms_area_address_range *arange) +{ + const uint32_t version = PVR_TYPE(mfspr(SPR_PVR)); + /* + * Memory hierarchy may change between processor version. Presently + * it's only creating memory hierarchy for P9 (Nimbus) and P9P (Axone). + */ + + if (version == PVR_TYPE_P9) + return add_memory_controller_p9n(msarea, arange); + else if (version == PVR_TYPE_P9P) + return; //return add_memory_controller_p9p(msarea, arange); + else + return; } static void get_msareas(struct dt_node *root, @@ -569,6 +678,8 @@ static void get_msareas(struct dt_node *root, /* Add RAM Area VPD */ vpd_add_ram_area(msarea); + add_memory_buffer_mmio(msarea); + /* This offset is from the arr, not the header! */ arange = (void *)arr + be32_to_cpu(arr->offset); for (j = 0; j < be32_to_cpu(arr->ecnt); j++) { From patchwork Thu Apr 2 11:13:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1265530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48tL8t20kjz9sQt for ; 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Thu, 02 Apr 2020 04:14:15 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 2 Apr 2020 22:13:56 +1100 Message-Id: <20200402111356.1413-4-oohall@gmail.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200402111356.1413-1-oohall@gmail.com> References: <20200402111356.1413-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 4/4] hw/ocmb: Add OCMB SCOM support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a driver for the SCOM ranges of the OCMB. Unlike most chips the OCMB has two different (three if you count OpenCAPI config space) register spaces and we need to ensure that the right access size is used on each. Additionally the SCOM interface is a bit non-standard in that a full physical address is passed as the SCOM address rather than a register number so we don't need to perform any address transformations, we just need to verify that the address falls into one of the nominated address ranges. Cc: Klaus Heinrich Kiwi Signed-off-by: Oliver O'Halloran --- core/init.c | 4 ++ hw/Makefile.inc | 1 + hw/ocmb.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++++ include/ocmb.h | 13 ++++ 4 files changed, 185 insertions(+) create mode 100644 hw/ocmb.c create mode 100644 include/ocmb.h diff --git a/core/init.c b/core/init.c index bff4e968aae5..595d087fa4f3 100644 --- a/core/init.c +++ b/core/init.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -1190,6 +1191,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Grab centaurs from device-tree if present (only on FSP-less) */ centaur_init(); + /* initialize ocmb scom-controller */ + ocmb_init(); + /* Initialize PSI (depends on probe_platform being called) */ psi_init(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index b708bdfe7630..a7f450cf7246 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -9,6 +9,7 @@ HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o +HW_OBJS += ocmb.o HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/ocmb.c b/hw/ocmb.c new file mode 100644 index 000000000000..19b15dd68095 --- /dev/null +++ b/hw/ocmb.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* + * Open Capi Memory Buffer chip + * + * Copyright 2020 IBM Corp. + */ + + +#define pr_fmt(fmt) "OCMB: " fmt + +#include +#include +#include +#include +#include +#include + +struct ocmb_range { + uint64_t start; + uint64_t end; + uint64_t flags; + + /* flags come from hdat */ +#define ACCESS_8B PPC_BIT(0) +#define ACCESS_4B PPC_BIT(1) +#define ACCESS_SIZE_MASK (ACCESS_8B | ACCESS_4B) +}; + +struct ocmb { + struct scom_controller scom; + int range_count; + struct ocmb_range ranges[]; +}; + +static const struct ocmb_range *find_range(const struct ocmb *o, uint64_t offset) +{ + int i; + + for (i = 0; i < o->range_count; i++) { + uint64_t start = o->ranges[i].start; + uint64_t end = o->ranges[i].end; + + if (offset >= start && offset <= end) + return &o->ranges[i]; + } + + return NULL; +} + +static int64_t ocmb_fake_scom_write(struct scom_controller *f, + uint32_t __unused chip_id, + uint64_t offset, uint64_t val) +{ + const struct ocmb *o = f->private; + const struct ocmb_range *r; + + r = find_range(o, offset); + if (!r) { + prerror("no matching address range!\n"); + return OPAL_XSCOM_ADDR_ERROR; + } + + switch (r->flags & ACCESS_SIZE_MASK) { + case ACCESS_8B: + if (offset & 0x7) + return OPAL_XSCOM_ADDR_ERROR; + out_be64((void *) offset, val); + break; + + case ACCESS_4B: + if (offset & 0x3) + return OPAL_XSCOM_ADDR_ERROR; + out_be32((void *) offset, val); + break; + default: + prerror("bad flags? %llx\n", r->flags); + return OPAL_XSCOM_ADDR_ERROR; + } + + return OPAL_SUCCESS; +} + +static int64_t ocmb_fake_scom_read(struct scom_controller *f, + uint32_t chip_id __unused, + uint64_t offset, uint64_t *val) +{ + const struct ocmb *o = f->private; + const struct ocmb_range *r = NULL; + + r = find_range(o, offset); + if (!r) { + prerror("no matching address range!\n"); + return OPAL_XSCOM_ADDR_ERROR; + } + + + switch (r->flags & ACCESS_SIZE_MASK) { + case ACCESS_8B: + if (offset & 0x7) + return OPAL_XSCOM_ADDR_ERROR; + *val = in_be64((void *) offset); + break; + + case ACCESS_4B: + if (offset & 0x3) + return OPAL_XSCOM_ADDR_ERROR; + *val = in_be32((void *) offset); + break; + default: + prerror("bad flags? %llx\n", r->flags); + return OPAL_XSCOM_ADDR_ERROR; + } + + return OPAL_SUCCESS; +} + +static bool ocmb_probe_one(struct dt_node *ocmb_node) +{ + uint64_t chip_id = dt_prop_get_u32(ocmb_node, "ibm,chip-id"); + const struct dt_property *flags; + int i = 0, num = 0; + struct ocmb *ocmb; + + num = dt_count_addresses(ocmb_node); + + ocmb = zalloc(sizeof(*ocmb) + sizeof(*ocmb->ranges) * num); + if (!ocmb) + return false; + + ocmb->scom.private = ocmb; + ocmb->scom.part_id = chip_id; + ocmb->scom.write = ocmb_fake_scom_write; + ocmb->scom.read = ocmb_fake_scom_read; + ocmb->range_count = num; + + flags = dt_require_property(ocmb_node, "flags", sizeof(u64) * num); + + for (i = 0; i < num; i++) { + uint64_t start, size; + + start = dt_get_address(ocmb_node, i, &size); + + ocmb->ranges[i].start = start; + ocmb->ranges[i].end = start + size - 1; + ocmb->ranges[i].flags = dt_property_get_u64(flags, i); + + prlog(PR_DEBUG, "Added range: %" PRIx64 " - [%llx - %llx]\n", + chip_id, start, start + size - 1); + } + + if (scom_register(&ocmb->scom)) + prerror("error registienr fake socm\n"); + + dt_add_property(ocmb_node, "scom-controller", NULL, 0); + + prerror("XXX: Added scom controller for %s\n", ocmb_node->name); + + return true; +} + +void ocmb_init(void) +{ + struct dt_node *dn; + + dt_for_each_compatible(dt_root, dn, "ibm,explorer") + ocmb_probe_one(dn); +} diff --git a/include/ocmb.h b/include/ocmb.h new file mode 100644 index 000000000000..e7531885d2a3 --- /dev/null +++ b/include/ocmb.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* + * Open Capi Memory Buffer chip + * + * Copyright 2020 IBM Corp. + */ + +#ifndef __OCMB_H +#define __OCMB_H + +extern void ocmb_init(void); + +#endif /* __OCMB_H */ \ No newline at end of file