From patchwork Thu Mar 26 06:48:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261821 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=WUHiihEU; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nwZb1NV8z9sSK for ; Thu, 26 Mar 2020 17:49:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726014AbgCZGt0 (ORCPT ); Thu, 26 Mar 2020 02:49:26 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:41305 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbgCZGtW (ORCPT ); Thu, 26 Mar 2020 02:49:22 -0400 Received: by mail-wr1-f67.google.com with SMTP id h9so6335450wrc.8 for ; Wed, 25 Mar 2020 23:49:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/dqPVl/H6tR+MiJPl05QKxIz0P0jfSZuaHPi1asTV90=; b=WUHiihEUH0lElsZ9NJHrJqQ421HHol3h7BqdPKEKB4XM8ztXYl9yb9D44b7U5zQKtE S7rLRKDtlmTJcFlhCcLPc7DoNWeXy7OWWlxbRROTuRdOZfXNyAyjQgHanlUbE6CVneDk dITLx4EJK9UHLBpBweL8IWT+qJbZIOPYFkSOA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/dqPVl/H6tR+MiJPl05QKxIz0P0jfSZuaHPi1asTV90=; b=WR4YBiiVy1Yf2IQwXUlNzbeOLgYeg1Ofbn+F84Tl39/l2+gdiox/KyHPNjG+VsXP1l sy5NUSw+aDMkeMsBfjGa7acKxlASaPZje0VV9Mg0gwuKMYfLck+Gzp+iS8hHmXU27IiA WvyULoUi01uL86uRUkJvLJnYVGOMOk0dAe+WVuSBqrGiRmUWPurkOs9Lf0kcXSv8fL0J 7ijFPCp/XgynR+7+iuCzw/VLXYCB0K0fUSorgBdgo92mFTk2LE7odJ9elpigTF1eKTyV bQPZind1FwGEuD/lnc1Whucr/so+n78ZH0JqSk170dKOjj1JoAniMZjp/gTzDKoSpDb+ El9Q== X-Gm-Message-State: ANhLgQ1Kkiewzx4LE2NwrN/P+mQ2tgW0Dl8efmca37ej0QYAOy7hXyHS 2Pxnfxwhz7Z5hSoCkieFPnUZ8g== X-Google-Smtp-Source: ADFU+vuaCkfq0b0wW8UmvZep91KWyv+2QNaLZlSlESaU3JAZep7YouX21pCUM8nvv5xBRVAzdtkeeg== X-Received: by 2002:adf:c64e:: with SMTP id u14mr6700306wrg.113.1585205360347; Wed, 25 Mar 2020 23:49:20 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:19 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 1/6] dt-bindings: pci: Update iProc PCI binding for INTx support Date: Thu, 26 Mar 2020 12:18:41 +0530 Message-Id: <1585205326-25326-2-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Update the iProc PCIe binding document for better modeling of the legacy interrupt (INTx) support. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 48 ++++++++++++++++++---- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index df065aa..d3f833a 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -13,9 +13,6 @@ controller, used in Stingray PAXB-based root complex is used for external endpoint devices. PAXC-based root complex is connected to emulated endpoint devices internal to the ASIC - reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers - linux,pci-domain: PCI domain ID. Should be unique for each host controller - bus-range: PCI bus numbers covered - #address-cells: set to <3> @@ -41,6 +38,21 @@ Required: - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal address used by the iProc PCIe core (not the PCIe address) +Legacy interrupt (INTx) support (optional): + +Note INTx is for PAXB only. +- interrupt-map-mask and interrupt-map, standard PCI properties to define +the mapping of the PCIe interface to interrupt numbers + +In addition, a sub-node that describes the legacy interrupt controller built +into the PCIe controller. +This sub-node must have the following properties: + - compatible: must be "brcm,iproc-intc" + - interrupt-controller: claims itself as an interrupt controller for INTx + - #interrupt-cells: set to <1> + - interrupts: interrupt line wired to the generic GIC for INTx support + - interrupt-parent: Phandle to the parent interrupt controller + MSI support (optional): For older platforms without MSI integrated in the GIC, iProc PCIe core provides @@ -77,8 +89,11 @@ Example: reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -98,6 +113,14 @@ Example: msi-parent = <&msi0>; + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + /* iProc event queue based MSI */ msi0: msi@18012000 { compatible = "brcm,iproc-msi"; @@ -115,8 +138,11 @@ Example: reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -130,4 +156,12 @@ Example: phys = <&phy 1 6>; phy-names = "pcie-phy"; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; From patchwork Thu Mar 26 06:48:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=NXMrBUAF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nwZc3CV9z9sSL for ; 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bh=fh/TLNefQmL1SjuEsz52lTohOhcfunUSRzYwviSzm/Y=; b=GrmqWHm37g4LopkkMG90UALXrNKNoghkzKoUzoF/fNrxbeGjmYMNsz5y5JHKXm3lpQ 0PQ0bqhSmTRqR4YncyG8N3vUf+jipNYK0VLE1+3fAiul+nQX7nrMMrW+lrKJhULwGbId vykBi6vXQForysVRq6IETiwlb4b5MMOnOfSQQVJ4nraDeBwc0LKh15CWNvhvzrOfSiE0 NqEp/b8Mm5mmId08WfGZf+Sfktct8zDJ0TbJIkog0TBDnqzd6hwlBwGgnscVQHaLn/4l c1eQ31b+JASNdRS7Lolgow0JBXUFRP4rf3oy29TzBfX2vSX6pyDJDtPKY0IM5+OTTomJ K1vQ== X-Gm-Message-State: ANhLgQ0rb5CrCQkkC8A3PkhxryFmeM6r9SdAN7na29lGG8btmm8SYekd 0c2Fqu914Lb7irM+UIkzzMMjtA== X-Google-Smtp-Source: ADFU+vvQ3rK47wJ0+nIAYV8ZUHsndQ8ahJHsCpAmdfrH86NngQd44OZSVGpJqx7/ULYofCL2OrXueg== X-Received: by 2002:adf:e611:: with SMTP id p17mr7444925wrm.212.1585205365864; Wed, 25 Mar 2020 23:49:25 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:25 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 2/6] PCI: iproc: Add INTx support with better modeling Date: Thu, 26 Mar 2020 12:18:42 +0530 Message-Id: <1585205326-25326-3-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Add PCIe legacy interrupt INTx support to the iProc PCIe driver by modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, INTD share the same interrupt line connected to the GIC in the system, while the status of each INTx can be obtained through the INTX CSR register. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam Reviewed-by: Andrew Murray --- drivers/pci/controller/pcie-iproc.c | 147 +++++++++++++++++++++++++++++++++++- drivers/pci/controller/pcie-iproc.h | 8 ++ 2 files changed, 153 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 0a468c7..62d8f43 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -270,6 +271,7 @@ enum iproc_pcie_reg { /* enable INTx */ IPROC_PCIE_INTX_EN, + IPROC_PCIE_INTX_CSR, /* outbound address mapping */ IPROC_PCIE_OARR0, @@ -314,6 +316,7 @@ static const u16 iproc_pcie_reg_paxb_bcma[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_LINK_STATUS] = 0xf0c, }; @@ -325,6 +328,7 @@ static const u16 iproc_pcie_reg_paxb[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -341,6 +345,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -846,9 +851,142 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) return link_is_active ? 0 : -ENODEV; } -static void iproc_pcie_enable(struct iproc_pcie *pcie) +static void iproc_pcie_mask_irq(struct irq_data *d) { + struct iproc_pcie *pcie = irq_data_get_irq_chip_data(d); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_EN); + val &= ~(BIT(irqd_to_hwirq(d))); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, val); + spin_unlock_irqrestore(&pcie->intx_lock, flags); +} + +static void iproc_pcie_unmask_irq(struct irq_data *d) +{ + struct iproc_pcie *pcie = irq_data_get_irq_chip_data(d); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_EN); + val |= (BIT(irqd_to_hwirq(d))); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, val); + spin_unlock_irqrestore(&pcie->intx_lock, flags); +} + +static struct irq_chip iproc_pcie_irq_chip = { + .name = "pcie-iproc-intc", + .irq_enable = iproc_pcie_unmask_irq, + .irq_disable = iproc_pcie_mask_irq, + .irq_mask = iproc_pcie_mask_irq, + .irq_unmask = iproc_pcie_unmask_irq, +}; + +static int iproc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &iproc_pcie_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = iproc_pcie_intx_map, +}; + +static void iproc_pcie_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct iproc_pcie *pcie; + struct device *dev; + unsigned long status; + u32 bit, virq; + + chained_irq_enter(chip, desc); + pcie = irq_desc_get_handler_data(desc); + dev = pcie->dev; + + /* go through INTx A, B, C, D until all interrupts are handled */ + do { + status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR); + for_each_set_bit(bit, &status, PCI_NUM_INTX) { + virq = irq_find_mapping(pcie->irq_domain, bit); + if (virq) + generic_handle_irq(virq); + else + dev_err(dev, "unexpected INTx%u\n", bit); + } + } while ((status & SYS_RC_INTX_MASK) != 0); + + chained_irq_exit(chip, desc); +} + +static int iproc_pcie_intx_enable(struct iproc_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node; + int ret; + + /* + * BCMA devices do not map INTx the same way as platform devices. All + * BCMA needs below line to enable INTx + */ iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); + + node = of_get_compatible_child(dev->of_node, "brcm,iproc-intc"); + if (node) + pcie->irq = of_irq_get(node, 0); + + if (!node || pcie->irq <= 0) + return 0; + + spin_lock_init(&pcie->intx_lock); + + /* set IRQ handler */ + irq_set_chained_handler_and_data(pcie->irq, iproc_pcie_isr, pcie); + + /* add IRQ domain for INTx */ + pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, + &intx_domain_ops, pcie); + if (!pcie->irq_domain) { + dev_err(dev, "failed to add INTx IRQ domain\n"); + ret = -ENOMEM; + goto err_rm_handler_data; + } + + return 0; + +err_rm_handler_data: + of_node_put(node); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + + return ret; +} + +static void iproc_pcie_intx_disable(struct iproc_pcie *pcie) +{ + uint32_t offset, virq; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, 0x0); + spin_unlock_irqrestore(&pcie->intx_lock, flags); + + if (pcie->irq <= 0) + return; + + for (offset = 0; offset < PCI_NUM_INTX; offset++) { + virq = irq_find_mapping(pcie->irq_domain, offset); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(pcie->irq_domain); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); } static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, @@ -1518,7 +1656,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_power_off_phy; } - iproc_pcie_enable(pcie); + ret = iproc_pcie_intx_enable(pcie); + if (ret) { + dev_err(dev, "failed to enable INTx\n"); + goto err_power_off_phy; + } if (IS_ENABLED(CONFIG_PCI_MSI)) if (iproc_pcie_msi_enable(pcie)) @@ -1562,6 +1704,7 @@ int iproc_pcie_remove(struct iproc_pcie *pcie) pci_remove_root_bus(pcie->root_bus); iproc_pcie_msi_disable(pcie); + iproc_pcie_intx_disable(pcie); phy_power_off(pcie->phy); phy_exit(pcie->phy); diff --git a/drivers/pci/controller/pcie-iproc.h b/drivers/pci/controller/pcie-iproc.h index 4f03ea5..787bfba 100644 --- a/drivers/pci/controller/pcie-iproc.h +++ b/drivers/pci/controller/pcie-iproc.h @@ -74,9 +74,13 @@ struct iproc_msi; * @ib: inbound mapping related parameters * @ib_map: outbound mapping region related parameters * + * @irq: interrupt line wired to the generic GIC for INTx + * @irq_domain: IRQ domain for INTx + * * @need_msi_steer: indicates additional configuration of the iProc PCIe * controller is required to steer MSI writes to external interrupt controller * @msi: MSI data + * @intx_lock: spinlock to protect access to INTx related registers */ struct iproc_pcie { struct device *dev; @@ -102,8 +106,12 @@ struct iproc_pcie { struct iproc_pcie_ib ib; const struct iproc_pcie_ib_map *ib_map; + int irq; + struct irq_domain *irq_domain; + bool need_msi_steer; struct iproc_msi *msi; + spinlock_t intx_lock; }; int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); From patchwork Thu Mar 26 06:48:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 25 Mar 2020 23:49:31 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:30 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 3/6] arm: dts: Change PCIe INTx mapping for Cygnus Date: Thu, 26 Mar 2020 12:18:43 +0530 Message-Id: <1585205326-25326-4-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-cygnus.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 2dac3ef..ca23e82 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -264,8 +264,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -292,6 +295,14 @@ , ; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -299,8 +310,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -327,6 +341,14 @@ , ; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; dma0: dma@18018000 { From patchwork Thu Mar 26 06:48:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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Wed, 25 Mar 2020 23:49:36 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:36 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 4/6] arm: dts: Change PCIe INTx mapping for NSP Date: Thu, 26 Mar 2020 12:18:44 +0530 Message-Id: <1585205326-25326-5-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-nsp.dtsi | 45 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index da6d70f..6d73221 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -529,8 +529,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -559,6 +562,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -566,8 +577,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -596,6 +610,14 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie2: pcie@18014000 { @@ -603,8 +625,11 @@ reg = <0x18014000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; linux,pci-domain = <2>; @@ -633,6 +658,14 @@ ; brcm,pcie-msi-inten; }; + + pcie2_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; thermal-zones { From patchwork Thu Mar 26 06:48:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261825 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=D8SvKWDd; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48nwZx66glz9sSK for ; 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Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-hr2.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 6142c67..80c3add 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -299,8 +299,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -328,6 +331,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -335,8 +346,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -364,5 +378,13 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; }; From patchwork Thu Mar 26 06:48:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 1261826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; 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Wed, 25 Mar 2020 23:49:47 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:47 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 6/6] arm64: dts: Change PCIe INTx mapping for NS2 Date: Thu, 26 Mar 2020 12:18:46 +0530 Message-Id: <1585205326-25326-7-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 28 ++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 15f7b0e..489bfd5 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -117,8 +117,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -140,6 +143,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie4: pcie@50020000 { @@ -148,8 +158,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; linux,pci-domain = <4>; @@ -171,6 +184,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie4_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie8: pcie@60c00000 {