From patchwork Mon Mar 23 14:38:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1260074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48mH7G1YrJz9sNg for ; Tue, 24 Mar 2020 01:38:33 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D98043944409; Mon, 23 Mar 2020 14:38:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 9D23D385E013 for ; Mon, 23 Mar 2020 14:38:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 9D23D385E013 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andre.simoesdiasvieira@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51DE21FB; Mon, 23 Mar 2020 07:38:27 -0700 (PDT) Received: from [10.57.19.63] (unknown [10.57.19.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BA37D3F52E; Mon, 23 Mar 2020 07:38:26 -0700 (PDT) Subject: [PATCH 1/2] arm: Add earlyclobber to MVE instructions that require it To: gcc-patches@gcc.gnu.org References: From: "Andre Vieira (lists)" Message-ID: <667b0fb7-9441-7cb7-cac1-ba612a16b40b@arm.com> Date: Mon, 23 Mar 2020 14:38:25 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Spam-Status: No, score=-27.6 required=5.0 tests=BAYES_00, BODY_8BITS, GARBLED_BODY, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch adds an earlyclobber to the MVE instructions that require it and were missing it. These are vrev64 and 32-bit element variants of vcadd, vhcadd vcmul, vmull[bt] and vqdmull[bt]. Regression tested on arm-none-eabi. Is this OK for trunk? Cheers, Andre 2020-03-23  Andre Vieira          * config/arm/mve.md (earlyclobber_32): New mode attribute.         (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,          mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 2e28d9d8408127dd52b9d16c772e7f27a47d390a..0cd67962a2641a3be46fe67819e093c0a712751b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -411,6 +411,8 @@ (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")]) (define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")]) (define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h") (V4SF "w")]) +(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w") + (V8HF "=w") (V4SF "=&w")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -856,7 +858,7 @@ (define_insn "mve_vrndaq_f" ;; (define_insn "mve_vrev64q_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "=&w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] VREV64Q_F)) ] @@ -967,7 +969,7 @@ (define_insn "mve_vcvtq_to_f_" ;; (define_insn "mve_vrev64q_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "=&w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] VREV64Q)) ] @@ -1541,7 +1543,7 @@ (define_insn "mve_vbrsrq_n_" ;; (define_insn "mve_vcaddq_rot270_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VCADDQ_ROT270)) @@ -1556,7 +1558,7 @@ (define_insn "mve_vcaddq_rot270_" ;; (define_insn "mve_vcaddq_rot90_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VCADDQ_ROT90)) @@ -1841,7 +1843,7 @@ (define_insn "mve_vhaddq_" ;; (define_insn "mve_vhcaddq_rot270_s" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VHCADDQ_ROT270_S)) @@ -1856,7 +1858,7 @@ (define_insn "mve_vhcaddq_rot270_s" ;; (define_insn "mve_vhcaddq_rot90_s" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VHCADDQ_ROT90_S)) @@ -2096,7 +2098,7 @@ (define_insn "mve_vmulhq_" ;; (define_insn "mve_vmullbq_int_" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VMULLBQ_INT)) @@ -2111,7 +2113,7 @@ (define_insn "mve_vmullbq_int_" ;; (define_insn "mve_vmulltq_int_" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] VMULLTQ_INT)) @@ -2621,7 +2623,7 @@ (define_insn "mve_vbicq_n_" ;; (define_insn "mve_vcaddq_rot270_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCADDQ_ROT270_F)) @@ -2636,7 +2638,7 @@ (define_insn "mve_vcaddq_rot270_f" ;; (define_insn "mve_vcaddq_rot90_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCADDQ_ROT90_F)) @@ -2831,7 +2833,7 @@ (define_insn "mve_vcmpneq_n_f" ;; (define_insn "mve_vcmulq_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCMULQ_F)) @@ -2846,7 +2848,7 @@ (define_insn "mve_vcmulq_f" ;; (define_insn "mve_vcmulq_rot180_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCMULQ_ROT180_F)) @@ -2861,7 +2863,7 @@ (define_insn "mve_vcmulq_rot180_f" ;; (define_insn "mve_vcmulq_rot270_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCMULQ_ROT270_F)) @@ -2876,7 +2878,7 @@ (define_insn "mve_vcmulq_rot270_f" ;; (define_insn "mve_vcmulq_rot90_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] VCMULQ_ROT90_F)) @@ -3236,7 +3238,7 @@ (define_insn "mve_vorrq_n_" ;; (define_insn "mve_vqdmullbq_n_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r")] VQDMULLBQ_N_S)) @@ -3251,7 +3253,7 @@ (define_insn "mve_vqdmullbq_n_s" ;; (define_insn "mve_vqdmullbq_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w")] VQDMULLBQ_S)) @@ -3266,7 +3268,7 @@ (define_insn "mve_vqdmullbq_s" ;; (define_insn "mve_vqdmulltq_n_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand: 2 "s_register_operand" "r")] VQDMULLTQ_N_S)) @@ -3281,7 +3283,7 @@ (define_insn "mve_vqdmulltq_n_s" ;; (define_insn "mve_vqdmulltq_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand:MVE_5 1 "s_register_operand" "w") (match_operand:MVE_5 2 "s_register_operand" "w")] VQDMULLTQ_S)) @@ -6134,7 +6136,7 @@ (define_insn "mve_vbrsrq_m_n_" ;; (define_insn "mve_vcaddq_rot270_m_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -6151,7 +6153,7 @@ (define_insn "mve_vcaddq_rot270_m_" ;; (define_insn "mve_vcaddq_rot90_m_" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -6355,7 +6357,7 @@ (define_insn "mve_vmulhq_m_" ;; (define_insn "mve_vmullbq_int_m_" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -6372,7 +6374,7 @@ (define_insn "mve_vmullbq_int_m_" ;; (define_insn "mve_vmulltq_int_m_" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -6763,7 +6765,7 @@ (define_insn "mve_vsubq_m_n_" ;; (define_insn "mve_vhcaddq_rot270_m_s" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -6780,7 +6782,7 @@ (define_insn "mve_vhcaddq_rot270_m_s" ;; (define_insn "mve_vhcaddq_rot90_m_s" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:MVE_2 3 "s_register_operand" "w") @@ -7341,7 +7343,7 @@ (define_insn "mve_vmulltq_poly_m_p" ;; (define_insn "mve_vqdmullbq_m_n_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "s_register_operand" "r") @@ -7358,7 +7360,7 @@ (define_insn "mve_vqdmullbq_m_n_s" ;; (define_insn "mve_vqdmullbq_m_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") @@ -7375,7 +7377,7 @@ (define_insn "mve_vqdmullbq_m_s" ;; (define_insn "mve_vqdmulltq_m_n_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand: 3 "s_register_operand" "r") @@ -7392,7 +7394,7 @@ (define_insn "mve_vqdmulltq_m_n_s" ;; (define_insn "mve_vqdmulltq_m_s" [ - (set (match_operand: 0 "s_register_operand" "=w") + (set (match_operand: 0 "s_register_operand" "") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") (match_operand:MVE_5 3 "s_register_operand" "w") @@ -7646,7 +7648,7 @@ (define_insn "mve_vbrsrq_m_n_f" ;; (define_insn "mve_vcaddq_rot270_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") @@ -7663,7 +7665,7 @@ (define_insn "mve_vcaddq_rot270_m_f" ;; (define_insn "mve_vcaddq_rot90_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") @@ -7748,7 +7750,7 @@ (define_insn "mve_vcmlaq_rot90_m_f" ;; (define_insn "mve_vcmulq_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") @@ -7765,7 +7767,7 @@ (define_insn "mve_vcmulq_m_f" ;; (define_insn "mve_vcmulq_rot180_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") @@ -7782,7 +7784,7 @@ (define_insn "mve_vcmulq_rot180_m_f" ;; (define_insn "mve_vcmulq_rot270_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") @@ -7799,7 +7801,7 @@ (define_insn "mve_vcmulq_rot270_m_f" ;; (define_insn "mve_vcmulq_rot90_m_f" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w")