From patchwork Wed Mar 18 13:00:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1257481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48j9Bl2H5cz9sNg for ; Thu, 19 Mar 2020 00:00:45 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD8B23945C04; Wed, 18 Mar 2020 13:00:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id 57BF73944416 for ; Wed, 18 Mar 2020 13:00:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 57BF73944416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Andrew_Stubbs@mentor.com IronPort-SDR: xRqkCciOyofRJXI/xH42RIFDj+qhv+C6Xy+aN13iOrpCFFP53UF9+UwGxWHWSeUwBX9nKXvaqY zfxcm4gNMtp9YYcwQ82jX0E9CaLVUQxVEIRY3pq8kj1/gxopRp0GnndSWtIcCyipfBP0gX9xdO ULgfS63VrWDVfjuMUSmnJ1GbsJBW0sUIJ7MMbY1rXmQyW1Kx8p/eYL9fqb9PHiaRz8TCjghy8M Gbhy2hfKVYNzneUNjYaaOGXzYiMNWMmRGXTeddzvPMney289xavU0YX0ZmKCthbRxK3BYc7vdo /c0= X-IronPort-AV: E=Sophos;i="5.70,567,1574150400"; d="scan'208";a="46879343" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa4.mentor.iphmx.com with ESMTP; 18 Mar 2020 05:00:38 -0800 IronPort-SDR: 4/LU/GzfD+42rvAzRx6szsblqXBEBb/py5n1gztyVx5Tjcle6N+/ilNwnHAB7O7wlWclDXbW40 6oOq35Jdp8fB2tWWS8k8sWpwVEBvs0dQ6CxyMZx73hTq/Nb92kOODwDoBFdT5Q9ICPmTMA8Suj Lh+4AdostFJVEaDqsUQNYtjQC/0pflympexlVrj3XHyRcSYdTee2g9DGvv/zMpguzWrZt5WcSd MIabCe1etokFbdg+c7tIDncSbgQUguajctD2GrCt3vOYBt0HomNQgtXHDcmXEYT5z89kUFNsNm Waw= To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed] amdgcn: Add cond_add/sub/and/ior/xor for all vector modes Message-ID: Date: Wed, 18 Mar 2020 13:00:33 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 Content-Language: en-GB X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-08.mgc.mentorg.com (139.181.222.8) To SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) X-Spam-Status: No, score=-24.7 required=5.0 tests=GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This patch adds support for new conditional vector operators, including cond_mult, and more modes for cond_add, cond_sub, cond_and, cond_ior and cond_xor. This allows vectorization of more algorithms and several new test passes. The min and max operators remain on the to do list because those require extends and truncates for some modes. Andrew amdgcn: Add cond_add/sub/and/ior/xor for all vector modes 2020-03-18 Andrew Stubbs gcc/ * config/gcn/gcn-valu.md (COND_MODE): Delete. (COND_INT_MODE): Delete. (cond_op): Add "mult". (cond_): Use VEC_ALLREG_MODE. (cond_): Use VEC_ALLREG_INT_MODE. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index a8034f77798..68d89fadc9e 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2903,19 +2903,15 @@ DONE; }) -; FIXME this should be VEC_REG_MODE, but not all dependencies are implemented. -(define_mode_iterator COND_MODE [V64SI V64DI V64SF V64DF]) -(define_mode_iterator COND_INT_MODE [V64SI V64DI]) - -(define_code_iterator cond_op [plus minus]) +(define_code_iterator cond_op [plus minus mult]) (define_expand "cond_" - [(match_operand:COND_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_op:COND_MODE - (match_operand:COND_MODE 2 "gcn_alu_operand") - (match_operand:COND_MODE 3 "gcn_alu_operand")) - (match_operand:COND_MODE 4 "register_operand")] + (cond_op:VEC_ALLREG_MODE + (match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]); @@ -2927,15 +2923,16 @@ DONE; }) +;; TODO smin umin smax umax (define_code_iterator cond_bitop [and ior xor]) (define_expand "cond_" - [(match_operand:COND_INT_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_INT_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_bitop:COND_INT_MODE - (match_operand:COND_INT_MODE 2 "gcn_alu_operand") - (match_operand:COND_INT_MODE 3 "gcn_alu_operand")) - (match_operand:COND_INT_MODE 4 "register_operand")] + (cond_bitop:VEC_ALLREG_INT_MODE + (match_operand:VEC_ALLREG_INT_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_INT_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_INT_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]);