From patchwork Fri Mar 13 09:10:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 1254307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=adacore.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48f0KV5S1Xz9sRN for ; Fri, 13 Mar 2020 20:10:36 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DBB023945C19; Fri, 13 Mar 2020 09:10:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp.eu.adacore.com (mel.act-europe.fr [IPv6:2a02:2ab8:224:1::a0a:d2]) by sourceware.org (Postfix) with ESMTPS id 2AB77393742C for ; Fri, 13 Mar 2020 09:10:30 +0000 (GMT) Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 1A5108138E for ; Fri, 13 Mar 2020 10:10:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cfMd5IhLBbZ1 for ; Fri, 13 Mar 2020 10:10:29 +0100 (CET) Received: from polaris.localnet (unknown [IPv6:2a01:e0a:41b:9230:1a03:73ff:fe45:373a]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id E74FA81385 for ; Fri, 13 Mar 2020 10:10:28 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [patch] Fix PR rtl-optimization/94119 Date: Fri, 13 Mar 2020 10:10:27 +0100 Message-ID: <3073123.yoXOXRUpF6@polaris> MIME-Version: 1.0 X-Spam-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This is a regression present on all active branches: the dbr pass goes awry on a branchy testcase compiled at -O2 for the MIPS, with specific set of options (-fno-reorder-blocks -mlong-calls) which leave the CFG in a convoluted state. The underlynig issue is that relax_delay_slots can streamline the CFG in these cases, in particular remove BARRIERs, but removing BARRIERs changes the way the instructions are associated with (basic) blocks by the liveness analysis code in resource.c (find_basic_block) and thus can cause entries in the cache maintained by resource.c to become outdated, thus producing wrong answers. The fix is to invalidate the cache entries affected by the removal of BARRIERs in relax_delay_slots, i.e. for the instructions down to the next BARRIER. Bootstrapped/regtested on SPAR/Solaris & SPARC64/Linux, applied on all active branches (without a testcase because it's MIPS specific and I don't understand hows gcc.target/mips works, see mips.exp for the gory details). 2019-03-13 Eric Botcazou PR rtl-optimization/94119 * resource.h (clear_hashed_info_until_next_barrier): Declare. * resource.c (clear_hashed_info_until_next_barrier): New function. * reorg.c (add_to_delay_list): Fix formatting. (relax_delay_slots): Call clear_hashed_info_until_next_barrier on the next instruction after removing a BARRIER. diff --git a/gcc/reorg.c b/gcc/reorg.c index dfd7494bf79..84beb9395aa 100644 --- a/gcc/reorg.c +++ b/gcc/reorg.c @@ -575,8 +575,9 @@ add_to_delay_list (rtx_insn *insn, vec *delay_list) { /* If INSN has its block number recorded, clear it since we may be moving the insn to a new block. */ - clear_hashed_info_for_insn (insn); - delay_list->safe_push (insn); + clear_hashed_info_for_insn (insn); + + delay_list->safe_push (insn); } /* Delete INSN from the delay slot of the insn that it is in, which may @@ -3211,7 +3212,14 @@ relax_delay_slots (rtx_insn *first) if (invert_jump (jump_insn, label, 1)) { - delete_related_insns (next); + rtx_insn *from = delete_related_insns (next); + + /* We have just removed a BARRIER, which means that the block + number of the next insns has effectively been changed (see + find_basic_block in resource.c), so clear it. */ + if (from) + clear_hashed_info_until_next_barrier (from); + next = jump_insn; } @@ -3484,18 +3492,22 @@ relax_delay_slots (rtx_insn *first) if (invert_jump (delay_jump_insn, label, 1)) { - int i; - /* Must update the INSN_FROM_TARGET_P bits now that the branch is reversed, so that mark_target_live_regs will handle the delay slot insn correctly. */ - for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) + for (int i = 1; i < XVECLEN (PATTERN (insn), 0); i++) { rtx slot = XVECEXP (PATTERN (insn), 0, i); INSN_FROM_TARGET_P (slot) = ! INSN_FROM_TARGET_P (slot); } - delete_related_insns (next); + /* We have just removed a BARRIER, which means that the block + number of the next insns has effectively been changed (see + find_basic_block in resource.c), so clear it. */ + rtx_insn *from = delete_related_insns (next); + if (from) + clear_hashed_info_until_next_barrier (from); + next = insn; } diff --git a/gcc/resource.c b/gcc/resource.c index d26217c056b..5ce53e61057 100644 --- a/gcc/resource.c +++ b/gcc/resource.c @@ -1283,6 +1283,25 @@ clear_hashed_info_for_insn (rtx_insn *insn) } } +/* Clear any hashed information that we have stored for instructions + between INSN and the next BARRIER that follow a JUMP or a LABEL. */ + +void +clear_hashed_info_until_next_barrier (rtx_insn *insn) +{ + while (insn && !BARRIER_P (insn)) + { + if (JUMP_P (insn) || LABEL_P (insn)) + { + rtx_insn *next = next_active_insn (insn); + if (next) + clear_hashed_info_for_insn (next); + } + + insn = next_nonnote_insn (insn); + } +} + /* Increment the tick count for the basic block that contains INSN. */ void diff --git a/gcc/resource.h b/gcc/resource.h index e3edb242703..c4f8aa20141 100644 --- a/gcc/resource.h +++ b/gcc/resource.h @@ -46,6 +46,7 @@ extern void mark_set_resources (rtx, struct resources *, int, enum mark_resource_type); extern void mark_referenced_resources (rtx, struct resources *, bool); extern void clear_hashed_info_for_insn (rtx_insn *); +extern void clear_hashed_info_until_next_barrier (rtx_insn *); extern void incr_ticks_for_insn (rtx_insn *); extern void mark_end_of_function_resources (rtx, bool); extern void init_resource_info (rtx_insn *);