From patchwork Tue Mar 3 09:40:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1248203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-520517-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=eR5D0OyC; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jYDCyYxA; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48WsTM5Xfxz9sPg for ; Tue, 3 Mar 2020 20:41:11 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; q=dns; s=default; b=cKcHOQfOtE0Gr2kJ sCR45vXaeQ/hWSfkdHYS8v6+3ayrdPZnxA1SeyuE2BU+fcEcx4kbu5e7j4POTaYb w3vVFdHrzffWJqYvLv7MutPSlT0eoEDq3OfDY3Ytw2STJUNpGML8uaAnWWCCmn1t BnbBx4ek3ltUxZ4OpYSjNfkrVz0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=default; bh=LDqu8U6RawwDKAvh6l9soW z7Vio=; b=eR5D0OyCyJMBeR+LaoW+9HtjxsC4D8C14bnmz7WTzvgciUCOToGvKw yzH4BeQt/hgbo9zMrgatsXSVJRSsFTTwQV0Kz1Rsh8sm12wwLRl/T6FuMfd5L0Md tK/ZWYLwxl4tcUfLDg9votx5j3TzF0x0DmkVTDcWKBxn22XJaz14I= Received: (qmail 64476 invoked by alias); 3 Mar 2020 09:41:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 64462 invoked by uid 89); 3 Mar 2020 09:41:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=ths, alternatives, arcmd, arc.md X-HELO: mail-wr1-f52.google.com Received: from mail-wr1-f52.google.com (HELO mail-wr1-f52.google.com) (209.85.221.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Mar 2020 09:41:02 +0000 Received: by mail-wr1-f52.google.com with SMTP id j7so3367581wrp.13 for ; Tue, 03 Mar 2020 01:41:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+xXpPJkRgMt6OSbNGu5bB+YpsFOI6w2X2X+wSSYoInk=; b=jYDCyYxAYbq2Ajj+f5bCAirIcB2WYRsOaMjFfjtxdJG0p4nFRkH9MM848auLdDGFjW TllbMaZWUd17gLdd9gRQ/XSH68LJoB9WekMXrtNo9eMLzUrGWroxtDxTOshjH3THFVtk PTnSu5Aly6HNZ6HNif3M00BJvfxoR73iQhRb6q3KUgyMd2SP6n7EC/4djOyKm4RcfBs7 GPZULSgJU+jjBs+MEjG7wMRXC89eHNXZri7LqHSPHvYK/xlqQgt0/gUR1TZ2IG2de0Gd SSJWd8JgMdZ4fZc7eYdANV0I7j+D66fW4yU674L0DfkE6dLPe3Nf7i074V8NNjJRwJna srQQ== Received: from localhost.localdomain ([79.115.250.90]) by smtp.gmail.com with ESMTPSA id n11sm22453233wrq.40.2020.03.03.01.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2020 01:40:59 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: law@redhat.com, fbedard@synopsys.com, claziss@synopsys.com, andrew.burgess@embecosm.com Subject: [PATCH 1/3] [ARC] Remove mmixed-code option. Date: Tue, 3 Mar 2020 11:40:44 +0200 Message-Id: <20200303094046.1439895-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The mmixed-code option is obsolete, remove it. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.c (arc_override_options): Remove TARGET_MIXED_CODE reference. * config/arc/arc.md (abssi2_mixed): Remove pattern. * config/arc/arc.h (TARGET_MIXED_CODE): Remove macro. (INDEX_REG_CLASS): Only refer to GENERAL_REGS. * config/arc/arc.opt (mmixed-code): Remove option. * doc/invoke.texi (ARC): Remove mmixed-code doc. --- gcc/config/arc/arc.h | 4 +--- gcc/config/arc/arc.md | 8 -------- gcc/config/arc/arc.opt | 8 -------- gcc/doc/invoke.texi | 8 +------- 4 files changed, 2 insertions(+), 26 deletions(-) diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index b7fa7ba8fa3..21ffeee9ad2 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -115,8 +115,6 @@ extern const char *arc_cpu_to_as (int argc, const char **argv); /* Run-time compilation parameters selecting different hardware subsets. */ -#define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET) - #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET) #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \ || TARGET_FP_DP_AX) @@ -571,7 +569,7 @@ extern enum reg_class arc_regno_reg_class[]; a scale factor or added to another register (as well as added to a displacement). */ -#define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS) +#define INDEX_REG_CLASS GENERAL_REGS /* The class value for valid base registers. A base register is one used in an address which is the register value plus a displacement. */ diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index a26a7a4dd5f..e1958fda2e6 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2001,14 +2001,6 @@ archs4x, archs4xd" ;; Absolute instructions -(define_insn "*abssi2_mixed" - [(set (match_operand:SI 0 "compact_register_operand" "=q") - (abs:SI (match_operand:SI 1 "compact_register_operand" "q")))] - "TARGET_MIXED_CODE" - "abs%? %0,%1%&" - [(set_attr "type" "two_cycle_core") - (set_attr "iscompact" "true")]) - (define_insn "abssi2" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,w,w") (abs:SI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,Cal")))] diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index deaf306739e..2b2b947ca08 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -135,14 +135,6 @@ mcode-density Target Report Mask(CODE_DENSITY) Enable code density instructions for ARCv2. -mmixed-code -Target Report Mask(MIXED_CODE_SET) -Tweak register allocation to help 16-bit instruction generation. -; originally this was: -;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions -; but we do that without -mmixed-code, too, it's just a different instruction -; count / size tradeoff. - ; We use an explict definition for the negative form because that is the ; actually interesting option, and we want that to have its own comment. mvolatile-cache diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8c6c90217f4..7627e889b5d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -727,7 +727,7 @@ Objective-C and Objective-C++ Dialects}. -mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol -mexpand-adddi -mindexed-loads -mlra -mlra-priority-none @gol -mlra-priority-compact mlra-priority-noncompact -mmillicode @gol --mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol +-mq-class -mRcq -mRcw -msize-level=@var{level} @gol -mtune=@var{cpu} -mmultcost=@var{num} -mcode-density-frame @gol -munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol -mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index} @@ -17956,12 +17956,6 @@ This option enable the compiler to emit @code{enter} and @code{leave} instructions. These instructions are only valid for CPUs with code-density feature. -@item -mmixed-code -@opindex mmixed-code -Tweak register allocation to help 16-bit instruction generation. -This generally has the effect of decreasing the average instruction size -while increasing the instruction count. - @item -mq-class @opindex mq-class Ths option is deprecated. Enable @samp{q} instruction alternatives. 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run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 64477 invoked by uid 89); 3 Mar 2020 09:41:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:2642, HContent-Transfer-Encoding:8bit X-HELO: mail-wm1-f66.google.com Received: from mail-wm1-f66.google.com (HELO mail-wm1-f66.google.com) (209.85.128.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Mar 2020 09:41:03 +0000 Received: by mail-wm1-f66.google.com with SMTP id g83so2102494wme.1 for ; Tue, 03 Mar 2020 01:41:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HdRJ1ADPxPvAPe/XLRCFCSSFuXFgjzJVxKZOTSkKlrs=; b=kxK450yvQ7ay9D3vAp1Ph+dRW3/k2xRliqdNlRiHVxz98/Wz5/AQL5is6Tf86CPA7X vG+kM8+7HaZd1rpNJ6+QcLdkSPgjMFuAIYpKhm47EYba7nVd4QWfYhaOtbboOfbrv48W J6DH/GNp4gFQMKoFkd27HCQDAFde8t/ZQl1+o9PvZMnaQBh4LJBaU1AyPY4v2Vx2xcs8 +1skV7UjUph+5AMM5K5BIM9v0ic407L7NJBaUVexGT4LaVqaAnqPstr8Bvrk2WSrSYPU /qClry+3CKR5y0PZEOAxs1LVz8F4ZH16zhknVdt0QncKuskL2YxtPKlkukgJ2NBMsgq2 qqUA== Received: from localhost.localdomain ([79.115.250.90]) by smtp.gmail.com with ESMTPSA id n11sm22453233wrq.40.2020.03.03.01.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2020 01:41:00 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: law@redhat.com, fbedard@synopsys.com, claziss@synopsys.com, andrew.burgess@embecosm.com Subject: [PATCH 2/3] [ARC] Remove malign-call Date: Tue, 3 Mar 2020 11:40:45 +0200 Message-Id: <20200303094046.1439895-2-claziss@gmail.com> In-Reply-To: <20200303094046.1439895-1-claziss@gmail.com> References: <20200303094046.1439895-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The malign-call option is obsolete, remove it. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.opt (malign-call): Remove option. * doc/invoke.texi (ARC): Remove malign-call doc. * common/config/arc/arc-common.c (arc_option_optimization_table): Remove malign-call. --- gcc/common/config/arc/arc-common.c | 1 - gcc/config/arc/arc.opt | 4 ---- gcc/doc/invoke.texi | 6 +----- 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 14c20123c70..7f46f547e30 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -62,7 +62,6 @@ static const struct default_options arc_option_optimization_table[] = { OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 }, { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 }, - { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 }, { OPT_LEVELS_NONE, 0, NULL, 0 } }; diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 2b2b947ca08..a8af5138183 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -301,10 +301,6 @@ mannotate-align Target Var(TARGET_ANNOTATE_ALIGN) Explain what alignment considerations lead to the decision to make an insn short or long. -malign-call -Target Var(TARGET_ALIGN_CALL) -Do alignment optimizations for call instructions. - mRcq Target Var(TARGET_Rcq) Enable Rcq constraint handling - most short code generation depends on this. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7627e889b5d..802d36d4098 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -723,7 +723,7 @@ Objective-C and Objective-C++ Dialects}. -mlong-calls -mmedium-calls -msdata -mirq-ctrl-saved @gol -mrgf-banked-regs -mlpc-width=@var{width} -G @var{num} @gol -mvolatile-cache -mtp-regno=@var{regno} @gol --malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol +-mauto-modify-reg -mbbit-peephole -mno-brcc @gol -mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol -mexpand-adddi -mindexed-loads -mlra -mlra-priority-none @gol -mlra-priority-compact mlra-priority-noncompact -mmillicode @gol @@ -17861,10 +17861,6 @@ Enable cache bypass for volatile references. The following options fine tune code generation: @c code generation tuning options @table @gcctabopt -@item -malign-call -@opindex malign-call -Do alignment optimizations for call instructions. - @item -mauto-modify-reg @opindex mauto-modify-reg Enable the use of pre/post modify with register displacement. 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Date: Tue, 3 Mar 2020 11:40:46 +0200 Message-Id: <20200303094046.1439895-3-claziss@gmail.com> In-Reply-To: <20200303094046.1439895-1-claziss@gmail.com> References: <20200303094046.1439895-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The munalign-prob-threshold option is obsolete, remove it. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.opt (munalign-prob-threshold): Remove option. * doc/invoke.texi (ARC): Remove munalign-prob-threshold doc. * config/arc/arc.c (arc_unalign_branch_p): Remove unused function. --- gcc/config/arc/arc.c | 23 ----------------------- gcc/config/arc/arc.opt | 6 ------ gcc/doc/invoke.texi | 11 +---------- 3 files changed, 1 insertion(+), 39 deletions(-) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index c57febd3783..af26e5b9711 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -9920,29 +9920,6 @@ gen_acc2 (void) return gen_rtx_REG (SImode, TARGET_BIG_ENDIAN ? 57: 56); } -/* FIXME: a parameter should be added, and code added to final.c, - to reproduce this functionality in shorten_branches. */ -#if 0 -/* Return nonzero iff BRANCH should be unaligned if possible by upsizing - a previous instruction. */ -int -arc_unalign_branch_p (rtx branch) -{ - rtx note; - - if (!TARGET_UNALIGN_BRANCH) - return 0; - /* Do not do this if we have a filled delay slot. */ - if (get_attr_delay_slot_filled (branch) == DELAY_SLOT_FILLED_YES - && !NEXT_INSN (branch)->deleted ()) - return 0; - note = find_reg_note (branch, REG_BR_PROB, 0); - return (!note - || (arc_unalign_prob_threshold && !br_prob_note_reliable_p (note)) - || INTVAL (XEXP (note, 0)) < arc_unalign_prob_threshold); -} -#endif - /* When estimating sizes during arc_reorg, when optimizing for speed, there are three reasons why we need to consider branches to be length 6: - annull-false delay slot insns are implemented using conditional execution, diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index a8af5138183..244c3abd86d 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -287,12 +287,6 @@ mmul32x16 Target Report Mask(MULMAC_32BY16_SET) Generate 32x16 multiply and mac instructions. -; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , -; alas, basic-block.h is not included in options.c . -munalign-prob-threshold= -Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) -Set probability threshold for unaligning branches. - mmedium-calls Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) Don't use less than 25 bit addressing range for calls. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 802d36d4098..51c2d6d04de 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -729,7 +729,7 @@ Objective-C and Objective-C++ Dialects}. -mlra-priority-compact mlra-priority-noncompact -mmillicode @gol -mq-class -mRcq -mRcw -msize-level=@var{level} @gol -mtune=@var{cpu} -mmultcost=@var{num} -mcode-density-frame @gol --munalign-prob-threshold=@var{probability} -mmpy-option=@var{multo} @gol +-mmpy-option=@var{multo} @gol -mdiv-rem -mcode-density -mll64 -mfpu=@var{fpu} -mrf16 -mbranch-index} @emph{ARM Options} @@ -18031,15 +18031,6 @@ Tune for ARC4x release 3.10a. Cost to assume for a multiply instruction, with @samp{4} being equal to a normal instruction. -@item -munalign-prob-threshold=@var{probability} -@opindex munalign-prob-threshold -Set probability threshold for unaligning branches. -When tuning for @samp{ARC700} and optimizing for speed, branches without -filled delay slot are preferably emitted unaligned and long, unless -profiling indicates that the probability for the branch to be taken -is below @var{probability}. @xref{Cross-profiling}. -The default is (REG_BR_PROB_BASE/2), i.e.@: 5000. - @end table The following options are maintained for backward compatibility, but