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Thu, 27 Feb 2020 12:21:01 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89FFB6A04F; Thu, 27 Feb 2020 12:21:00 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:21:00 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:27 -0500 Message-Id: <20200227122042.32692-2-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 01/16] doc/opal-uv-abi.rst X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Ryan Grimm --- doc/opal-uv-abi.rst | 425 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 425 insertions(+) create mode 100644 doc/opal-uv-abi.rst diff --git a/doc/opal-uv-abi.rst b/doc/opal-uv-abi.rst new file mode 100644 index 00000000..79474a34 --- /dev/null +++ b/doc/opal-uv-abi.rst @@ -0,0 +1,425 @@ +.. SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + +================= +OPAL UV ABI (RFC) +================= + +.. contents:: + :depth: 3 + +.. sectnum:: + :depth: 3 + +This document describes the function calling interface between OPAL +and the Ultravisor. + +Protected Execution Facility +############################ + +Protected Execution Facility (PEF) is an architectural change for +POWER 9 that enables Secure Virtual Machines (SVMs). When enabled, +PEF adds a new higher privileged mode, called Ultravisor mode, to +POWER architecture. Along with the new mode there is new firmware +called the Protected Execution Ultravisor (or Ultravisor for short). +Ultravisor mode is the highest privileged mode in POWER architecture. + ++------------------+ +| Privilege States | ++==================+ +| Problem | ++------------------+ +| Supervisor | ++------------------+ +| Hypervisor | ++------------------+ +| Ultravisor | ++------------------+ + +PEF protects SVMs from the hypervisor, privileged users, and other +VMs in the system. SVMs are protected while at rest and can only be +executed by an authorized machine. All virtual machines utilize +hypervisor services. The Ultravisor filters calls between the SVMs +and the hypervisor to assure that information does not accidentally +leak. All hypercalls except H_RANDOM are reflected to the hypervisor. +H_RANDOM is not reflected to prevent the hypervisor from influencing +random values in the SVM. + +To support this there is a refactoring of the ownership of resources +in the CPU. Some of the resources which were previously hypervisor +privileged are now ultravisor privileged. + +Hardware +======== + +The hardware changes include the following: + +* There is a new bit in the MSR that determines whether the current + process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process + is in secure mode, MSR(s)=0 process is in normal mode. + +* The MSR(S) bit can only be set by the Ultravisor. + +* HRFID cannot be used to set the MSR(S) bit. If the hypervisor needs + to return to a SVM it must use an ultracall. It can determine if + the VM it is returning to is secure. + +* There is a new Ultravisor privileged register, SMFCTRL, which has an + enable/disable bit SMFCTRL(E). + +* The privilege of a process is now determined by three MSR bits, + MSR(S, HV, PR). In each of the tables below the modes are listed + from least privilege to highest privilege. The higher privilege + modes can access all the resources of the lower privilege modes. + +**Secure Mode MSR Settings** + ++---+---+---+---------------+ +| S | HV| PR|Privilege | ++===+===+===+===============+ +| 1 | 0 | 1 | Problem | ++---+---+---+---------------+ +| 1 | 0 | 0 | Privileged(OS)| ++---+---+---+---------------+ +| 1 | 1 | 0 | Ultravisor | ++---+---+---+---------------+ +| 1 | 1 | 1 | Reserved | ++---+---+---+---------------+ + +**Normal Mode MSR Settings** + ++---+---+---+---------------+ +| S | HV| PR|Privilege | ++===+===+===+===============+ +| 0 | 0 | 1 | Problem | ++---+---+---+---------------+ +| 0 | 0 | 0 | Privileged(OS)| ++---+---+---+---------------+ +| 0 | 1 | 0 | Hypervisor | ++---+---+---+---------------+ +| 0 | 1 | 1 | Problem (HV) | ++---+---+---+---------------+ + +* Memory is partitioned into secure and normal memory. Only processes + that are running in secure mode can access secure memory. + +* The hardware does not allow anything that is not running secure to + access secure memory. This means that the Hypervisor cannot access + the memory of the SVM without using an ultracall (asking the + Ultravisor). The Ultravisor will only allow the hypervisor to see + the SVM memory encrypted. + +* I/O systems are not allowed to directly address secure memory. This + limits the SVMs to virtual I/O only. + +* The architecture allows the SVM to share pages of memory with the + hypervisor that are not protected with encryption. However, this + sharing must be initiated by the SVM. + +* When a process is running in secure mode all hypercalls + (syscall lev=1) are reflected to the Ultravisor. + +* When a process is in secure mode all interrupts go to the + Ultravisor. + +* The following resources have become Ultravisor privileged and + require an Ultravisor interface to manipulate: + + * Processor configurations registers (SCOMs). + + * Stop state information. + + * The debug registers CIABR, DAWR, and DAWRX become Ultravisor + resources when SMFCTRL(D) is set. If SMFCTRL(D) is not set they do + not work in secure mode. When set, reading and writing requires + an Ultravisor call, otherwise that will cause a Hypervisor Emulation + Assistance interrupt. + + * PTCR and partition table entries (partition table is in secure + memory). An attempt to write to PTCR will cause a Hypervisor + Emulation Assitance interrupt. + + * LDBAR (LD Base Address Register) and IMC (In-Memory Collection) + non-architected registers. An attempt to write to them will cause a + Hypervisor Emulation Assistance interrupt. + + * Paging for an SVM, sharing of memory with Hypervisor for an SVM. + (Including Virtual Processor Area (VPA) and virtual I/O). + +Software/Microcode +================== + +The software changes include: + +* When the UV_ESM ultracall is made the Ultravisor copies the VM into + secure memory, decrypts the verification information, and checks the + integrity of the SVM. If the integrity check passes the Ultravisor + passes control in secure mode. + +The Ultravisor offers new services to the hypervisor and SVMs. These +are accessed through ultracalls. + +Terminology +=========== + +* Hypercalls: special system calls used to request services from + Hypervisor. + +* Normal memory: Memory that is accessible to Hypervisor. + +* Normal page: Page backed by normal memory and available to + Hypervisor. + +* Secure memory: Memory that is accessible only to Ultravisor and + SVMs. + +* Secure page: Page backed by secure memory and only available to + Ultravisor and SVM. + +* SVM: Secure Virtual Machine. + +* Ultracalls: special system calls used to request services from + Ultravisor. + +Ultravisor Initialization +######################### + +Secure Memory +============= + +Skiboot parses secure memory from the HDAT tables and creates the secure-memory +and ibm,ultravisor device tree nodes. secure-memory similar to a memory@ node +except the device_type is "secure_memory". For example: + +.. code-block:: dts + + secure-memory@100fe00000000 { + device_type = "secure_memory"; + compatible = "ibm,secure_memory"; + ibm,chip-id = <0>; + reg = < 0x100fe 0x0 0x2 0x0>; + } + +Regions of secure memory will be reserved by hostboot such as OCC, HOMER, and +SBE. Skiboot will use the existing reserve infrastructure to reserve them. +For example: + +.. code-block:: + + ibm,HCODE@100fffcaf0000 + ibm,OCC@100fffcdd0000 + ibm,RINGOVD@100fffcae0000 + ibm,WOFDATA@100fffcb90000 + ibm,arch-reg-data@100fffd700000 + ibm,hbrt-code-image@100fffcec0000 + ibm,hbrt-data@100fffd420000 + ibm,homer-image@100fffd800000 + ibm,homer-image@100fffdc00000 + ibm,occ-common-area@100ffff800000 + ibm,sbe-comm@100fffce90000 + ibm,sbe-comm@100fffceb0000 + ibm,sbe-ffdc@100fffce80000 + ibm,sbe-ffdc@100fffcea0000 + ibm,secure-crypt-algo-code@100fffce70000 + ibm,uvbwlist@100fffcad0000 + +For Mambo, ultra.tcl creates the secure-memory device tree node and the +ibm,ultravisor device tree node in external/mambo/skiboot.tcl. Secure memory +is currently defined as the bottom half of the total the size of memory. Mambo +has no protection on secure memory, so a watchpoint could be used to ensure +Skiboot does not touch secure memory. + +For BML, the BML script parses secure memory from the Cronus config file and +creates the secure-memory and ibm,ultravisor device tree nodes. + +In all cases, the console log should indicate secure memory has been found and +added to the device tree. For example: + +.. code-block:: + + [ 68.235326307,5] UV: Secure memory range added to DT [0x0001000e00000000..0x001001000000000] + +Loading The Ultravisor +====================== + +Skiboot uses secure and trusted boot to load and verify the compressed UV image +from the PNOR into regular memory. It unpacks the UV into regular memory in +the function ``init_uv``. + +``init_uv`` finds the UV node in the device tree via the "ibm,ultravisor" +compatible property. For example: + +.. code-block:: dts + + ibm,ultravisor { + compatible = "ibm,ultravisor"; + #address-cells = <0x02>; + #size-cells = <0x02>; + + firmware@200000000 { + compatible = "ibm,uv-firmware"; + reg = <0x02 0x00 0xf677f>; + uv-src-address = <0x00 0xc0000000>; + memcons = <0x00 0x3022d030>; + sys-fdt = <0x00 0x30509068>; + uv-fdt = <0x02 0x200000>; + }; + }; + +Skiboot creates ibm,ultravisor and the reg property in hdata/spira.c. + +Mambo and BML use scripts to put the ultra image directly in regular memory and +uv-src-address is provided so skiboot knows where to copy the UV image from, +like the example above. + +Starting The Ultravisor +======================= + +Skiboot starts the UV in ``main_cpu_entry`` before the kernel is loaded and booted. +Skiboot creates a job on all threads and sends them to ``start_uv`` in asm/head.S. +This function's prototype is: + +.. code-block:: c + + /** + * @brief Start UV. + * + * @param uv_load_addr Load address of ultravisor. + * @param sys_fdt Pointer to system fdt + * + * @return 0 on success, else a negative error code on failure. + */ + u64 start_uv(u64 uv_load_addr, void *sys_fdt) + +The sys_fdt allows passing information to the UV, such as the location of the +memory consolde ultravisor fdt and is easy to extend. + +The ``uv_fdt`` is constructed in secure memory. It is allocated after the +ultravisor image at ``uv_base_addr + UV_LOAD_MAX_SIZE``. This allows the +ultravisor to load at start of the first secure memory range and recover the +memory allocated to ``uv_fdt``. + +.. code-block:: dts + + ibm,uv-fdt { + compatible = "ibm,uv-fdt"; + wrapping-key-password = "gUMShz6l2x4O9IeHrvBSuBR0FYANZTYK"; + }; + +The UV parses ``sys_fdt``, creates internal structures, and threads return in +hypervisor privilege moded. + +If successful, skiboot sets a variable named ``uv_present`` to true. Skiboot +uses this variable to dermine if the UV is initialized and ready to perform +ucalls. + +uv_base_addr is used by skiboot to know where to jump to. + +Ultravisor Failed Start Recovery +================================ + +If the ultravisor fails to start it will return a error code to init_uv. +init_uv will print error messages to the skiboot log and attempt to free +structures associated with the ultravisor. + +Skiboot will continue to be in ultravisor privilege mode, and will need to +perform a recovery action. + +[**TODO**: Need to describe the steps for Ultravisor load failure recovery action.] + +Ultracalls +########## + +Ultravisor calls ABI +==================== + +This section describes Ultravisor calls (ultracalls) needed by skiboot. +The ultracalls allow the skiboot to request services from the +Ultravisor such as initializing a chip unit via XSCOM. + +The specific service needed from an ultracall is specified in register +R3 (the first parameter to the ultracall). Other parameters to the +ultracall, if any, are specified in registers R4 through R12. + +Return value of all ultracalls is in register R3. Other output values +from the ultracall, if any, are returned in registers R4 through R12. + +Each ultracall returns specific error codes, applicable in the context +of the ultracall. However, like with the PowerPC Architecture Platform +Reference (PAPR), if no specific error code is defined for a +particular situation, then the ultracall will fallback to an erroneous +parameter-position based code. i.e U_PARAMETER, U_P2, U_P3 etc +depending on the ultracall parameter that may have caused the error. + +For now this only covers ultracalls currently implemented and being used by +skiboot but others can be added here when it makes sense. + +The full specification for all ultracalls will eventually be made available in +the public/OpenPower version of the PAPR specification. + +Ultracalls used by Skiboot +========================== + +UV_READ_SCOM +------------ + +Perform an XSCOM read and put the value in a buffer. + +Syntax +~~~~~~ + +.. code-block:: c + + long ucall(unsigned long UV_READ_SCOM, + unsigned long *retbuf, + u64 partid, + u64 pcb_addr) + +Return values +~~~~~~~~~~~~~ + +* U_SUCCESS on success. +* U_PERMISSION if called from VM context. +* U_PARAMETER if invalid partiton or address. +* U_BUSY if unit is busy, need to retry. +* U_XSCOM_CHIPLET_OFF if cpu is asleep. +* U_XSCOM_PARTIAL_GOOD if partial good. +* U_XSCOM_ADDR_ERROR if address error. +* U_XSCOM_CLOCK_ERROR if clock error. +* U_XSCOM_PARITY_ERROR if parity error. +* U_XSCOM_TIMEOUT if timeout. + +UV_WRITE_SCOM +------------- + +Perform an XSCOM write. + +Syntax +~~~~~~ + +.. code-block:: c + + long ucall(unsigned long UV_WRITE_SCOM, + u64 partid, + u64 pcb_addr, + u64 val) + +Return values +~~~~~~~~~~~~~ + +One of the following values: + +* U_SUCCESS on success. +* U_PERMISSION if called from VM context. +* U_PARAMETER if invalid partiton. +* U_BUSY if unit is busy, need to retry. +* U_XSCOM_CHIPLET_OFF if cpu is asleep. +* U_XSCOM_PARTIAL_GOOD if partial good. +* U_XSCOM_ADDR_ERROR if address error. +* U_XSCOM_CLOCK_ERROR if clock error. +* U_XSCOM_PARITY_ERROR if parity error. +* U_XSCOM_TIMEOUT if timeout. + +References +########## + +.. [1] `Supporting Protected Computing on IBM Power Architecture `_ From patchwork Thu Feb 27 12:20:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SssX0mPfz9sP7 for ; Thu, 27 Feb 2020 23:48:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48SssX02cWzDqwJ for ; Thu, 27 Feb 2020 23:48:16 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 27 Feb 2020 12:21:12 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 619996A057; Thu, 27 Feb 2020 12:21:11 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:21:11 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:28 -0500 Message-Id: <20200227122042.32692-3-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 phishscore=0 impostorscore=0 suspectscore=3 adultscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 02/16] Add functions to initialize and start an ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Power 9 introduces a mode called ultravisor mode. init_uv looks for uv-src-address in the device tree and copies the image to the address specified in "reg". start_ultravisor is called in load_and_boot_kernel with the pointer to the system fdt. Every thread is sent to the ultravisor image and returns with UV mode off. A minimal ultravisor could disable UV and PEF, instructions in commit "skiboot.tcl: ultravisor support." [ maddy: Initial implementation] [Signed-off-by: Madhavan Srinivasan [ santosh: Initial implementation] Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- asm/misc.S | 22 ++++++++++++ core/init.c | 6 ++++ hw/Makefile.inc | 2 +- hw/ultravisor.c | 81 ++++++++++++++++++++++++++++++++++++++++++++ include/processor.h | 8 +++++ include/ultravisor.h | 17 ++++++++++ 6 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 hw/ultravisor.c create mode 100644 include/ultravisor.h diff --git a/asm/misc.S b/asm/misc.S index 647f60b2..f9dea492 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -255,3 +255,25 @@ enter_p9_pm_state: mtspr SPR_PSSCR,%r3 PPC_INST_STOP b . + +/* + * start_uv register usage: + * + * r3 : UV base addr + * r4 : system fdt + */ +.global start_uv +start_uv: + mflr %r0 + std %r0,16(%r1) + sync + /* flush caches, etc */ + icbi 0,%r3 + sync + isync + mtctr %r3 + mr %r3,%r4 + bctrl /* branch to UV here */ + ld %r0,16(%r1) + mtlr %r0 + blr diff --git a/core/init.c b/core/init.c index 339462e5..f124f893 100644 --- a/core/init.c +++ b/core/init.c @@ -46,6 +46,7 @@ #include #include #include +#include enum proc_gen proc_gen; unsigned int pcie_max_link_speed; @@ -602,6 +603,8 @@ void __noreturn load_and_boot_kernel(bool is_reboot) abort(); } + start_ultravisor(fdt); + op_display(OP_LOG, OP_MOD_INIT, 0x000C); mem_dump_free(); @@ -1354,6 +1357,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Add the list of interrupts going to OPAL */ add_opal_interrupts(); + /* Initialize the ultravisor */ + init_uv(); + /* Now release parts of memory nodes we haven't used ourselves... */ mem_region_release_unused(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index b708bdfe..9a4872ca 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -8,7 +8,7 @@ HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o -HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o +HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o ultravisor.o HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/ultravisor.c b/hw/ultravisor.c new file mode 100644 index 00000000..362b7f54 --- /dev/null +++ b/hw/ultravisor.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#include +#include +#include +#include +#include +#include +#include + +static struct dt_node *uv_fw_node; +static uint64_t uv_base_addr; + +static void cpu_start_ultravisor(void *fdt) +{ + prlog(PR_DEBUG, "UV: Starting on CPU 0x%04x\n", this_cpu()->pir); + start_uv(uv_base_addr, fdt); +} + +int start_ultravisor(void *fdt) +{ + struct cpu_thread *cpu; + struct cpu_job **jobs; + int i = 0; + + if (!uv_base_addr || !fdt) { + prlog(PR_DEBUG, "UV: Bad pointers, not starting\n"); + return OPAL_INTERNAL_ERROR; + } + + jobs = zalloc(sizeof(struct cpu_job *) * cpu_max_pir); + + prlog(PR_DEBUG, "UV: Starting @0x%016llx fdt %p\n", + uv_base_addr, fdt); + + for_each_available_cpu(cpu) { + if (cpu == this_cpu()) + continue; + jobs[i++] = cpu_queue_job(cpu, "start_ultravisor", + cpu_start_ultravisor, fdt); + } + + cpu_start_ultravisor(fdt); + + while (i > 0) + cpu_wait_job(jobs[--i], true); + + free(jobs); + + return OPAL_SUCCESS; +} + +void init_uv() +{ + uint64_t uv_dt_src, uv_fw_sz; + + if (!is_msr_bit_set(MSR_S)) { + prlog(PR_DEBUG, "UV: S bit not set\n"); + return; + } + + uv_fw_node = dt_find_compatible_node(dt_root, NULL, "ibm,uv-firmware"); + if (!uv_fw_node) { + prerror("UV: No ibm,uv-firmware node found\n"); + return; + } + + if (!dt_find_property(uv_fw_node, "uv-src-address")) { + prerror("UV: No uv-src-address found\n"); + return; + } + + uv_dt_src = dt_prop_get_u64(uv_fw_node, "uv-src-address"); + uv_base_addr = dt_get_address(uv_fw_node, 0, &uv_fw_sz); + + prlog(PR_INFO, "UV: Copying to protected memory 0x%llx from 0x%llx\n", + uv_base_addr, uv_dt_src); + + memcpy((void *)uv_base_addr, (void *)uv_dt_src, UV_LOAD_MAX_SIZE); +} diff --git a/include/processor.h b/include/processor.h index a0c2864a..f1a88d32 100644 --- a/include/processor.h +++ b/include/processor.h @@ -11,6 +11,7 @@ #define MSR_HV PPC_BIT(3) /* Hypervisor mode */ #define MSR_VEC PPC_BIT(38) /* VMX enable */ #define MSR_VSX PPC_BIT(40) /* VSX enable */ +#define MSR_S PPC_BIT(41) /* Secure mode enable */ #define MSR_EE PPC_BIT(48) /* External Int. Enable */ #define MSR_PR PPC_BIT(49) /* Problem state */ #define MSR_FP PPC_BIT(50) /* Floating Point Enable */ @@ -371,6 +372,13 @@ static inline void st_le32(uint32_t *addr, uint32_t val) asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr)); } +static inline bool is_msr_bit_set(uint64_t bit) +{ + if (mfmsr() & bit) + return true; + return false; +} + #endif /* __TEST__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/ultravisor.h b/include/ultravisor.h new file mode 100644 index 00000000..44cf36bf --- /dev/null +++ b/include/ultravisor.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#ifndef __ULTRAVISOR_H +#define __ULTRAVISOR_H + +#include +#include + +#define UV_LOAD_MAX_SIZE 0x200000 + +extern int start_uv(uint64_t entry, void *fdt); + +int start_ultravisor(void *fdt); +void init_uv(void); + +#endif /* __ULTRAVISOR_H */ From patchwork Thu Feb 27 12:20:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245829 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SsqR6ZJRz9sP7 for ; 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Thu, 27 Feb 2020 12:21:25 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCLML464815490 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:21:22 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F62C6A047; Thu, 27 Feb 2020 12:21:22 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AA2556A051; Thu, 27 Feb 2020 12:21:21 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:21:21 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:29 -0500 Message-Id: <20200227122042.32692-4-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=245 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 03/16] Disable protected execution facility X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch disables Protected Execution Faciltiy (PEF). This software procedure is needed for the lab because Cronus will be configured to bring the machine up with PEF on. Hostboot has a similar procedure for running with PEF off. Skiboot can run with PEF on but the kernel cannot; the kernel will take a machine check when trying to write a protected resource, such as the PTCR. So, use this until we have an ultravisor, or if we want to use BML with Cronus without UV = 1. Signed-off-by: Ryan Grimm --- asm/misc.S | 39 +++++++++++++++++++++++++++++++++++++++ include/processor.h | 3 +++ 2 files changed, 42 insertions(+) diff --git a/asm/misc.S b/asm/misc.S index f9dea492..9d2f3b6e 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -277,3 +277,42 @@ start_uv: ld %r0,16(%r1) mtlr %r0 blr + +/* + * Exit UV mode and disable Protected Execution Facility + * For each core, this should be run on all secondary threads first to bring + * them out of UV mode. Then, it is called by the primary thread to disable + * PEF and bring it out of UV mode. All threads will then be running in HV + * mode. The only way to reenable UV mode is with a reboot. + * + * Power9 hardware requires [h]srr1 to be set explicitly. + * + * r3 = 1 if primary thread + * 0 if secondary thread + */ +.global exit_uv_mode +exit_uv_mode: + mfmsr %r4 + LOAD_IMM64(%r5, ~MSR_S) + and %r4,%r4,%r5 + mtspr SPR_USRR1,%r4 + + mfspr %r4,SPR_HSRR1 + and %r4,%r4,%r5 + mtspr SPR_HSRR1,%r3 + + mfspr %r4,SPR_SRR1 + and %r4,%r4,%r5 + mtspr SPR_SRR1,%r4 + + cmpdi %r3,1 + bne 1f + mfspr %r4, SPR_SMFCTRL + LOAD_IMM64(%r5, ~PPC_BIT(0)) + and %r4,%r4,%r5 + mtspr SPR_SMFCTRL,%r4 +1: + isync + mflr %r4 + mtspr SPR_USRR0,%r4 + urfid diff --git a/include/processor.h b/include/processor.h index f1a88d32..65e4a07b 100644 --- a/include/processor.h +++ b/include/processor.h @@ -66,6 +66,9 @@ #define SPR_HMEER 0x151 /* HMER interrupt enable mask */ #define SPR_PCR 0x152 #define SPR_AMOR 0x15d +#define SPR_USRR0 0x1fa /* RW: Ultravisor Save/Restore Register 0 */ +#define SPR_USRR1 0x1fb /* RW: Ultravisor Save/Restore Register 1 */ +#define SPR_SMFCTRL 0x1ff /* RW: Secure Memory Facility Control */ #define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */ #define SPR_TSCR 0x399 #define SPR_HID0 0x3f0 From patchwork Thu Feb 27 12:20:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245830 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Ssqw4n9Jz9sRQ for ; Thu, 27 Feb 2020 23:46:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48Ssqw3lwPzDqsN for ; Thu, 27 Feb 2020 23:46:52 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; 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Thu, 27 Feb 2020 07:22:03 -0500 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ydq6xdcu7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2020 07:22:03 -0500 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 01RCKu0E030014; Thu, 27 Feb 2020 12:22:03 GMT Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by ppma04dal.us.ibm.com with ESMTP id 2ydcmm0e8e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2020 12:22:03 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCM01449742180 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:22:00 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6D5826A057; Thu, 27 Feb 2020 12:22:00 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6DAE26A047; Thu, 27 Feb 2020 12:21:59 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:21:59 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:30 -0500 Message-Id: <20200227122042.32692-5-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=896 clxscore=1015 mlxscore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 04/16] Add uv-entry dt property for starting ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We can jump into any location in the uv image for testing. Signed-off-by: Ryan Grimm --- hw/ultravisor.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 362b7f54..2fc1ecf1 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -14,8 +14,13 @@ static uint64_t uv_base_addr; static void cpu_start_ultravisor(void *fdt) { + uint64_t uv_entry = 0; + + if (dt_find_property(uv_fw_node, "uv-entry")) + uv_entry = dt_prop_get_u64(uv_fw_node, "uv-entry"); + prlog(PR_DEBUG, "UV: Starting on CPU 0x%04x\n", this_cpu()->pir); - start_uv(uv_base_addr, fdt); + start_uv(uv_base_addr + uv_entry, fdt); } int start_ultravisor(void *fdt) From patchwork Thu Feb 27 12:20:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245831 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SsrQ66r2z9sRR for ; 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Thu, 27 Feb 2020 12:22:09 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCM7EE48169232 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:22:07 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A0FB26A05A; Thu, 27 Feb 2020 12:22:07 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B5AA16A047; Thu, 27 Feb 2020 12:22:06 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:22:06 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:31 -0500 Message-Id: <20200227122042.32692-6-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=1 impostorscore=0 clxscore=1015 mlxscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 05/16] skiboot.tcl: ultravisor support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This tcl code turns on the S bit in MSR and sets up the SMF control register if MAMBO_ENABLE_SMF is set. It loads ULTRA_LID at 0xc0000000 and sets up the ibm,ultravisor device tree node if MAMBO_ENABLE_ULTRA is set. This can be tested using this skiboot as the ultravisor image with: export SKIBOOT=skiboot.lid export ULTRA_LID=$SKIBOOT export ULTRA_ENTRY=grep exit_uv_mode skiboot.map|cut -f1 -d " " export MAMBO_ENABLE_ULTRA=1 export MAMBO_ENABLE_SMF=1 All threads will then exit UV mode with SMF off. Signed-off-by: Ryan Grimm --- external/mambo/skiboot.tcl | 63 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl index 8d1cfc66..f6e0ee9e 100644 --- a/external/mambo/skiboot.tcl +++ b/external/mambo/skiboot.tcl @@ -56,6 +56,16 @@ if { ![info exists env(SKIBOOT_ZIMAGE)] } { } mconfig payload PAYLOAD $env(SKIBOOT_ZIMAGE) +mconfig ultra_image ULTRA_IMG $env(ULTRA_LID) + +mconfig ultra_src_addr ULTRA_SRC_ADDR 0xc0000000; + +mconfig ultra_entry ULTRA_ENTRY 0; + +mconfig enable_smf MAMBO_ENABLE_SMF none + +mconfig enable_ultra MAMBO_ENABLE_ULTRA none + mconfig linux_cmdline LINUX_CMDLINE "" # Paylod: Memory location for a Linux style ramdisk/initrd @@ -140,6 +150,10 @@ if { $default_config == "P9" } { if { $mconf(numa) } { myconf config memory_region_id_shift 45 } + + if { $mconf(enable_smf) } { + myconf config processor/initial/SMFCTRL 0x8000000000000002 + } } if { $mconf(numa) } { @@ -496,6 +510,9 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { mysim mcm 0 cpu $c thread $t set spr pir $pir lappend irqreg $pir incr pir + if { $mconf(enable_smf) } { + mysim mcm 0 cpu $c thread $t set spr msr 0x9000000000400000 + } } mysim of addprop $cpu_node array "ibm,ppc-interrupt-server#s" irqreg } @@ -658,6 +675,52 @@ if { [info exists env(SKIBOOT_ENABLE_MAMBO_STB)] } { } } +#top half of memory +mconfig spr_urmor ULTRA_URMOR [format "0x%016X" [expr [mysim display memory_size] / 2]] + +if {$mconf(enable_ultra) != "none"} { + set uv_node [ mysim of addchild $root_node "ibm,ultravisor" "" ] + mysim of addprop $uv_node string "compatible" "ibm,ultravisor" + mysim of addprop $uv_node int "#address-cells" 2 + mysim of addprop $uv_node int "#size-cells" 2 + + set uv_fw_node [ mysim of addchild $uv_node "firmware" "" ] + mysim of addprop $uv_fw_node string "compatible" "ibm,uv-firmware" + set src_addr $mconf(ultra_src_addr) + set src_addr_prop [ list [expr $src_addr >> 32] [expr $src_addr & 0xffffffff] ] + mysim of addprop $uv_fw_node array "uv-src-address" src_addr_prop + set uv_entry $mconf(ultra_entry) + set uv_entry_prop [ list [expr $uv_entry >> 32] [expr $uv_entry & 0xffffffff] ] + mysim of addprop $uv_fw_node array "uv-entry" uv_entry_prop + + set start $mconf(spr_urmor) + set size [expr [mysim display memory_size] - $mconf(spr_urmor)] + set reg [list [expr $start >> 32] [expr $start & 0xffffffff] [expr $size >> 32] [expr $size & 0xffffffff]] + mysim of addprop $uv_fw_node array "reg" reg + + #secure-memory node + set start_hex [format %x $start] + set secure_mem_node [mysim of addchild $root_node "secure-memory@$start_hex" ""] + mysim of addprop $secure_mem_node string "compatible" "ibm,secure-memory" + mysim of addprop $secure_mem_node array "reg" reg + mysim of addprop $secure_mem_node string "device_type" "secure-memory" + set associativity [list 4 0 0 0 0] + mysim of addprop $secure_mem_node "array" "ibm,associativity" associativity + set chip_id [format %x 0] + mysim of addprop $secure_mem_node array "ibm,chip-id" chip_id + + if {[file exists $mconf(ultra_image)]} { + puts "Using ultra from $mconf(ultra_image)" + set ultra_file $mconf(ultra_image) + } else { + puts "ERROR: Could not find ultra: $mconf(ultra_image)" + exit + } + + set ultra_size [file size $ultra_file] + mysim memory fread $src_addr $ultra_size $ultra_file +} + # Kernel command line args, appended to any from the device tree # e.g.: of::set_bootargs "xmon" # From patchwork Thu Feb 27 12:20:32 2020 Content-Type: text/plain; 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Thu, 27 Feb 2020 12:22:19 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB37E6A04D; Thu, 27 Feb 2020 12:22:18 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:22:18 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:32 -0500 Message-Id: <20200227122042.32692-7-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 suspectscore=1 mlxscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 06/16] Add memcons support for ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan The ultravisor console buffer is provided at offset 0x01100000 from the skiboot base. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj --- hw/ultravisor.c | 13 +++++++++++++ include/console.h | 3 +++ include/debug_descriptor.h | 1 + include/mem-map.h | 16 ++++++++++------ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 2fc1ecf1..a2fe63cc 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -8,10 +8,20 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; +struct memcons uv_memcons __section(".data.memcons") = { + .magic = MEMCONS_MAGIC, + .obuf_phys = INMEM_UV_CON_START, + .ibuf_phys = INMEM_UV_CON_START + INMEM_UV_CON_OUT_LEN, + .obuf_size = INMEM_UV_CON_OUT_LEN, + .ibuf_size = INMEM_UV_CON_IN_LEN, +}; + static void cpu_start_ultravisor(void *fdt) { uint64_t uv_entry = 0; @@ -83,4 +93,7 @@ void init_uv() uv_base_addr, uv_dt_src); memcpy((void *)uv_base_addr, (void *)uv_dt_src, UV_LOAD_MAX_SIZE); + + dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); + debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; } diff --git a/include/console.h b/include/console.h index 61448e28..1e7c2a10 100644 --- a/include/console.h +++ b/include/console.h @@ -28,9 +28,12 @@ struct memcons { }; extern struct memcons memcons; +extern struct memcons uv_memcons; #define INMEM_CON_IN_LEN 16 #define INMEM_CON_OUT_LEN (INMEM_CON_LEN - INMEM_CON_IN_LEN) +#define INMEM_UV_CON_IN_LEN 16 +#define INMEM_UV_CON_OUT_LEN (INMEM_UV_CON_LEN - INMEM_UV_CON_IN_LEN) /* Console driver */ struct con_ops { diff --git a/include/debug_descriptor.h b/include/debug_descriptor.h index cbe9293e..949e3d92 100644 --- a/include/debug_descriptor.h +++ b/include/debug_descriptor.h @@ -20,6 +20,7 @@ struct debug_descriptor { /* Memory console */ __be64 memcons_phys; + __be64 uv_memcons_phys; __be32 memcons_tce; __be32 memcons_obuf_tce; __be32 memcons_ibuf_tce; diff --git a/include/mem-map.h b/include/mem-map.h index 8ac11e91..3686b92c 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -91,16 +91,20 @@ #define INMEM_CON_START (SKIBOOT_BASE + 0x01000000) #define INMEM_CON_LEN 0x100000 -/* This is the location of HBRT console buffer at base + 17M */ -#define HBRT_CON_START (SKIBOOT_BASE + 0x01100000) +/* This is the location of our ultravisor console buffer at base + 17M */ +#define INMEM_UV_CON_START (SKIBOOT_BASE + 0x01100000) +#define INMEM_UV_CON_LEN 0x100000 + +/* This is the location of HBRT console buffer at base + 18M */ +#define HBRT_CON_START (SKIBOOT_BASE + 0x01200000) #define HBRT_CON_LEN 0x100000 -/* Tell FSP to put the init data at base + 20M, allocate 8M */ -#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000) +/* Tell FSP to put the init data at base + 19M, allocate 8M */ +#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01300000) #define SPIRA_HEAP_SIZE 0x00800000 /* This is our PSI TCE table. It's 256K entries on P8 */ -#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) +#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01c00000) #define PSI_TCE_TABLE_SIZE 0x00200000UL /* This is our dump result table after MPIPL. Hostboot will write to this @@ -119,7 +123,7 @@ * * (Ensure this has at least a 64k alignment) */ -#define SKIBOOT_SIZE 0x01c10000 +#define SKIBOOT_SIZE 0x01e00000 /* We start laying out the CPU stacks from here, indexed by PIR * each stack is STACK_SIZE in size (naturally aligned power of From patchwork Thu Feb 27 12:20:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SssC17pKz9sP7 for ; Thu, 27 Feb 2020 23:47:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48SssB71KZzDqsx for ; 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Thu, 27 Feb 2020 12:22:26 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 70A036A051; Thu, 27 Feb 2020 12:22:26 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 852486A05A; Thu, 27 Feb 2020 12:22:25 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:22:25 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:33 -0500 Message-Id: <20200227122042.32692-8-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 mlxlogscore=833 adultscore=0 bulkscore=0 mlxscore=0 suspectscore=1 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 07/16] Add ultra call support for skiboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan A new type of system call called the ultra call is used to get the services of the ultravisor. This ultracall support is needed in skiboot to access the xscoms which are in the secure memory area. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ andmike: ABI change to switch from r0 to r3 ] Signed-off-by: Michael Anderson --- asm/misc.S | 27 +++++++++++++++++++++++++++ include/ultravisor.h | 1 + 2 files changed, 28 insertions(+) diff --git a/asm/misc.S b/asm/misc.S index 9d2f3b6e..8dca77b0 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -316,3 +316,30 @@ exit_uv_mode: mflr %r4 mtspr SPR_USRR0,%r4 urfid + +.global ucall +ucall: + mflr %r0 + stdu %r1,-STACK_FRAMESIZE(%r1) + std %r0,STACK_LR(%r1) + mfcr %r0 + stw %r0,STACK_CR(%r1) + std %r4,STACK_GPR4(%r1) /* Save ret buffer */ + mr %r4,%r5 + mr %r5,%r6 + mr %r6,%r7 + mr %r7,%r8 + mr %r8,%r9 + mr %r9,%r10 + sc 2 /* invoke the ultravisor */ + ld %r12,STACK_GPR4(%r1) + std %r4, 0(%r12) + std %r5, 8(%r12) + std %r6, 16(%r12) + std %r7, 24(%r12) + lwz %r0,STACK_CR(%r1) + mtcrf 0xff,%r0 + ld %r0,STACK_LR(%r1) + mtlr %r0 + addi %r1,%r1,STACK_FRAMESIZE + blr /* return r3 = status */ diff --git a/include/ultravisor.h b/include/ultravisor.h index 44cf36bf..148041a0 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -9,6 +9,7 @@ #define UV_LOAD_MAX_SIZE 0x200000 +extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); extern int start_uv(uint64_t entry, void *fdt); int start_ultravisor(void *fdt); From patchwork Thu Feb 27 12:20:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245835 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Sssy4hkRz9sP7 for ; Thu, 27 Feb 2020 23:48:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48Sssy3KXxzDqyP for ; Thu, 27 Feb 2020 23:48:38 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 27 Feb 2020 12:22:53 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D2DA6A047; Thu, 27 Feb 2020 12:22:52 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:22:52 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:34 -0500 Message-Id: <20200227122042.32692-9-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=1 mlxscore=0 bulkscore=0 phishscore=0 mlxlogscore=796 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 08/16] xscoms: read/write xscoms using ucall X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan xscom registers are in the secure memory area when secure mode is enabled. These registers cannot be accessed directly and need to use ultravisor services using ultracall. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ linuxram: Set uv_present just after starting UV ] Signed-off-by: Ram Pai [ grimm: Don't check MSR in xscom read/write ] Signed-off-by: Ryan Grimm --- hw/ultravisor.c | 3 +++ include/ultravisor.h | 23 +++++++++++++++++++++++ include/xscom.h | 5 +++++ 3 files changed, 31 insertions(+) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index a2fe63cc..52b43e25 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -13,6 +13,7 @@ static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; +bool uv_present = false; struct memcons uv_memcons __section(".data.memcons") = { .magic = MEMCONS_MAGIC, @@ -58,6 +59,8 @@ int start_ultravisor(void *fdt) cpu_start_ultravisor(fdt); + uv_present = true; + while (i > 0) cpu_wait_job(jobs[--i], true); diff --git a/include/ultravisor.h b/include/ultravisor.h index 148041a0..0d4d4939 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -6,13 +6,36 @@ #include #include +#include #define UV_LOAD_MAX_SIZE 0x200000 +#define UCALL_BUFSIZE 4 +#define UV_READ_SCOM 0xF114 +#define UV_WRITE_SCOM 0xF118 + extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); extern int start_uv(uint64_t entry, void *fdt); +extern bool uv_present; int start_ultravisor(void *fdt); void init_uv(void); +static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + long rc; + + rc = ucall(UV_READ_SCOM, retbuf, partid, pcb_addr); + *val = retbuf[0]; + return rc; +} + +static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + + return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); +} + #endif /* __ULTRAVISOR_H */ diff --git a/include/xscom.h b/include/xscom.h index 8a466d56..2346db64 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * SCOM "partID" definitions: @@ -174,9 +175,13 @@ extern void _xscom_unlock(void); /* Targeted SCOM access */ static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val) { + if (uv_present) + return uv_xscom_read(partid, pcb_addr, val); return _xscom_read(partid, pcb_addr, val, true); } static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) { + if (uv_present) + return uv_xscom_write(partid, pcb_addr, val); return _xscom_write(partid, pcb_addr, val, true); } extern int xscom_write_mask(uint32_t partid, uint64_t pcb_addr, uint64_t val, uint64_t mask); From patchwork Thu Feb 27 12:20:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SstM4FBKz9sP7 for ; Thu, 27 Feb 2020 23:48:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48SstM27CJzDr3b for ; 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Thu, 27 Feb 2020 12:23:02 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B83A56A05D; Thu, 27 Feb 2020 12:23:02 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C76C76A051; Thu, 27 Feb 2020 12:23:01 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:01 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:35 -0500 Message-Id: <20200227122042.32692-10-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=1 mlxlogscore=999 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 09/16] hdata/memory.c: Parse HDAT for secure memory X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The secure memory ranges are provided by the hostboot through HDAT. Skiboot parses HDAT and creates secure-memory@ device tree nodes. Check bit 15 when checking for reserves that are too big so we reserve regions from HB that are in secure memory. Signed-off-by: Ryan Grimm --- hdata/memory.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index 9c588ff6..c25bd9c0 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -32,7 +32,7 @@ struct HDIF_ms_area_address_range { __be64 start; __be64 end; __be32 chip; - __be32 mirror_attr; + __be32 memory_attr; __be64 mirror_start; __be32 controller_id; __be32 phys_attr; @@ -59,6 +59,9 @@ struct HDIF_ms_area_address_range { #define MS_CONTROLLER_MCS_ID(id) GETFIELD(PPC_BITMASK32(4, 7), id) #define MS_CONTROLLER_MCA_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) +#define MS_ATTR_PEF PPC_BIT32(23) +#define UV_SECURE_MEM_BIT PPC_BIT(15) + struct HDIF_ms_area_id { __be16 id; #define MS_PTYPE_RISER_CARD 0x8000 @@ -129,10 +132,10 @@ static bool add_address_range(struct dt_node *root, chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); prlog(PR_DEBUG, " Range: 0x%016llx..0x%016llx " - "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", + "on Chip 0x%x memattr: 0x%08x pattr: 0x%x status:0x%x\n", (long long)be64_to_cpu(arange->start), (long long)be64_to_cpu(arange->end), - chip_id, be32_to_cpu(arange->mirror_attr), + chip_id, be32_to_cpu(arange->memory_attr), mem_type, mem_status); /* reg contains start and length */ @@ -161,6 +164,13 @@ static bool add_address_range(struct dt_node *root, return false; } + if (be32_to_cpu(arange->memory_attr) & MS_ATTR_PEF) { + prlog(PR_DEBUG, "HDAT: Found secure memory\n"); + name = "secure-memory"; + dev_type = "secure-memory"; + compat = "ibm,secure-memory"; + } + if (be16_to_cpu(id->flags) & MS_AREA_SHARED) { mem = dt_find_by_name_addr(dt_root, name, reg[0]); if (mem) { @@ -674,9 +684,10 @@ static void get_hb_reserved_mem(struct HDIF_common_hdr *ms_vpd) /* * Workaround broken HDAT reserve regions which are - * bigger than 512MB + * bigger than 512MB and not secure memory */ - if ((end_addr - start_addr) > 0x20000000) { + if (((end_addr - start_addr) > 0x20000000) && + !(start_addr & UV_SECURE_MEM_BIT)) { prlog(PR_ERR, "MEM: Ignoring Bad HDAT reserve: too big\n"); continue; } From patchwork Thu Feb 27 12:20:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SsvY3F85z9sRQ for ; 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Thu, 27 Feb 2020 12:23:10 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCN8Fs54329718 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:23:08 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A92D96A057; Thu, 27 Feb 2020 12:23:08 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AF1116A05D; Thu, 27 Feb 2020 12:23:07 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:07 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:36 -0500 Message-Id: <20200227122042.32692-11-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 mlxscore=0 suspectscore=1 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 10/16] hdata/spira.c: Create ibm, ultravisor dt node X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Create ibm,ultravisor node if secure memory exists. See doc/opal-uv-abi.rst for details. Signed-off-by: Ryan Grimm --- hdata/spira.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/hdata/spira.c b/hdata/spira.c index 7c5918d2..1435d175 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1712,6 +1712,36 @@ static void update_spirah_addr(void) #endif } +#define UV_LOAD_MAX_SIZE 0x200000 + +static void add_uv(void) +{ + struct dt_node *uv_node, *secure_mem_node, *uv_fw_node; + uint64_t uv_fw_start; + char fw_name[64]; + + secure_mem_node = dt_find_compatible_node_on_chip(dt_root, NULL, + "ibm,secure-memory", 0); + if (!secure_mem_node) { + prlog(PR_DEBUG, "HDAT: No ibm,secure-memory found\n"); + return; + } + + uv_node = dt_new_check(dt_root, "ibm,ultravisor"); + dt_add_property_string(uv_node, "compatible", "ibm,ultravisor"); + dt_add_property_cells(uv_node, "#address-cells", 2); + dt_add_property_cells(uv_node, "#size-cells", 2); + + uv_fw_start = dt_get_address(secure_mem_node, 0, NULL); + + snprintf(fw_name, 64, "firmware@%llx", (unsigned long long)uv_fw_start); + uv_fw_node = dt_new_check(uv_node, fw_name); + dt_add_property_string(uv_fw_node, "compatible", "ibm,uv-firmware"); + dt_add_property_cells(uv_fw_node, "reg", uv_fw_start >> 32, + uv_fw_start & 0xffffffff, UV_LOAD_MAX_SIZE >> 23, + UV_LOAD_MAX_SIZE & 0xffffffff); +} + int parse_hdat(bool is_opal) { cpu_type = PVR_TYPE(mfspr(SPR_PVR)); @@ -1753,6 +1783,9 @@ int parse_hdat(bool is_opal) /* Parse MS VPD */ memory_parse(); + /* Add UV node if secure memory exists */ + add_uv(); + /* Add any FSPs */ fsp_parse(); From patchwork Thu Feb 27 12:20:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Ssth3YZtz9sRQ for ; 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Thu, 27 Feb 2020 12:23:18 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCNGbZ59179380 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:23:16 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 068FB6A04D; Thu, 27 Feb 2020 12:23:16 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 10C3A6A047; Thu, 27 Feb 2020 12:23:15 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:14 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:37 -0500 Message-Id: <20200227122042.32692-12-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 mlxlogscore=914 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=3 phishscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 11/16] core/mem_region.c: Implement local free X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Ryan Grimm --- core/mem_region.c | 32 ++++++++++++++++++++++++++++++++ include/mem_region-malloc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/core/mem_region.c b/core/mem_region.c index eb48a1a1..6fe315bd 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -906,6 +906,38 @@ restart: return p; } +void __local_free(void *p, const char *location) +{ + struct mem_region *region; + struct alloc_hdr *hdr; + + if (!p) + return; + + lock(&mem_region_lock); + + list_for_each(®ions, region, list) { + /* local_alloc doesn't use heap */ + if (region == &skiboot_heap) + continue; + + if (p >= region_start(region) && + (p < (region_start(region) + region->len))) { + hdr = p - sizeof(*hdr); + + if (hdr->free) + bad_header(region, hdr, "re-freed", location); + + lock(®ion->free_list_lock); + make_free(region, (struct free_hdr *)hdr, location, false); + unlock(®ion->free_list_lock); + } + + } + + unlock(&mem_region_lock); +} + struct mem_region *find_mem_region(const char *name) { struct mem_region *region; diff --git a/include/mem_region-malloc.h b/include/mem_region-malloc.h index 4350c564..c1a6b886 100644 --- a/include/mem_region-malloc.h +++ b/include/mem_region-malloc.h @@ -28,4 +28,7 @@ void *__local_alloc(unsigned int chip, size_t size, size_t align, #define local_alloc(chip_id, size, align) \ __local_alloc((chip_id), (size), (align), __location__) +void __local_free(void *ptr, const char *location); +#define local_free(ptr) __local_free(ptr, __location__); + #endif /* __MEM_REGION_MALLOC_H */ From patchwork Thu Feb 27 12:20:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Ssv21QLWz9sP7 for ; Thu, 27 Feb 2020 23:49:34 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48Ssv14nYqzDr40 for ; Thu, 27 Feb 2020 23:49:33 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 27 Feb 2020 12:23:22 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B39636A047; Thu, 27 Feb 2020 12:23:21 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:21 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:38 -0500 Message-Id: <20200227122042.32692-13-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=3 mlxlogscore=999 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 12/16] Load the ultravisor from flash and decompress X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The ultravisor, labeled UVISOR is preloaded from the PNOR in main_cpu_entry after the kernel is preloaded. This also works on FSP-based systems with an ultra.lid on the FSP. Skiboot decompresses it laster in init_uv. Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- core/flash.c | 1 + core/init.c | 1 + hw/fsp/fsp.c | 2 + hw/ultravisor.c | 102 ++++++++++++++++++++++++++++++++++++++----- include/platform.h | 1 + include/ultravisor.h | 4 +- 6 files changed, 100 insertions(+), 11 deletions(-) diff --git a/core/flash.c b/core/flash.c index de748641..bc44a4e5 100644 --- a/core/flash.c +++ b/core/flash.c @@ -45,6 +45,7 @@ static struct { { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, "ROOTFS" }, { RESOURCE_ID_CAPP, RESOURCE_SUBID_SUPPORTED, "CAPP" }, { RESOURCE_ID_IMA_CATALOG, RESOURCE_SUBID_SUPPORTED, "IMA_CATALOG" }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, "UVISOR" }, { RESOURCE_ID_VERSION, RESOURCE_SUBID_NONE, "VERSION" }, { RESOURCE_ID_KERNEL_FW, RESOURCE_SUBID_NONE, "BOOTKERNFW" }, }; diff --git a/core/init.c b/core/init.c index f124f893..1300ab03 100644 --- a/core/init.c +++ b/core/init.c @@ -1300,6 +1300,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) preload_capp_ucode(); start_preload_kernel(); + uv_preload_image(); /* Catalog decompression routine */ imc_decompress_catalog(); diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 7592ee07..0411f035 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -114,6 +114,7 @@ static u64 fsp_hir_timeout; #define KERNEL_LID_PHYP 0x80a00701 #define KERNEL_LID_OPAL 0x80f00101 #define INITRAMFS_LID_OPAL 0x80f00102 +#define ULTRA_LID_OPAL 0x80f00105 /* * We keep track on last logged values for some things to print only on @@ -2372,6 +2373,7 @@ static struct { } fsp_lid_map[] = { { RESOURCE_ID_KERNEL, RESOURCE_SUBID_NONE, KERNEL_LID_OPAL }, { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, INITRAMFS_LID_OPAL }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, ULTRA_LID_OPAL }, { RESOURCE_ID_IMA_CATALOG,IMA_CATALOG_NIMBUS, 0x80f00103 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD20, 0x80a02002 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD21, 0x80a02001 }, diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 52b43e25..650466e8 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -10,11 +10,16 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; bool uv_present = false; +static char *uv_image = NULL; +static size_t uv_image_size; + struct memcons uv_memcons __section(".data.memcons") = { .magic = MEMCONS_MAGIC, .obuf_phys = INMEM_UV_CON_START, @@ -69,9 +74,51 @@ int start_ultravisor(void *fdt) return OPAL_SUCCESS; } +static int uv_decompress_image(void) +{ + struct xz_decompress *uv_xz; + uint64_t uv_fw_size; + + if (!uv_image) { + prerror("UV: Preload hasn't started yet! Aborting.\n"); + return OPAL_INTERNAL_ERROR; + } + + if (wait_for_resource_loaded(RESOURCE_ID_UV_IMAGE, + RESOURCE_SUBID_NONE) != OPAL_SUCCESS) { + prerror("UV: Ultravisor image load failed\n"); + return OPAL_INTERNAL_ERROR; + } + + uv_xz = malloc(sizeof(struct xz_decompress)); + if (!uv_xz) { + prerror("UV: Cannot allocate memory for decompression of UV\n"); + return OPAL_NO_MEM; + } + + uv_xz->dst = (void *)dt_get_address(uv_fw_node, 0, &uv_fw_size); + uv_xz->dst_size = uv_fw_size; + uv_xz->src_size = uv_image_size; + uv_xz->src = uv_image; + + if (stb_is_container((void*)uv_xz->src, uv_xz->src_size)) + uv_xz->src = uv_xz->src + SECURE_BOOT_HEADERS_SIZE; + + xz_start_decompress(uv_xz); + if ((uv_xz->status != OPAL_PARTIAL) && (uv_xz->status != OPAL_SUCCESS)) { + prerror("UV: XZ decompression failed status 0x%x\n", uv_xz->status); + free(uv_xz); + return OPAL_INTERNAL_ERROR; + } + + free(uv_xz); + return OPAL_SUCCESS; +} + void init_uv() { uint64_t uv_dt_src, uv_fw_sz; + int ret; if (!is_msr_bit_set(MSR_S)) { prlog(PR_DEBUG, "UV: S bit not set\n"); @@ -81,22 +128,57 @@ void init_uv() uv_fw_node = dt_find_compatible_node(dt_root, NULL, "ibm,uv-firmware"); if (!uv_fw_node) { prerror("UV: No ibm,uv-firmware node found\n"); - return; + goto err; } - if (!dt_find_property(uv_fw_node, "uv-src-address")) { - prerror("UV: No uv-src-address found\n"); - return; - } + ret = uv_decompress_image(); + if (ret) { + if (!dt_find_property(uv_fw_node, "uv-src-address")) { + prerror("UV: No uv-src-address found\n"); + goto err; + } - uv_dt_src = dt_prop_get_u64(uv_fw_node, "uv-src-address"); - uv_base_addr = dt_get_address(uv_fw_node, 0, &uv_fw_sz); + uv_dt_src = dt_prop_get_u64(uv_fw_node, "uv-src-address"); + uv_base_addr = dt_get_address(uv_fw_node, 0, &uv_fw_sz); - prlog(PR_INFO, "UV: Copying to protected memory 0x%llx from 0x%llx\n", - uv_base_addr, uv_dt_src); + prlog(PR_INFO, "UV: Copying to protected memory 0x%llx from 0x%llx\n", + uv_base_addr, uv_dt_src); - memcpy((void *)uv_base_addr, (void *)uv_dt_src, UV_LOAD_MAX_SIZE); + memcpy((void *)uv_base_addr, (void *)uv_dt_src, UV_LOAD_MAX_SIZE); + } dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; +err: + local_free(uv_image); +} + +/* + * Preload the UV image from PNOR partition + * + * uv_image is allocated locally to the chip and freed here if preload fails + * or free in init_uv + */ +void uv_preload_image(void) +{ + struct proc_chip *chip = next_chip(NULL); + int ret; + + prlog(PR_DEBUG, "UV: Preload starting\n"); + + uv_image_size = MAX_COMPRESSED_UV_IMAGE_SIZE; + uv_image = local_alloc(chip->id, uv_image_size, uv_image_size); + if (!uv_image) { + prerror("UV: Memory allocation failed\n"); + return; + } + memset(uv_image, 0, uv_image_size); + + ret = start_preload_resource(RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, + uv_image, &uv_image_size); + + if (ret != OPAL_SUCCESS) { + local_free(uv_image); + prerror("UV: platform load failed: %d\n", ret); + } } diff --git a/include/platform.h b/include/platform.h index 6ecdbe47..04491d6a 100644 --- a/include/platform.h +++ b/include/platform.h @@ -17,6 +17,7 @@ enum resource_id { RESOURCE_ID_INITRAMFS, RESOURCE_ID_CAPP, RESOURCE_ID_IMA_CATALOG, + RESOURCE_ID_UV_IMAGE, RESOURCE_ID_VERSION, RESOURCE_ID_KERNEL_FW, }; diff --git a/include/ultravisor.h b/include/ultravisor.h index 0d4d4939..26a986cd 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -8,7 +8,8 @@ #include #include -#define UV_LOAD_MAX_SIZE 0x200000 +#define MAX_COMPRESSED_UV_IMAGE_SIZE 0x40000 /* 256 Kilobytes */ +#define UV_LOAD_MAX_SIZE 0x200000 #define UCALL_BUFSIZE 4 #define UV_READ_SCOM 0xF114 @@ -19,6 +20,7 @@ extern int start_uv(uint64_t entry, void *fdt); extern bool uv_present; int start_ultravisor(void *fdt); +void uv_preload_image(void); void init_uv(void); static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) From patchwork Thu Feb 27 12:20:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Ssw11gfrz9sRQ for ; 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Thu, 27 Feb 2020 12:23:31 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01RCNSIQ50069764 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Feb 2020 12:23:29 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF5AA6A054; Thu, 27 Feb 2020 12:23:28 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E123D6A04F; Thu, 27 Feb 2020 12:23:27 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:27 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:39 -0500 Message-Id: <20200227122042.32692-14-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=1 mlxlogscore=999 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 13/16] skiboot/imc: Disable IMC node when UV enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan Remove the IMC nodes when the ultravisor is enabled, since both HOMER and IMC scoms are not accessable in hypervisor state. Signed-off-by: Madhavan Srinivasan --- hw/imc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/imc.c b/hw/imc.c index 3a5382c0..576eac87 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -603,6 +603,17 @@ imc_mambo: if (pause_microcode_at_boot()) goto err; + /* + * If MSR(S) bit is set, disable IMC nodes. + * IMC nodes need access to specific scom and HOMER region + * which are not accessible from hypervisor. + * + * At this point uv_present cant be used since uv_init() + * is called much later. Hencing checking for the MSR bit here. + */ + if (is_msr_bit_set(MSR_S)) + goto err; + /* * If the dt_attach_root() fails, "imc-counters" node will not be * seen in the device-tree and hence OS should not make any From patchwork Thu Feb 27 12:20:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245841 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Sswh6781z9sP7 for ; Thu, 27 Feb 2020 23:51:00 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48Sswh192fzDr4Y for ; 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Thu, 27 Feb 2020 12:23:33 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6744F6A04F; Thu, 27 Feb 2020 12:23:33 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7182C6A047; Thu, 27 Feb 2020 12:23:32 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:32 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:40 -0500 Message-Id: <20200227122042.32692-15-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=3 bulkscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 malwarescore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 14/16] Add an ultravisor device tree in secure memory X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch adds a UV FDT created in secure memory. It is allocated directly after the ultravisor. The UV FDT will contain information like the wrapping key. The code uses libfdt directly to ensure only secure memory is used. Signed-off-by: Ryan Grimm Signed-off-by: Ram Pai --- hw/ultravisor.c | 27 ++++++++++++++++++++++++++- include/ultravisor.h | 1 + 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 650466e8..1467a1e5 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -12,6 +12,7 @@ #include #include #include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; @@ -115,9 +116,27 @@ static int uv_decompress_image(void) return OPAL_SUCCESS; } +static int create_dtb_uv(void *uv_fdt) +{ + if (fdt_create(uv_fdt, UV_FDT_MAX_SIZE)) { + prerror("UV: Failed to create uv_fdt\n"); + return OPAL_NO_MEM; + } + + fdt_finish_reservemap(uv_fdt); + fdt_begin_node(uv_fdt, ""); + fdt_property_string(uv_fdt, "description", "Ultravisor fdt"); + fdt_begin_node(uv_fdt, "ibm,uv-fdt"); + fdt_property_string(uv_fdt, "compatible", "ibm,uv-fdt"); + fdt_end_node(uv_fdt); + fdt_finish(uv_fdt); + + return OPAL_SUCCESS; +} + void init_uv() { - uint64_t uv_dt_src, uv_fw_sz; + uint64_t uv_dt_src, uv_fw_sz, uv_fdt_addr; int ret; if (!is_msr_bit_set(MSR_S)) { @@ -131,6 +150,8 @@ void init_uv() goto err; } + uv_base_addr = dt_get_address(uv_fw_node, 0, &uv_fw_sz); + ret = uv_decompress_image(); if (ret) { if (!dt_find_property(uv_fw_node, "uv-src-address")) { @@ -149,6 +170,10 @@ void init_uv() dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; + + uv_fdt_addr = uv_base_addr + UV_LOAD_MAX_SIZE; + create_dtb_uv((void *)uv_fdt_addr); + dt_add_property_u64(uv_fw_node, "uv-fdt", uv_fdt_addr); err: local_free(uv_image); } diff --git a/include/ultravisor.h b/include/ultravisor.h index 26a986cd..347b085d 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -14,6 +14,7 @@ #define UCALL_BUFSIZE 4 #define UV_READ_SCOM 0xF114 #define UV_WRITE_SCOM 0xF118 +#define UV_FDT_MAX_SIZE 0x100000 extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); extern int start_uv(uint64_t entry, void *fdt); From patchwork Thu Feb 27 12:20:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48SsxJ3FvMz9sP7 for ; Thu, 27 Feb 2020 23:51:32 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48SsxJ14MlzDr5l for ; Thu, 27 Feb 2020 23:51:32 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 27 Feb 2020 12:23:39 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 331AA6A051; Thu, 27 Feb 2020 12:23:38 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:38 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:41 -0500 Message-Id: <20200227122042.32692-16-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=1 bulkscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 malwarescore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 15/16] ultravisor: Pickup wraping key data from mambo X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Michael Anderson Signed-off-by: Michael Anderson --- external/mambo/skiboot.tcl | 77 ++++++++++++++++++++++++++++++++++++++ include/ultravisor.h | 2 + platforms/mambo/uv.c | 39 +++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 platforms/mambo/uv.c diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl index f6e0ee9e..b4bf75c2 100644 --- a/external/mambo/skiboot.tcl +++ b/external/mambo/skiboot.tcl @@ -95,6 +95,9 @@ mconfig net_mac MAMBO_NET_MAC 00:11:22:33:44:55 # Net: What is the name of the tap device mconfig net_tapdev MAMBO_NET_TAPDEV "tap0" +# TPM Wrapping Directory for key files +mconfig wrapkey_dir WRAPKEY_DIR none + # Enable (default) or disable the "speculation-policy-favor-security" setting, # set to 0 to disable. When enabled it causes Linux's RFI flush to be enabled. mconfig speculation_policy_favor_security MAMBO_SPECULATION_POLICY_FAVOR_SECURITY 1 @@ -333,6 +336,80 @@ foreach pmem_size $pmem_sizes { # PMEM_VOLATILE set pmem_start [pmem_node_add $pmem_root $pmem_start $pmem_size] } +# +# Add files to simulate TPM wrapping keys. +# wrapping-key-policy-a +# wrapping-key-policy-b +# wrapping-key-passwd +# wrapping-key-publicname +# + +proc add_key_prop { k_file node p_name } { + set key_list [list] + set f [open $k_file r] + + while {1} { + set key_byte [read $f 2] + if {[eof $f]} { + close $f + break + } + lappend key_list $key_byte + } + + mysim of addprop $node byte_array $p_name $key_list +} + +if { $mconf(wrapkey_dir) != "none" } { + set tpm_node [ mysim of addchild $root_node "tpm_sim" "" ] + mysim of addprop $tpm_node string "compatible" "uv,tpm_sim" + + # policy-a.txt + if {[file exists $mconf(wrapkey_dir)/policy-a.txt]} { + puts "Using policy-a.txt" + add_key_prop $mconf(wrapkey_dir)/policy-a.txt $tpm_node "wrapping-key-policy-a" + } else { + puts "ERROR: Could not find policy-a.txt in : $mconf(wrapkey_dir)" + exit + } + + # policy-b.txt + if {[file exists $mconf(wrapkey_dir)/policy-b.txt]} { + puts "Using policy-b.txt" + add_key_prop $mconf(wrapkey_dir)/policy-b.txt $tpm_node "wrapping-key-policy-b" + } else { + puts "ERROR: Could not find policy-b.txt in : $mconf(wrapkey_dir)" + exit + } + + # wrapping-key-passwd + if {[file exists $mconf(wrapkey_dir)/wrapping-key-passwd.txt]} { + puts "Using wrapping-key-passwd.txt" + add_key_prop $mconf(wrapkey_dir)/wrapping-key-passwd.txt $tpm_node "wrapping-key-passwd" + } else { + puts "ERROR: Could not find wrapping-key-passwd.txt in : $mconf(wrapkey_dir)" + exit + } + + # wrapping-key-publicname + if {[file exists $mconf(wrapkey_dir)/wrapping-key-publicname.txt]} { + puts "Using wrapping-key-publicname.txt" + add_key_prop $mconf(wrapkey_dir)/wrapping-key-publicname.txt $tpm_node "wrapping-key-publicname" + } else { + puts "ERROR: Could not find wrapping-key-publicname.txt in : $mconf(wrapkey_dir)" + exit + } + + # wrapping-key-handle + if {[file exists $mconf(wrapkey_dir)/wrapping-key-handle.txt]} { + puts "Using wrapping-key-handle.txt" + add_key_prop $mconf(wrapkey_dir)/wrapping-key-handle.txt $tpm_node "wrapping-key-handle" + } else { + puts "ERROR: Could not find wrapping-key-handle.txt in : $mconf(wrapkey_dir)" + exit + } + +} # Default NVRAM is blank and will be formatted by Skiboot if no file is provided set fake_nvram_start $cpio_end diff --git a/include/ultravisor.h b/include/ultravisor.h index 347b085d..faa1d16b 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -24,6 +24,8 @@ int start_ultravisor(void *fdt); void uv_preload_image(void); void init_uv(void); +int add_wrapping_key_mambo(void *fdt); + static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) { unsigned long retbuf[UCALL_BUFSIZE]; diff --git a/platforms/mambo/uv.c b/platforms/mambo/uv.c new file mode 100644 index 00000000..2519d240 --- /dev/null +++ b/platforms/mambo/uv.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2016-2017 IBM Corp. */ + +const char *wrap_key_prop_str[] = { + "wrapping-key-passwd", + "wrapping-key-publicname", + "wrapping-key-policy-a", + "wrapping-key-policy-b", + NULL +}; + +int add_wrapping_key_mambo(void *fdt) +{ + struct dt_node *tpm_sim_node; + const struct dt_property *property = NULL; + int i; + + tpm_sim_node = dt_find_compatible_node(dt_root, NULL, "uv,tpm_sim"); + if (!tpm_sim_node) { + prlog(PR_INFO, "uv,tpm_sim compatible node not found\n"); + return OPAL_HARDWARE; + } + + fdt_begin_node(fdt, "ibm,uv-tpm"); + fdt_property_string(fdt, "compatible", "ibm,uv-tpm"); + + for (i = 0; wrap_key_prop_str[i] != NULL; i++) { + property = dt_find_property(tpm_sim_node, wrap_key_prop_str[i]); + if (property) { + fdt_property(fdt, wrap_key_prop_str[i], + property->prop, + property->len); + } + } + + fdt_end_node(fdt); + + return OPAL_SUCCESS; +} From patchwork Thu Feb 27 12:20:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1245843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48Ssxh4QVkz9sP7 for ; Thu, 27 Feb 2020 23:51:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48Ssxh1NxwzDr0m for ; Thu, 27 Feb 2020 23:51:52 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48SsKJ4xZDzDqrq for ; Thu, 27 Feb 2020 23:23:48 +1100 (AEDT) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01RCKMf6093319 for ; Thu, 27 Feb 2020 07:23:45 -0500 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ydqfvvuf5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; 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Thu, 27 Feb 2020 12:23:42 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F35956A051; Thu, 27 Feb 2020 12:23:41 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 001706A047; Thu, 27 Feb 2020 12:23:40 +0000 (GMT) Received: from alain.ibm.com (unknown [9.80.218.175]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 27 Feb 2020 12:23:40 +0000 (GMT) From: Ryan Grimm To: oohall@gmail.com Date: Thu, 27 Feb 2020 07:20:42 -0500 Message-Id: <20200227122042.32692-17-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200227122042.32692-1-grimm@linux.ibm.com> References: <20200227122042.32692-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-27_03:2020-02-26, 2020-02-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=1 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=973 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002270100 Subject: [Skiboot] [RFC PATCH v4 16/16] libstb/trustedboot: Map UV image measurement to PCR4 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, suka@us.ibm.com, skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Claudio Carvalho This maps the ultravisor image to be measured to PCR4. The image is automatically verified and measured hen it is loaded from PNOR. Signed-off-by: Claudio Carvalho --- libstb/trustedboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/libstb/trustedboot.c b/libstb/trustedboot.c index 3f977de1..87f3b6bf 100644 --- a/libstb/trustedboot.c +++ b/libstb/trustedboot.c @@ -45,6 +45,7 @@ static struct { { RESOURCE_ID_KERNEL, PCR_4}, { RESOURCE_ID_CAPP, PCR_4}, { RESOURCE_ID_VERSION, PCR_4}, /* Also data for Hostboot */ + { RESOURCE_ID_UV_IMAGE, PCR_4}, }; /*