From patchwork Wed Nov 29 22:21:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Makarov X-Patchwork-Id: 842785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-468177-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Ke0ruNft"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ynFPW4Dyhz9sDB for ; Thu, 30 Nov 2017 09:21:35 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; q=dns; s= default; b=m/PX4c8HSU9c9u6bD4T47Y+F0h/391egNS6ItROTg6bXEFQSwmGyl lDGO3X1oVzrkwdsajDABqF+oti61IodPs9s9NkstvfcpC7mZT+7Mg7mArguYoXby cqAJE7vTSmX29mvewo0kokhLNLyyR5fdqKEo8QefROVFnIYvlTyPjc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; s= default; bh=XX29jKEmx1JjhodRkQS4BYQsiPc=; b=Ke0ruNft2uMqX1LUUbbH ezj8T5NbXbfLzrqGoBgM518YMLRS6g6jbE6+ofFALh9sfXNhoErSrM3mLX1sD7GA MwD0+XeIOGy20TeukqYpU7kWOCRc9/6U2Rkx6oN0EpqVfSPTxjqcvT/Gryq9QI9c QvZ0ykFOK4ItQFD6J/oa0x4= Received: (qmail 59726 invoked by alias); 29 Nov 2017 22:21:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59693 invoked by uid 89); 29 Nov 2017 22:21:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.4 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, KAM_SHORT, KB_WAM_FROM_NAME_SINGLEWORD, SPF_HELO_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Nov 2017 22:21:24 +0000 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7AB41C058ED2 for ; Wed, 29 Nov 2017 22:21:23 +0000 (UTC) Received: from [10.10.121.35] (ovpn-121-35.rdu2.redhat.com [10.10.121.35]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1048160F80 for ; Wed, 29 Nov 2017 22:21:22 +0000 (UTC) From: Vladimir Makarov Subject: patch to fix PR80818 To: "gcc-patches@gcc.gnu.org" Message-ID: Date: Wed, 29 Nov 2017 17:21:22 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 X-IsSubscribed: yes The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80818 The patch was successfully tested and bootstrapped on x86_64. The patch has no test because it is hard to check the problem. I checked manually that the patch solves the problem on a test provided by Andreas Krebbel. Committed as rev. 255258. Index: ChangeLog =================================================================== --- ChangeLog (revision 255255) +++ ChangeLog (working copy) @@ -1,3 +1,15 @@ +2017-11-29 Vladimir Makarov + + PR rtl-optimization/80818 + * lra.c (collect_non_operand_hard_regs): New arg insn. Pass it + recursively. Use insn code for clobber. + (lra_set_insn_recog_data): Pass the new arg to + collect_non_operand_hard_regs. + (add_regs_to_insn_regno_info): Pass insn instead of uid. Use insn + code for clobber. + (lra_update_insn_regno_info): Pass insn to + add_regs_to_insn_regno_info. + 2017-11-29 Julia Koval * config/i386/avx512vbmi2intrin.h (_mm512_shldv_epi16, Index: lra.c =================================================================== --- lra.c (revision 255256) +++ lra.c (working copy) @@ -807,7 +807,8 @@ setup_operand_alternative (lra_insn_reco to LIST. X is a part of insn given by DATA. Return the result list. */ static struct lra_insn_reg * -collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, +collect_non_operand_hard_regs (rtx_insn *insn, rtx *x, + lra_insn_recog_data_t data, struct lra_insn_reg *list, enum op_type type, bool early_clobber) { @@ -881,25 +882,28 @@ collect_non_operand_hard_regs (rtx *x, l switch (code) { case SET: - list = collect_non_operand_hard_regs (&SET_DEST (op), data, + list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data, list, OP_OUT, false); - list = collect_non_operand_hard_regs (&SET_SRC (op), data, + list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data, list, OP_IN, false); break; case CLOBBER: - /* We treat clobber of non-operand hard registers as early - clobber (the behavior is expected from asm). */ - list = collect_non_operand_hard_regs (&XEXP (op, 0), data, - list, OP_OUT, true); - break; + { + int code = INSN_CODE (insn); + /* We treat clobber of non-operand hard registers as early + clobber (the behavior is expected from asm). */ + list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, + list, OP_OUT, code < 0); + break; + } case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: - list = collect_non_operand_hard_regs (&XEXP (op, 0), data, + list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, list, OP_INOUT, false); break; case PRE_MODIFY: case POST_MODIFY: - list = collect_non_operand_hard_regs (&XEXP (op, 0), data, + list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, list, OP_INOUT, false); - list = collect_non_operand_hard_regs (&XEXP (op, 1), data, + list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data, list, OP_IN, false); break; default: @@ -907,12 +911,12 @@ collect_non_operand_hard_regs (rtx *x, l for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) { if (fmt[i] == 'e') - list = collect_non_operand_hard_regs (&XEXP (op, i), data, + list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data, list, OP_IN, false); else if (fmt[i] == 'E') for (j = XVECLEN (op, i) - 1; j >= 0; j--) - list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, - list, OP_IN, false); + list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j), + data, list, OP_IN, false); } } return list; @@ -1055,7 +1059,7 @@ lra_set_insn_recog_data (rtx_insn *insn) insn_static_data->hard_regs = NULL; else insn_static_data->hard_regs - = collect_non_operand_hard_regs (&PATTERN (insn), data, + = collect_non_operand_hard_regs (insn, &PATTERN (insn), data, NULL, OP_IN, false); data->arg_hard_regs = NULL; if (CALL_P (insn)) @@ -1402,13 +1406,14 @@ lra_get_copy (int n) /* This page contains code dealing with info about registers in insns. */ -/* Process X of insn UID recursively and add info (operand type is +/* Process X of INSN recursively and add info (operand type is given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) about registers in X to the insn DATA. If X can be early clobbered, alternatives in which it can be early clobbered are given by EARLY_CLOBBER_ALTS. */ static void -add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, +add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, + rtx_insn *insn, enum op_type type, bool early_clobber, alternative_mask early_clobber_alts) { @@ -1436,7 +1441,7 @@ add_regs_to_insn_regno_info (lra_insn_re /* Process all regs even unallocatable ones as we need info about all regs for rematerialization pass. */ expand_reg_info (); - if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid)) + if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn))) { data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, early_clobber, early_clobber_alts, @@ -1471,20 +1476,25 @@ add_regs_to_insn_regno_info (lra_insn_re switch (code) { case SET: - add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false, 0); - add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false, 0); + add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, false, 0); + add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, false, 0); break; case CLOBBER: - /* We treat clobber of non-operand hard registers as early - clobber (the behavior is expected from asm). */ - add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true, ALL_ALTERNATIVES); - break; + { + int code = INSN_CODE (insn); + + /* We treat clobber of non-operand hard registers as early + clobber (the behavior is expected from asm). */ + add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT, + code < 0, code < 0 ? ALL_ALTERNATIVES : 0); + break; + } case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: - add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false, 0); + add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0); break; case PRE_MODIFY: case POST_MODIFY: - add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false, 0); - add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false, 0); + add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0); + add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, false, 0); break; default: if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) @@ -1505,11 +1515,11 @@ add_regs_to_insn_regno_info (lra_insn_re for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) { if (fmt[i] == 'e') - add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false, 0); + add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, false, 0); else if (fmt[i] == 'E') { for (j = XVECLEN (x, i) - 1; j >= 0; j--) - add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid, + add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn, type, false, 0); } } @@ -1585,7 +1595,7 @@ setup_insn_reg_info (lra_insn_recog_data void lra_update_insn_regno_info (rtx_insn *insn) { - int i, uid, freq; + int i, freq; lra_insn_recog_data_t data; struct lra_static_insn_data *static_data; enum rtx_code code; @@ -1597,14 +1607,13 @@ lra_update_insn_regno_info (rtx_insn *in static_data = data->insn_static_data; freq = get_insn_freq (insn); invalidate_insn_data_regno_info (data, insn, freq); - uid = INSN_UID (insn); for (i = static_data->n_operands - 1; i >= 0; i--) - add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid, + add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn, static_data->operand[i].type, static_data->operand[i].early_clobber, static_data->operand[i].early_clobber_alts); if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) - add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid, + add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn, code == USE ? OP_IN : OP_OUT, false, 0); if (CALL_P (insn)) /* On some targets call insns can refer to pseudos in memory in @@ -1616,7 +1625,7 @@ lra_update_insn_regno_info (rtx_insn *in link = XEXP (link, 1)) if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) && MEM_P (XEXP (XEXP (link, 0), 0))) - add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, + add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn, code == USE ? OP_IN : OP_OUT, false, 0); if (NONDEBUG_INSN_P (insn)) setup_insn_reg_info (data, freq);