From patchwork Wed Nov 29 12:39:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 842553 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="YGl9KzO/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yn0Tn30ZDz9t2V for ; Wed, 29 Nov 2017 23:39:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A2ADBC21F18; Wed, 29 Nov 2017 12:39:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 43350C21E31; Wed, 29 Nov 2017 12:39:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 97AAFC21DD9; Wed, 29 Nov 2017 12:39:12 +0000 (UTC) Received: from mail-wm0-f46.google.com (mail-wm0-f46.google.com [74.125.82.46]) by lists.denx.de (Postfix) with ESMTPS id 297B5C21E31 for ; Wed, 29 Nov 2017 12:39:12 +0000 (UTC) Received: by mail-wm0-f46.google.com with SMTP id 9so5927190wme.4 for ; Wed, 29 Nov 2017 04:39:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=reply-to:to:cc:from:subject:message-id:date:user-agent:mime-version; bh=7CzqbPNQOxy21clTIbDMq88DpKgVSRBZSnHA/S/dzig=; b=YGl9KzO/Z6D70ldYzqfX/vnuujaB/P6LMkOIa43JlU49uN5WjhjWekKxfBqgHHYIKo Fm2svwdgvIHD1bLq93zwCvO1b45hjLeBeF/BN5C3tsrc352VEkHOoBqBZsRIUKyv/1tM NyuoK2Y+7Binwkmh6x3X+Nr5ICljy6+Ek4ZT77rXJZ49OShfskzTZ+aqHCTAm6v2Y2Ru QqwS/CESaf3LhPgyXd3JlmL6RS6ZcEUwDqSHgUfp6zyx+rL6c902FF4W25aDhvv7lS22 91VJsXJUwIpkkS3JI5JJ2aXZDErOhjNmhxZbaTyCAq9bj0salDyZs2stwf2LXFtrUqcG bCGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:to:cc:from:subject:message-id:date :user-agent:mime-version; bh=7CzqbPNQOxy21clTIbDMq88DpKgVSRBZSnHA/S/dzig=; b=nHc+uPy0XBZdGpI3Xg8Ne/UPmIriWNPCVaOE/K8PQBxzoPSaSZHHkXG+yM1A9+m7Q/ FU5B3S6Vhqau3Zm7eflMxbUegSVy2ovNY8wVhQY8/KPpz/R1/aT6ErTlgvsIYuIA3AdH Uh+OWzQeRqgwh9BFOqCy99TF98B+EBtiYU/eduVhw2KBYGLbZB7GRKa2n+6kZZvwSBrD 4BoL9pEZLy1SrS/svssJ069zqgIhDvUyJ6odg85i+0qHfJ53YR4e6c6OI3d+8vW06Yr2 z1BUdbGkqTn4xN+78INjAesYs+5OdcgNgmXojGtTQd4n44ImcL/UTZsyvzPBi9tdJxKH j3Ow== X-Gm-Message-State: AJaThX4tBK4R89+q1KSsPw4IhpQ/3/mRNLwrYAk9RU3QQakb9p6Y0LLs WzenXFjHec2A+2V2Z9rscTgxEdP3 X-Google-Smtp-Source: AGs4zMaAGcUUHFje3j6CsiukXSjItIn00VpyW2WIz9MKHI4F1PE3pnLplcSEdsJHHIj4FM/pWNE9Eg== X-Received: by 10.28.142.193 with SMTP id q184mr2310683wmd.62.1511959151403; Wed, 29 Nov 2017 04:39:11 -0800 (PST) Received: from [64.233.184.108] ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id f19sm831831wrh.64.2017.11.29.04.39.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Nov 2017 04:39:10 -0800 (PST) To: Tom Rini From: Michal Simek Message-ID: Date: Wed, 29 Nov 2017 13:39:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Cc: "u-boot@lists.denx.de" Subject: [U-Boot] [GIT PULL] Xilinx changes for v2018.01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: monstr@monstr.eu Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi Tom, please pull these changes to your tree. Travis is not showing any issue https://travis-ci.org/michalsimek-test/u-boot/builds/308832565 Changes are described below. Thanks, Michal The following changes since commit 73a01d90c0b2ed2527283f289f73d69ef52cafa5: test: Correct operation when tests pass (2017-11-27 23:05:22 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.01 for you to fetch changes up to a04a5daae25a74ad2ac90b66667dac126242baa0: net: xilinx_axi_emac: Use readl and writel for io ops (2017-11-29 08:02:40 +0100) ---------------------------------------------------------------- Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support ---------------------------------------------------------------- Anurag Kumar Vulisha (6): arm64: zynqmp: Add SMMU support for SATA IP arm64: zynqmp: Add reset-controller support in serdes driver arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3 arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3 arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB Bharat Kumar Gogada (1): arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe Chirag Parekh (2): arm: zynq: Add SCL & SDA GPIO entries for recovery arm64: zynqmp: Update device tree for gpio Heinrich Schuchardt (1): arm64: zynqmp: remove unnecessary logical constraint Hyun Kwon (1): arm64: zynqmp: Update the GPU address size Jean-Francois Dagenais (1): tools: zynqmpimage: adjust ug1085 reference to v1.4 of the document Jeff Westfahl (1): mtd: nand: zynq: Add a config option to use 1st stage bootloader timing Joe Hershberger (1): mtd: nand: zynq: Add support for the NAND lock/unlock operation Jolly Shah (1): arm64: zynqmp: Reduced min-residency time for idle state node Jyotheeswar Reddy (1): arm64: zynqmp: DT: Fix typo in idle-states node definition Jyotheeswar Reddy Mutthareddyvari (1): arm64: zynqmp: PM: Specify power domains for DP related nodes Madhurkiran Harikrishnan (1): arm64: zynqmp: Add clock name for GPU Manish Narani (3): arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon arm64: zynqmp: Enabled CCI support for USB arm64: zynqmp: Add USB OTG interrupts support in dt Michal Simek (52): arm: zynq: Remove empty ifdef env structures from config file arm: zynq: Sync location of DT properties with Linux arm: zynq: Enable bootz command for Xilinx platforms arm: zynq: Enable debug console on zc770 xm010 by default arm: zynq: Enable MACRONIX flash for zc702/zc706/zc770 xm010 arm: zynq: Enable qspi for zc770_xm013 arm: zynq: Add board support for cc108 arm: zynq: Return value from fdtdec_setup_memory_banksize directly arm: zynq: Enable FPGA/FPGA_XILINX via Kconfig arm: zynq: Move ZYNQ_SERIAL to Kconfig arm: zynq: Sort dts names arm: zynq: Add mini u-boot configuration for zynq ata: Fix ahci wording arm64: zynqmp: Remove slcr with mio status pin detection tools: mkimage: Extend mkimage to also include pmufw arm64: zynqmp: Add SD1 level shifter mode to alternative selection arm64: zynqmp: Use u32 type instead of uint32_t arm64: zynqmp: Add support for CG/EG/EV device detection arm64: zynqmp: Add new ID for RFSoC arm64: zynqmp: Enable debug uart for zc1751 dc5 arm64: zynqmp: Wire QSPI boot mode for SPL arm64: zynqmp: Add references to cpu nodes arm64: zynqmp: Fix broken architected timer interrupt trigger arm64: zynqmp: Add missing gpio property to dtsi arm64: zynqmp: Use revision in dts file description arm64: zynqmp: Add revB string to compatible string arm64: zynqmp: Add missing alias for gem0 for ep108 arm64: zynqmp: Remove leading 0s from mtd table for spi flashes arm64: zynqmp: Use SPDX license with dc4 arm64: zynqmp: Remove local-mac-address from dtsi file arm64: zynqmp: Update device tree for pinmux arm64: zynqmp: Add support for zcu102 1.0 rev arm64: zynqmp: Remove tx_termination_fix detection on silicon v1 arm64: zynqmp: dt: Add AMS node arm64: zynqmp: Move nodes which have no reg property out of bus arm64: zynqmp: Remove clock setting from dtsi arm64: zynqmp: Add note about si5328 interrupt arm64: zynqmp: Add revision to identification string arm: zynq: Add missing ps7_post_config declaration arm: zynq: Enable debug uart on zc706 arm: zynq: Remove ps7_debug code arm: zynq: Move ps7_* to separate file arm: zynq: Get rid of ps7_reset_apu() for syzygy board arm: zynq: Move common ps7_init* initialization to arch code arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init arm: zynq: Add support for EMIT_WRITE operation arm: zynq: Convert all board to use arch ps7_init code arm: zynq: Use unsigned type with comparison with ARRAY_SIZE arm: zynq: Do not show information from checkboard twice arm: zynq: Show information about silicon version arm: zynq: Add ps7_init for cc108 arm: zynq: Change Zynq/ZynqMP Kconfig description Naga Sureshkumar Relli (1): arm64: zynqmp: disable smmu Nava kishore Manne (3): arm64: zynqmp: Label whole PL part as fpga_full region arm64: zynqmp: rtc: Add calibration arm64: zynqmp: Add support for zynqmp nvmem firmware driver Rob Herring (1): arm64: dts: xilinx: fix PCI bus dtc warnings Sai Pavan Boddu (1): arm: zynq: Add device-type property for zynq ethernet phy nodes Shubhrajyoti Datta (2): arm64: zynqmp: Update the OPPs for cpu freq arm64: zynqmp: Enable watchdog by default Siva Durga Prasad Paladugu (8): arm64: zynqmp: mp: Correct the R5 release sequence arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU table arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP defined net: xilinx_axi_emac: Use wait_for_bit instead of while loop net: xilinx_axi_emac: Read dma address using fdtdec_get_addr net: xilinx_axi_emac: Add support for non processor mode net: zynq_gem: Dont enable SGMII and PCS selection net: xilinx_axi_emac: Use readl and writel for io ops Soren Brinkmann (1): arm64: zynqmp: PM: Add IRQ Tom McLeod (1): arm: zynq: Add support for SYZYGY Hub board Wilson Lee (1): mtd: zynq: nand: Move board_nand_init() function to board.c arch/arm/Kconfig | 4 +- arch/arm/cpu/armv8/zynqmp/Kconfig | 20 ++++ arch/arm/cpu/armv8/zynqmp/Makefile | 1 - arch/arm/cpu/armv8/zynqmp/cpu.c | 16 ++- arch/arm/cpu/armv8/zynqmp/mp.c | 14 +++ arch/arm/cpu/armv8/zynqmp/slcr.c | 63 ----------- arch/arm/cpu/armv8/zynqmp/spl.c | 5 + arch/arm/dts/Makefile | 17 ++- arch/arm/dts/zynq-7000.dtsi | 2 +- arch/arm/dts/zynq-cc108.dts | 116 +++++++++++++++++++ arch/arm/dts/zynq-cse-qspi-single.dts | 13 +++ arch/arm/dts/zynq-cse-qspi.dtsi | 126 +++++++++++++++++++++ arch/arm/dts/zynq-syzygy-hub.dts | 72 ++++++++++++ arch/arm/dts/zynq-zc702.dts | 19 +++- arch/arm/dts/zynq-zc706.dts | 1 + arch/arm/dts/zynq-zc770-xm010.dts | 1 + arch/arm/dts/zynq-zc770-xm013.dts | 1 + arch/arm/dts/zynq-zed.dts | 1 + arch/arm/dts/zynq-zybo.dts | 3 +- arch/arm/dts/zynqmp-clk.dtsi | 2 +- arch/arm/dts/zynqmp-ep108-clk.dtsi | 2 +- arch/arm/dts/zynqmp-ep108.dts | 5 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 5 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 - arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 37 ++++++ arch/arm/dts/zynqmp-zcu102-revA.dts | 321 +++++++++++++++++++++++++++++++++++++++++++++++++++- arch/arm/dts/zynqmp-zcu102-revB.dts | 1 + arch/arm/dts/zynqmp.dtsi | 284 ++++++++++++++++++++++++++++++---------------- arch/arm/include/asm/arch-zynqmp/hardware.h | 5 + arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 +- arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/include/mach/nand.h | 9 ++ arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 48 ++++++++ arch/arm/mach-zynq/include/mach/sys_proto.h | 3 - board/topic/zynq/ps7_init_common.c => arch/arm/mach-zynq/ps7_spl_init.c | 37 +++++- arch/arm/mach-zynq/slcr.c | 3 +- arch/arm/mach-zynq/spl.c | 18 +-- board/opalkelly/zynq/MAINTAINERS | 6 + board/opalkelly/zynq/Makefile | 9 ++ board/opalkelly/zynq/board.c | 1 + board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 297 +++++++++++++++++++++++++++++++++++++++++++++++++ board/topic/zynq/Makefile | 2 +- board/topic/zynq/ps7_init_gpl.h | 34 ------ board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +- board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +- board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 2 +- board/xilinx/zynq/board.c | 13 ++- board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c | 815 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynq/zynq-cse-qspi-single | 1 + board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 285 +---------------------------------------------- board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 117 ------------------- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 289 +---------------------------------------------- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 117 ------------------- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 285 +---------------------------------------------- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 117 ------------------- board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 285 +---------------------------------------------- board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 117 ------------------- board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 292 +----------------------------------------------- board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 98 ---------------- board/xilinx/zynqmp/zynqmp.c | 98 +++++++++++++++- configs/syzygy_hub_defconfig | 58 ++++++++++ configs/topic_miami_defconfig | 2 + configs/topic_miamilite_defconfig | 2 + configs/topic_miamiplus_defconfig | 2 + configs/xilinx_zynqmp_ep_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 6 + configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 82 ++++++++++++++ configs/xilinx_zynqmp_zcu102_revA_defconfig | 3 +- configs/xilinx_zynqmp_zcu102_revB_defconfig | 3 +- configs/zynq_cc108_defconfig | 56 ++++++++++ configs/zynq_cse_qspi_defconfig | 62 +++++++++++ configs/zynq_microzed_defconfig | 2 + configs/zynq_picozed_defconfig | 2 + configs/zynq_z_turn_defconfig | 2 + configs/zynq_zc702_defconfig | 4 + configs/zynq_zc706_defconfig | 9 ++ configs/zynq_zc770_xm010_defconfig | 8 ++ configs/zynq_zc770_xm011_defconfig | 3 + configs/zynq_zc770_xm012_defconfig | 3 + configs/zynq_zc770_xm013_defconfig | 8 ++ configs/zynq_zed_defconfig | 3 + configs/zynq_zybo_defconfig | 2 + drivers/ata/ahci.c | 4 +- drivers/ata/dwc_ahci.c | 2 +- drivers/ata/sata_ceva.c | 4 +- drivers/mtd/nand/Kconfig | 7 ++ drivers/mtd/nand/zynq_nand.c | 23 +++- drivers/net/xilinx_axi_emac.c | 130 ++++++++++++---------- drivers/net/zynq_gem.c | 11 +- drivers/serial/Kconfig | 7 ++ include/ahci.h | 8 +- include/configs/syzygy_hub.h | 72 ++++++++++++ include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 13 --- include/configs/zynq_cse.h | 53 +++++++++ include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 +++++ scripts/Makefile.spl | 3 +- scripts/config_whitelist.txt | 1 - tools/zynqmpimage.c | 101 ++++++++++++++++- 104 files changed, 3013 insertions(+), 2358 deletions(-) delete mode 100644 arch/arm/cpu/armv8/zynqmp/slcr.c create mode 100644 arch/arm/dts/zynq-cc108.dts create mode 100644 arch/arm/dts/zynq-cse-qspi-single.dts create mode 100644 arch/arm/dts/zynq-cse-qspi.dtsi create mode 100644 arch/arm/dts/zynq-syzygy-hub.dts create mode 100644 arch/arm/dts/zynqmp-zcu102-rev1.0.dts create mode 100644 arch/arm/mach-zynq/include/mach/nand.h create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h rename board/topic/zynq/ps7_init_common.c => arch/arm/mach-zynq/ps7_spl_init.c (76%) create mode 100644 board/opalkelly/zynq/MAINTAINERS create mode 100644 board/opalkelly/zynq/Makefile create mode 100644 board/opalkelly/zynq/board.c create mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c delete mode 100644 board/topic/zynq/ps7_init_gpl.h create mode 100644 board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c create mode 120000 board/xilinx/zynq/zynq-cse-qspi-single delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h create mode 100644 configs/syzygy_hub_defconfig create mode 100644 configs/xilinx_zynqmp_zcu102_rev1_0_defconfig create mode 100644 configs/zynq_cc108_defconfig create mode 100644 configs/zynq_cse_qspi_defconfig create mode 100644 include/configs/syzygy_hub.h create mode 100644 include/configs/zynq_cse.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h