From patchwork Wed Jan 22 06:05:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517966-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=r/cRywPc; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482ZdT2KQgz9sRR for ; Wed, 22 Jan 2020 17:05:33 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=sp9jhYvYMS/CRxU1 dDBJtSj4px8xAK8W8lPeXNjEHLQ1MaDxZLnbD30Wo4sLcpYVWcR++IXOSiHP8AYf nsdXTml36Qv+4zEqo3RNJzZTkTmnOsjp34uFw+29Xptv0rzKnv/0TyMQyjSxk2W+ CGurqiDeIF4iMr19/gMrzUJlsoA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=0mDk0m4PEkZXvQw1gsCi+D KA1oo=; b=r/cRywPcG+z6WKS2Te5fdJxRrO6quwXv1ir1LKjSo+V+tnBickUyl3 4QU8gOTfStXLRN0DANbnioD0N7M7rlLk65FeSYtpAb4ma6+Lw5O/OgS3a1GqoTA2 GYoNTqkxAt+l1c5hvHPbvXTx8jaDUEmCPLTQHMDBt8L4kLUJWKZmg= Received: (qmail 59750 invoked by alias); 22 Jan 2020 06:05:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59739 invoked by uid 89); 22 Jan 2020 06:05:25 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp2.axis.com Received: from smtp2.axis.com (HELO smtp2.axis.com) (195.60.68.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:05:24 +0000 IronPort-SDR: xzo0SirKXrlgczy1bFHhFANZX3eI3bLXV1TYU4DnzhNYuDCKJVA5JWO+HtBD4ef15B9UWxjwQI IlXstkz/luRm29I09+5kvZdFNKSXUZX0m/qaRwzkDMHXcM2blFBmz9d9f2Ym0c+uLevozMET7Q F1VyIbziNPwsRwuQCH2ksapw8Hughv6CYuatKnED3liEEl0Za36ARrDO6jur+wMzQg2AjdBpkm jS2PqMjftBeRFKzS1wuFso8HSsExNB2Zir0cjzrc6x/DXlW8Irzu1zxIYyLOx9RUTZElbS9F3F nd4= Date: Wed, 22 Jan 2020 07:05:21 +0100 Message-ID: <202001220605.00M65LNc017786@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 1/9] config.gcc: Remove support for crisv32-*-* and cris-*-linux*. MIME-Version: 1.0 X-IsSubscribed: yes gcc: * config.gcc: Remove support for crisv32-*-* and cris-*-linux*. Or really, move from the obsolete targets section, to unsupported targets section, and remove crisv32-*-* and cris-*-linux* from the rest. --- gcc/config.gcc | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 5532a7be6ac..f899b149183 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -248,8 +248,6 @@ md_file= # Obsolete configurations. case ${target} in tile*-*-* \ - | crisv32-*-* \ - | cris-*-linux* \ ) if test "x$enable_obsolete" != xyes; then echo "*** Configuration ${target} is obsolete." >&2 @@ -273,6 +271,8 @@ case ${target} in | arm*-*-elf \ | arm*-*-linux* \ | arm*-*-uclinux* \ + | cris-*-linux* \ + | crisv32-*-* \ | i[34567]86-go32-* \ | i[34567]86-*-go32* \ | m68k-*-uclinuxoldabi* \ @@ -365,9 +365,6 @@ bfin*-*) bpf-*-*) cpu_type=bpf ;; -crisv32-*) - cpu_type=cris - ;; frv*) cpu_type=frv extra_options="${extra_options} g.opt" ;; @@ -1500,14 +1497,6 @@ cr16-*-elf) tmake_file="${tmake_file} cr16/t-cr16 " use_collect2=no ;; -crisv32-*-elf | crisv32-*-none) - tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}" - tmake_file="cris/t-cris" - target_cpu_default=32 - gas=yes - extra_options="${extra_options} cris/elf.opt" - use_gcc_stdint=wrap - ;; cris-*-elf | cris-*-none) tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}" tmake_file="cris/t-cris cris/t-elfmulti" @@ -1515,19 +1504,6 @@ cris-*-elf | cris-*-none) extra_options="${extra_options} cris/elf.opt" use_gcc_stdint=wrap ;; -crisv32-*-linux* | cris-*-linux*) - tm_file="dbxelf.h elfos.h ${tm_file} gnu-user.h linux.h glibc-stdint.h cris/linux.h" - tmake_file="${tmake_file} cris/t-cris cris/t-linux" - extra_options="${extra_options} cris/linux.opt" - case $target in - cris-*-*) - target_cpu_default=10 - ;; - crisv32-*-*) - target_cpu_default=32 - ;; - esac - ;; csky-*-*) if test x${with_endian} != x; then case ${with_endian} in From patchwork Wed Jan 22 06:06:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517967-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=XSkMbhf3; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482Zff09t0z9sRX for ; Wed, 22 Jan 2020 17:06:33 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=CgevW+mB9FWH5RE0 6J5QszblhxNOOrPYUxThjikyEAmRSlYwNlE7IrS94SCTBUVPwoms82qFWY5obf4T 8MyynGMKswD0cU9KrTZGUQkN6oEADITxZpmotQ99m8FppX7ges1BBuFBvXDUKETp mv2FxpOGwLYNjdZ64P2oH1azr4w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=wzOP4lkJ39SzIw4VFpKo4B GxABk=; b=XSkMbhf3F+li8vVQ20xcdoGCProRNjLkmUEjNzQ7IweuGvOlUapIR1 hMrWXL2AlsSjGluIV/zdNT9s3Tr47K10Bcz+hHKggW/IETLaJliLAfh0MTpenxvJ ZsjzCuWw9PrFZthW9ux/VBDH3FFEveZy4pS3URHhVOkgrfepSpWx4= Received: (qmail 61584 invoked by alias); 22 Jan 2020 06:06:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61569 invoked by uid 89); 22 Jan 2020 06:06:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp1.axis.com Received: from smtp1.axis.com (HELO smtp1.axis.com) (195.60.68.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:06:24 +0000 IronPort-SDR: NAsZqRWgU2yZQJTjh1s0QNVcXyFThZnPJnV2GxvY9eJA9Ka9aInwQMYz27xbAarIfi207/5DmB f61rEcK9dDn9KmMN0YV7O1DwZrg2CrG21KIffj4YLkVB0nxhiaxj0jE4iBxTE0MdNEyYhfiCoR 2lmIgq0W2MeDhO0/Ab0dLsuJ9DHzfWdTTEOwo+JJ3fe0+WnAUjO2WoQ0OwWU1VwzU9cN+rcXZQ ZQCfT9mnPYcJmtvnQajlUFZtuRyZbfuXPztGH8BJkTCbYQ1vTLFGiInPm0PkYqJ9jVzLj2BhEV 8e8= Date: Wed, 22 Jan 2020 07:06:21 +0100 Message-ID: <202001220606.00M66LJ4017851@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 2/9] gcc: cris: Remove from gcc/config/cris: t-linux, linux.h, linux.opt MIME-Version: 1.0 X-IsSubscribed: yes gcc: * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt: Remove. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). --- gcc/config/cris/linux.h | 150 ---------------------------------------------- gcc/config/cris/linux.opt | 33 ---------- gcc/config/cris/t-linux | 5 -- 3 files changed, 188 deletions(-) delete mode 100644 gcc/config/cris/linux.h delete mode 100644 gcc/config/cris/linux.opt delete mode 100644 gcc/config/cris/t-linux diff --git a/gcc/config/cris/linux.h b/gcc/config/cris/linux.h deleted file mode 100644 index 3bb6f68a13d..00000000000 --- a/gcc/config/cris/linux.h +++ /dev/null @@ -1,150 +0,0 @@ -/* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 2001-2020 Free Software Foundation, Inc. - Contributed by Axis Communications. Written by Hans-Peter Nilsson. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - - -/* After the first "Node:" comment comes all preprocessor directives and - attached declarations described in the info files, the "Using and - Porting GCC" manual (uapgcc), in the same order as found in the "Target - macros" section in the gcc-2.9x CVS edition of 2000-03-17. FIXME: Not - really, but needs an update anyway. - - There is no generic copy-of-uapgcc comment, you'll have to see uapgcc - for that. If applicable, there is a CRIS-specific comment. The order - of macro definitions follow the order in the manual. Every section in - the manual (node in the info pages) has an introductory `Node: - ' comment. If no macros are defined for a section, only - the section-comment is present. */ - -/* This file defines the macros for cris-axis-linux-gnu that are not - covered by cris.h, elfos.h and (config/)linux.h. */ - -/* Make sure we have a valid TARGET_CPU_DEFAULT, so we can assume it - and take shortcuts below. */ -#ifndef TARGET_CPU_DEFAULT -#error "TARGET_CPU_DEFAULT not defined" -#elif (TARGET_CPU_DEFAULT+0) != 10 && (TARGET_CPU_DEFAULT+0) != 32 -#error "TARGET_CPU_DEFAULT must be 10 or 32, or this file be updated" -#endif - -/* Node: Instruction Output */ - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "" - -/* Node: Driver */ -/* These macros are CRIS-specific, but used in target driver macros. */ - -#undef CRIS_CPP_SUBTARGET_SPEC -#if TARGET_CPU_DEFAULT == 32 -# define CRIS_CPP_SUBTARGET_SPEC \ - "%{pthread:-D_REENTRANT}\ - %{!march=*:%{!mcpu=*:-D__arch_v32 -D__CRIS_arch_version=32}}" -#else -# define CRIS_CPP_SUBTARGET_SPEC \ - "%{pthread:-D_REENTRANT}\ - %{!march=*:%{!mcpu=*:-D__arch_v10 -D__CRIS_arch_version=10}}" -#endif - -#undef CRIS_CC1_SUBTARGET_SPEC -#if TARGET_CPU_DEFAULT == 32 -# define CRIS_CC1_SUBTARGET_SPEC \ - "%{!march=*:%{!mcpu=*:-march=v32}}" -#define CRIS_SUBTARGET_DEFAULT_ARCH MASK_AVOID_GOTPLT -#else -# define CRIS_CC1_SUBTARGET_SPEC \ - "%{!march=*:%{!mcpu=*:-march=v10}}" -#define CRIS_SUBTARGET_DEFAULT_ARCH 0 -#endif - -#undef CRIS_ASM_SUBTARGET_SPEC -#if TARGET_CPU_DEFAULT == 32 -# define CRIS_ASM_SUBTARGET_SPEC \ - "--em=criself \ - %{!march=*:%{!mcpu=*:--march=v32}} \ - %{!fleading-underscore:--no-underscore}\ - %{" FPIE_OR_FPIC_SPEC ": --pic}" -#else -# define CRIS_ASM_SUBTARGET_SPEC \ - "--em=criself \ - %{!march=*:%{!mcpu=*:--march=v10}} \ - %{!fleading-underscore:--no-underscore}\ - %{" FPIE_OR_FPIC_SPEC ": --pic}" -#endif - -/* Previously controlled by target_flags. */ -#undef TARGET_LINUX -#define TARGET_LINUX 1 - -#undef CRIS_SUBTARGET_DEFAULT -#define CRIS_SUBTARGET_DEFAULT \ - (MASK_SVINTO \ - + MASK_ETRAX4_ADD \ - + MASK_ALIGN_BY_32 \ - + CRIS_SUBTARGET_DEFAULT_ARCH) - -#undef CRIS_DEFAULT_CPU_VERSION -#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG - -#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" - -#undef CRIS_LINK_SUBTARGET_SPEC -#define CRIS_LINK_SUBTARGET_SPEC \ - "-mcrislinux\ - %{shared} %{static}\ - %{symbolic:-Bdynamic} %{static:-Bstatic}\ - %{!shared:%{!static:\ - %{rdynamic:-export-dynamic}\ - -dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}\ - %{!r:%{O2|O3: --gc-sections}}" - - -/* Node: Run-time Target */ - -/* For the cris-*-linux* subtarget. */ -#undef TARGET_OS_CPP_BUILTINS -#define TARGET_OS_CPP_BUILTINS() \ - do \ - { \ - GNU_USER_TARGET_OS_CPP_BUILTINS(); \ - if (flag_leading_underscore <= 0) \ - builtin_define ("__NO_UNDERSCORES__"); \ - } \ - while (0) - -/* Node: Type Layout */ - -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -/* Node: Sections */ - -/* GNU/Linux has crti and crtn and does not need the - CRT_CALL_STATIC_FUNCTION trick in cris.h. */ -#undef CRT_CALL_STATIC_FUNCTION - -/* - * Local variables: - * eval: (c-set-style "gnu") - * indent-tabs-mode: t - * End: - */ diff --git a/gcc/config/cris/linux.opt b/gcc/config/cris/linux.opt deleted file mode 100644 index 766c4de3957..00000000000 --- a/gcc/config/cris/linux.opt +++ /dev/null @@ -1,33 +0,0 @@ -; GNU/Linux-specific options for the CRIS port of the compiler. - -; Copyright (C) 2005-2020 Free Software Foundation, Inc. -; -; This file is part of GCC. -; -; GCC is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License as published by the Free -; Software Foundation; either version 3, or (at your option) any later -; version. -; -; GCC is distributed in the hope that it will be useful, but WITHOUT ANY -; WARRANTY; without even the implied warranty of MERCHANTABILITY or -; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -; for more details. -; -; You should have received a copy of the GNU General Public License -; along with GCC; see the file COPYING3. If not see -; . - -; Provide a legacy -mlinux option. -mlinux -Target Report RejectNegative Undocumented - -mno-gotplt -Target Report RejectNegative Mask(AVOID_GOTPLT) -Together with -fpic and -fPIC, do not use GOTPLT references. - -; There's a small added setup cost with using GOTPLT references -; for the first (resolving) call, but should in total be a win -; both in code-size and execution-time. -mgotplt -Target Report RejectNegative InverseMask(AVOID_GOTPLT) Undocumented diff --git a/gcc/config/cris/t-linux b/gcc/config/cris/t-linux deleted file mode 100644 index 71a964936db..00000000000 --- a/gcc/config/cris/t-linux +++ /dev/null @@ -1,5 +0,0 @@ -# We *know* we have a limits.h in the glibc library, with extra -# definitions needed for e.g. libgfortran. -ifneq ($(inhibit_libc),true) -LIMITS_H_TEST = : -endif From patchwork Wed Jan 22 06:07:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226989 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517968-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=gidRIdvw; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482ZgR2jdrz9sRX for ; Wed, 22 Jan 2020 17:07:15 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=eAoQmohrMwKVPWog CsmKvjvjIqJ34aeQnPY2LxtUQ+QL8Z3wnXC17rVpjTMqo+GnVDEZU1wVl8WH/AJA pz71yYrV81FPd4eseB/Ox9bopYKQRCvPxMq2SEPVjxoyqm6yKqOueKXjQOBFKzaj VVRBF6eMdz9M1KhhPY/DZXZqqmI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=bHyFAoqvy7eL2LeO5WkRKz EjYFg=; b=gidRIdvwE+2IE748n4KXH+oHJa765X2ygjNzKjLgjjVOoZv3/8Y+Ur C2b4/Dxzx3WZ5ntI5Hcl0XU+sdOILd76yG6LoSPb4T45vhJZOzyRHbkxLdHkEoPs /vGzEwROE/jnnSv9XJIkB6sxvQ5ZBSY2FrRC8O0SWesiCY3vi4L5g= Received: (qmail 63267 invoked by alias); 22 Jan 2020 06:07:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63254 invoked by uid 89); 22 Jan 2020 06:07:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp1.axis.com Received: from smtp1.axis.com (HELO smtp1.axis.com) (195.60.68.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:07:05 +0000 IronPort-SDR: zQG37a2TCvMpDb6U/JDGz5LQS5+rforcj3T7IuhUCs9Q71XTTivY9gmJ7y7j6k98CIRRtO1aXZ B/YBZJ0OyKafMNpk1M3hZJdALJI9ky6WJ0kc8Gj+g2RaZ05divCMwVG5/fcpxIfO8viuou5Urr EMXOuiicICeduhtoRs/I6/DOOVMzmIoPrfWL5CaitYFS4U+UHLMhlsLqugsmZZdJ88GhVOzGYa rA/EQ8yn6k08yYdd01afL8jN13FfG4+OhP8eVmLT9M071RxeVEG4brnqJcKHQubO+ZuTeizgPj iZ0= Date: Wed, 22 Jan 2020 07:07:03 +0100 Message-ID: <202001220607.00M673rG017916@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 3/9] libgcc: cris: Remove support for crisv32-*-* and cris*-*-linux MIME-Version: 1.0 X-IsSubscribed: yes libgcc: * config.host: Remove support for crisv32-*-* and cris*-*-linux. * config/cris/libgcc-glibc.ver, config/cris/t-linux: Remove. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). --- libgcc/config.host | 9 --------- libgcc/config/cris/libgcc-glibc.ver | 7 ------- libgcc/config/cris/t-linux | 2 -- 3 files changed, 18 deletions(-) delete mode 100644 libgcc/config/cris/libgcc-glibc.ver delete mode 100644 libgcc/config/cris/t-linux diff --git a/libgcc/config.host b/libgcc/config.host index 8f0ea90af57..5146422a263 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -112,9 +112,6 @@ bpf-*-*) ;; cr16-*-*) ;; -crisv32-*-*) - cpu_type=cris - ;; csky*-*-*) cpu_type=csky ;; @@ -577,15 +574,9 @@ cr16-*-elf) tmake_file="${tmake_file} cr16/t-cr16 cr16/t-crtlibid t-fdpbit" extra_parts="$extra_parts crti.o crtn.o crtlibid.o" ;; -crisv32-*-elf) - tmake_file="$tmake_file cris/t-cris t-softfp-sfdf t-softfp" - ;; cris-*-elf) tmake_file="$tmake_file cris/t-cris t-softfp-sfdf t-softfp cris/t-elfmulti" ;; -cris-*-linux* | crisv32-*-linux*) - tmake_file="$tmake_file cris/t-cris t-softfp-sfdf t-softfp cris/t-linux" - ;; csky-*-elf*) tmake_file="csky/t-csky t-fdpbit" extra_parts="$extra_parts crti.o crtn.o" diff --git a/libgcc/config/cris/libgcc-glibc.ver b/libgcc/config/cris/libgcc-glibc.ver deleted file mode 100644 index e35de83100f..00000000000 --- a/libgcc/config/cris/libgcc-glibc.ver +++ /dev/null @@ -1,7 +0,0 @@ -GCC_4.3 { - __Mul - __Div - __Udiv - __Mod - __Umod -} diff --git a/libgcc/config/cris/t-linux b/libgcc/config/cris/t-linux deleted file mode 100644 index 8c7f4d44249..00000000000 --- a/libgcc/config/cris/t-linux +++ /dev/null @@ -1,2 +0,0 @@ -# Override t-linux default. -SHLIB_MAPFILES = libgcc-std.ver $(srcdir)/config/cris/libgcc-glibc.ver From patchwork Wed Jan 22 06:07:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226990 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517969-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=OHtiYaug; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482ZhR3vTBz9sRR for ; Wed, 22 Jan 2020 17:08:07 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=Xwi/NO74K2ASgwLB x2oRrXa+viMdlSM+eDlrrpRSyPnjl2LE6mCOF3rTgZzqQldFK1xbFbdmcS2G1430 WPi6cFiRYV9SiA12gCctcwU0BOSUmkCNVLfw1uUYHpk8CEvUU0jvDGkC1CRxM09I NkQJbagmbqMhSEPzxPHjNSfLcPM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=/4GS2yknnJwQjJIQoV91Df zEPhk=; b=OHtiYaug9PbIqaZVR1YDBx7nA2B9OBv8ZYoPgm8msAKk2SeDzvH7LX K6jUPq1RNdvytpiALK0kMeu/koGdnfKeRnhdjyYDxIZZlYBkdog8lT6xiiyBSpKr TJR+jVF1NfMx59lG7wW0gGSjaBN7LtR+rljK8FV6y9KGVG9HX/avc= Received: (qmail 65023 invoked by alias); 22 Jan 2020 06:07:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65012 invoked by uid 89); 22 Jan 2020 06:07:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp1.axis.com Received: from smtp1.axis.com (HELO smtp1.axis.com) (195.60.68.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:07:55 +0000 IronPort-SDR: 4b9GxKM1s3+5+uXJOIWxZ8Eqc3Wd6RswezE2CL0CxjNi9iEtD2uNi9W7K4AHY+IdaMfY48457/ IUZyBBfIO8DS7rhjwgzWw9NPBJxO5iQ7RbPSqWusgybHcegvto/im6ndsdsAGUzzrok1pRw/TB IS80hWmCDuLvxBwFc0SIFpFRpS/OlWkrW1Rz0F2ecPy2/YOL3lnIJLv+eHfZJwLMKQg1ZfnoCe xWoLQ+Ls0bwhn7kwa0lL6RiNhx9B7N0kjosIUdftKlSBIiTzQwx7XpCFqO5IpB2P9wmeoDI7Wi e/g= Date: Wed, 22 Jan 2020 07:07:52 +0100 Message-ID: <202001220607.00M67q0T017977@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 4/9] gcc/testsuite: gcc.target/cris: Remove crisv32-* and cris-linux-* tests. MIME-Version: 1.0 X-IsSubscribed: yes testsuite: * gcc.target/cris/: Adjust for removing crisv32-* and cris-linux-*. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). After this, within gcc.target, grep -i v32 and grep -i linux finds no matches, except for a comment in gcc.target/cris/asmreg-1.c, now grammar-corrected. --- gcc/testsuite/gcc.target/cris/asm-other.S | 11 ++++------- gcc/testsuite/gcc.target/cris/asmreg-1.c | 2 +- gcc/testsuite/gcc.target/cris/cris.exp | 2 +- gcc/testsuite/gcc.target/cris/inasm-other.c | 8 +++----- gcc/testsuite/gcc.target/cris/sync-1-v10.c | 1 - gcc/testsuite/gcc.target/cris/sync-1-v32.c | 5 ----- gcc/testsuite/gcc.target/cris/sync-2i.c | 1 - gcc/testsuite/gcc.target/cris/sync-2s.c | 1 - gcc/testsuite/gcc.target/cris/sync-3i.c | 1 - gcc/testsuite/gcc.target/cris/sync-3s.c | 1 - gcc/testsuite/gcc.target/cris/sync-4i.c | 1 - gcc/testsuite/gcc.target/cris/sync-4s.c | 1 - gcc/testsuite/gcc.target/cris/torture/cris-torture.exp | 2 +- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c | 13 +------------ gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c | 4 ---- gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c | 1 - gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c | 4 ---- 37 files changed, 11 insertions(+), 107 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/cris/sync-1-v32.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c delete mode 100644 gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c diff --git a/gcc/testsuite/gcc.target/cris/asm-other.S b/gcc/testsuite/gcc.target/cris/asm-other.S index 4fe7ebfc41c..6f34f11fdcf 100644 --- a/gcc/testsuite/gcc.target/cris/asm-other.S +++ b/gcc/testsuite/gcc.target/cris/asm-other.S @@ -1,13 +1,10 @@ /* { dg-do assemble } */ -/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */ -/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */ +/* The base test-case is sort-of-disabled or rather made + always-pass, but remains included by other tests. */ -/* Make sure we can assemble for the "other" variant, with the twist - that the gcc option -march=v0 isn't valid for the assembler. */ +/* Make sure we can *assemble* for another variant. */ .text -#if OTHER_ISA == 32 - addoq 42,$r1,$acr -#else +#ifdef OTHER_ISA 0: move.d [$r2=$r0+42],$r1 bwf 0b diff --git a/gcc/testsuite/gcc.target/cris/asmreg-1.c b/gcc/testsuite/gcc.target/cris/asmreg-1.c index f430fafbeea..d77d1514667 100644 --- a/gcc/testsuite/gcc.target/cris/asmreg-1.c +++ b/gcc/testsuite/gcc.target/cris/asmreg-1.c @@ -3,7 +3,7 @@ /* { dg-final { scan-assembler "\\\.ifnc \\\$r9-\\\$r10-\\\$r11-\\\$r12" } } */ /* Sanity check for asm register operands in syscall failed for - cris-axis-linux-gnu due to regmove bug. + cris-axis-linux-gnu due to a regmove bug. Hans-Peter Nilsson . */ extern void lseek64 (int, long long, int); diff --git a/gcc/testsuite/gcc.target/cris/cris.exp b/gcc/testsuite/gcc.target/cris/cris.exp index c85c849e860..386ff3790b3 100644 --- a/gcc/testsuite/gcc.target/cris/cris.exp +++ b/gcc/testsuite/gcc.target/cris/cris.exp @@ -18,7 +18,7 @@ # looping over tests. # Exit immediately if this isn't a CRIS target. -if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then { +if { ![istarget cris-*-*] } then { return } diff --git a/gcc/testsuite/gcc.target/cris/inasm-other.c b/gcc/testsuite/gcc.target/cris/inasm-other.c index c1c043f56d3..deeb09d8df6 100644 --- a/gcc/testsuite/gcc.target/cris/inasm-other.c +++ b/gcc/testsuite/gcc.target/cris/inasm-other.c @@ -1,6 +1,6 @@ /* { dg-do assemble } */ -/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */ -/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */ +/* The base test-case is sort-of-disabled or rather made + always-pass, but remains included by other tests. */ /* Make sure we can (generate code and) assemble for the "other" variant, with the twist that the gcc option -march=v0 isn't @@ -13,9 +13,7 @@ void f(void) { -#if OTHER_ISA == 32 - asm volatile ("addoq 42,$r11,$acr"); -#else +#ifdef OTHER_ISA asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t" "bwf 0b\n\t" "nop"); diff --git a/gcc/testsuite/gcc.target/cris/sync-1-v10.c b/gcc/testsuite/gcc.target/cris/sync-1-v10.c index 861fc8c538d..fd88f2125e8 100644 --- a/gcc/testsuite/gcc.target/cris/sync-1-v10.c +++ b/gcc/testsuite/gcc.target/cris/sync-1-v10.c @@ -1,5 +1,4 @@ /* Check that we can assemble both base atomic variants. */ /* { dg-do assemble } */ /* { dg-options "-O2 -march=v10" { target { ! march_option } } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-1.c" diff --git a/gcc/testsuite/gcc.target/cris/sync-1-v32.c b/gcc/testsuite/gcc.target/cris/sync-1-v32.c deleted file mode 100644 index 3c1d076ab78..00000000000 --- a/gcc/testsuite/gcc.target/cris/sync-1-v32.c +++ /dev/null @@ -1,5 +0,0 @@ -/* Check that we can assemble both base atomic variants. */ -/* { dg-do assemble } */ -/* { dg-options "-O2 -march=v32" } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ -#include "sync-1.c" diff --git a/gcc/testsuite/gcc.target/cris/sync-2i.c b/gcc/testsuite/gcc.target/cris/sync-2i.c index d491d3c0869..e43aa5356f5 100644 --- a/gcc/testsuite/gcc.target/cris/sync-2i.c +++ b/gcc/testsuite/gcc.target/cris/sync-2i.c @@ -2,7 +2,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Dop -Dtype=int" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ /* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," } } */ /* { dg-final { scan-assembler-not "\tand" } } */ diff --git a/gcc/testsuite/gcc.target/cris/sync-2s.c b/gcc/testsuite/gcc.target/cris/sync-2s.c index 06ff98a2769..9be7dc6bcb5 100644 --- a/gcc/testsuite/gcc.target/cris/sync-2s.c +++ b/gcc/testsuite/gcc.target/cris/sync-2s.c @@ -2,7 +2,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Dop -Dtype=short" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ /* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," } } */ /* { dg-final { scan-assembler-not "\tand" } } */ diff --git a/gcc/testsuite/gcc.target/cris/sync-3i.c b/gcc/testsuite/gcc.target/cris/sync-3i.c index 9e67d61cb35..114e0a846e8 100644 --- a/gcc/testsuite/gcc.target/cris/sync-3i.c +++ b/gcc/testsuite/gcc.target/cris/sync-3i.c @@ -4,7 +4,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Dxchg -Dtype=int" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ /* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/cris/sync-3s.c b/gcc/testsuite/gcc.target/cris/sync-3s.c index 8e87a3b6221..facbb39ed94 100644 --- a/gcc/testsuite/gcc.target/cris/sync-3s.c +++ b/gcc/testsuite/gcc.target/cris/sync-3s.c @@ -4,7 +4,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Dxchg -Dtype=short" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ /* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/cris/sync-4i.c b/gcc/testsuite/gcc.target/cris/sync-4i.c index 78a7012ccdb..9756c696386 100644 --- a/gcc/testsuite/gcc.target/cris/sync-4i.c +++ b/gcc/testsuite/gcc.target/cris/sync-4i.c @@ -1,7 +1,6 @@ /* Check that we don't get alignment-checking code, int. */ /* { dg-do compile } */ /* { dg-options "-O2 -Dtype=int -mno-trap-unaligned-atomic" } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */ /* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */ /* { dg-final { scan-assembler-not "\tand" } } */ diff --git a/gcc/testsuite/gcc.target/cris/sync-4s.c b/gcc/testsuite/gcc.target/cris/sync-4s.c index 6691a48283f..2d644303a79 100644 --- a/gcc/testsuite/gcc.target/cris/sync-4s.c +++ b/gcc/testsuite/gcc.target/cris/sync-4s.c @@ -1,7 +1,6 @@ /* Check that we don't get alignment-checking code, short. */ /* { dg-do compile } */ /* { dg-options "-O2 -Dtype=short -mno-trap-unaligned-atomic" } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ /* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */ /* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */ /* { dg-final { scan-assembler-not "\tand" } } */ diff --git a/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp b/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp index d9fb8530042..c03e657e250 100644 --- a/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp +++ b/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp @@ -18,7 +18,7 @@ # optimization options. # Exit immediately if this isn't a CRIS target. -if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then { +if { ![istarget cris-*-*] } then { return } diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c deleted file mode 100644 index dd8704cc92d..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c index 8055fd380e9..4cd233316e2 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dop -Dtype=int -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c deleted file mode 100644 index c8cef184149..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c deleted file mode 100644 index 3c162e96a4d..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c index 61e1c2047b4..3596e9ea5b1 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c deleted file mode 100644 index 0d78e90019d..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c deleted file mode 100644 index 626a3d5cba4..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c index 339e74cd86c..46a04f42c0e 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c deleted file mode 100644 index 17c6d34d11a..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c index f2835aa06c1..9a50732ef32 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target *-*-linux* } } */ +/* { dg-do run { target { ! *-*-* } } } */ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dop -Dtype=short -mno-unaligned-atomic-may-use-library" } */ @@ -47,12 +47,8 @@ type ret = 42; void my_abort (void) __asm__ (SYMSTR (abort)) __attribute__ ((__used__)); void my_abort (void) #else -#ifdef __gnu_linux__ -void trap_handler(int signum) -#else #error "can't catch break 8" #endif -#endif { if (1 #ifndef TRAP_USING_ABORT @@ -78,13 +74,6 @@ int main(void) { type ret; -#ifndef TRAP_USING_ABORT -#ifdef __gnu_linux__ - if (signal (SIGTRAP, trap_handler) == SIG_ERR) - abort (); -#endif -#endif - #ifndef mis_ok trap_expected = 1; #endif diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c index ba639172ba9..fc91e7c9a8a 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dop -Dtype=short -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c deleted file mode 100644 index 3685c504731..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dop -Dtype=short -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c deleted file mode 100644 index da25614e23b..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c index 09a7a9ea3a0..af6ef8ac748 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dxchg -Dtype=int -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c deleted file mode 100644 index d757a683b17..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c deleted file mode 100644 index e8a425328eb..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c index 2b97613de3c..8c7918470c6 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c deleted file mode 100644 index fb711e0ef78..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c deleted file mode 100644 index 4a3511bf2fb..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c index 94a25e37f04..e7c90a360d3 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c deleted file mode 100644 index 32f8ebbd9bf..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c deleted file mode 100644 index d8dede9c1f6..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=short -mno-unaligned-atomic-may-use-library" } */ -#include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c index 6f5eb02afed..5dcef52207d 100644 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c +++ b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c @@ -2,5 +2,4 @@ /* { dg-additional-sources "../sync-1.c" } */ /* { dg-options "-Dxchg -Dtype=short -DTRAP_USING_ABORT -mno-trap-using-break8" } */ /* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */ -/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */ #include "sync-mis-op-s-1.c" diff --git a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c b/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c deleted file mode 100644 index a6f501c10cc..00000000000 --- a/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c +++ /dev/null @@ -1,4 +0,0 @@ -/* { dg-do run { target *-*-linux* } } */ -/* { dg-additional-sources "../sync-1.c" } */ -/* { dg-options "-Dxchg -Dtype=short -Dmis_ok" } */ -#include "sync-mis-op-s-1.c" From patchwork Wed Jan 22 06:08:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org 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sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp2.axis.com Received: from smtp2.axis.com (HELO smtp2.axis.com) (195.60.68.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:08:39 +0000 IronPort-SDR: FxOy22KOeDfyeYThSTgEFzgELdUgVrUPvIYU6eUSEaO7f+n2uGbJErFAzVnPCNf17zGRJiYoMD HKM7rLH2XMYpSDwRWxckayGp1CwENmlmQGNZ/Mxk9RZ0flkR7ogs4X5kUYstlOGGtIN1grPXwa m68f2mcx6RKPrJVvMAtkmUqGwsBudb5zfbc5l9p4q+8BtydFi0aaTCQTIEdop3mEPJ/OdECMBs hGqQHCh8d6l9WhR8ya2qceZetBsNHdApDOhBHpH/hcVA/FyyQihVBWUhKjMhEJk3X0TtdSkJK6 RQ4= Date: Wed, 22 Jan 2020 07:08:36 +0100 Message-ID: <202001220608.00M68aIx018042@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 5/9] gcc/testsuite: Remove traces of crisv32-* outside gcc.target/cris MIME-Version: 1.0 X-IsSubscribed: yes testsuite: * gcc.dg/20020919-1.c, gcc.dg/pr31866.c, gcc.dg/pr46647.c, gcc.dg/sibcall-10.c, gcc.dg/sibcall-3.c, gcc.dg/sibcall-4.c, gcc.dg/sibcall-9.c, gcc.dg/torture/cris-asm-mof-1.c, gcc.dg/torture/cris-volatile-1.c, gcc.dg/torture/pr38948.c, gcc.dg/tree-ssa/20040204-1.c, gcc.dg/tree-ssa/loop-1.c, gcc.dg/weak/typeof-2.c, lib/target-supports.exp: Remove remaining traces of crisv32-*. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). Uses of "cris*" (as opposed to "cris") are deliberately left unadjusted. --- gcc/testsuite/gcc.dg/20020919-1.c | 2 +- gcc/testsuite/gcc.dg/pr31866.c | 2 +- gcc/testsuite/gcc.dg/pr46647.c | 4 ++-- gcc/testsuite/gcc.dg/sibcall-10.c | 2 +- gcc/testsuite/gcc.dg/sibcall-3.c | 2 +- gcc/testsuite/gcc.dg/sibcall-4.c | 2 +- gcc/testsuite/gcc.dg/sibcall-9.c | 2 +- gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c | 2 +- gcc/testsuite/gcc.dg/torture/cris-volatile-1.c | 2 +- gcc/testsuite/gcc.dg/torture/pr38948.c | 1 - gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/loop-1.c | 2 +- gcc/testsuite/gcc.dg/weak/typeof-2.c | 1 - gcc/testsuite/lib/target-supports.exp | 5 ++--- 14 files changed, 14 insertions(+), 17 deletions(-) diff --git a/gcc/testsuite/gcc.dg/20020919-1.c b/gcc/testsuite/gcc.dg/20020919-1.c index 1dcf75e8ff6..38add3a45f0 100644 --- a/gcc/testsuite/gcc.dg/20020919-1.c +++ b/gcc/testsuite/gcc.dg/20020919-1.c @@ -8,7 +8,7 @@ You must be this tall ---> fit two long longs in asm-declared registers to enter this amusement. */ -/* { dg-do compile { target alpha*-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */ +/* { dg-do compile { target alpha*-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */ /* { dg-options "-O2" } */ /* Constructed examples; input/output (same register), output, input, and diff --git a/gcc/testsuite/gcc.dg/pr31866.c b/gcc/testsuite/gcc.dg/pr31866.c index 4081c0e6ad9..d6a2ab05690 100644 --- a/gcc/testsuite/gcc.dg/pr31866.c +++ b/gcc/testsuite/gcc.dg/pr31866.c @@ -1,5 +1,5 @@ /* PR tree-optimization/31866 */ -/* { dg-do compile { target alpha*-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */ +/* { dg-do compile { target alpha*-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */ /* { dg-options "-O2" } */ #if defined (__alpha__) diff --git a/gcc/testsuite/gcc.dg/pr46647.c b/gcc/testsuite/gcc.dg/pr46647.c index d7ada9650dc..7eefc6e336a 100644 --- a/gcc/testsuite/gcc.dg/pr46647.c +++ b/gcc/testsuite/gcc.dg/pr46647.c @@ -25,5 +25,5 @@ func3 (void) return 0; } -/* The xfail for avr, cris-* and crisv32-* is due to PR53535. */ -/* { dg-final { scan-tree-dump-not "memset" "optimized" { xfail avr-*-* cris-*-* crisv32-*-* } } } */ +/* The xfail for avr and cris-* is due to PR53535. */ +/* { dg-final { scan-tree-dump-not "memset" "optimized" { xfail avr-*-* cris-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/sibcall-10.c b/gcc/testsuite/gcc.dg/sibcall-10.c index 3d58036b468..4ac2ee45fbf 100644 --- a/gcc/testsuite/gcc.dg/sibcall-10.c +++ b/gcc/testsuite/gcc.dg/sibcall-10.c @@ -5,7 +5,7 @@ Copyright (C) 2002 Free Software Foundation Inc. Contributed by Hans-Peter Nilsson */ -/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ +/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ /* -mlongcall disables sibcall patterns. */ /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */ /* -msave-restore disables sibcall patterns. */ diff --git a/gcc/testsuite/gcc.dg/sibcall-3.c b/gcc/testsuite/gcc.dg/sibcall-3.c index eafe8dd8456..9962b641298 100644 --- a/gcc/testsuite/gcc.dg/sibcall-3.c +++ b/gcc/testsuite/gcc.dg/sibcall-3.c @@ -5,7 +5,7 @@ Copyright (C) 2002 Free Software Foundation Inc. Contributed by Hans-Peter Nilsson */ -/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ +/* { dg-do run { xfail { { cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ /* -mlongcall disables sibcall patterns. */ /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */ /* { dg-options "-O2 -foptimize-sibling-calls" } */ diff --git a/gcc/testsuite/gcc.dg/sibcall-4.c b/gcc/testsuite/gcc.dg/sibcall-4.c index 1e039c66854..9ba1d16d489 100644 --- a/gcc/testsuite/gcc.dg/sibcall-4.c +++ b/gcc/testsuite/gcc.dg/sibcall-4.c @@ -5,7 +5,7 @@ Copyright (C) 2002 Free Software Foundation Inc. Contributed by Hans-Peter Nilsson */ -/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ +/* { dg-do run { xfail { { cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ /* -mlongcall disables sibcall patterns. */ /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */ /* { dg-options "-O2 -foptimize-sibling-calls" } */ diff --git a/gcc/testsuite/gcc.dg/sibcall-9.c b/gcc/testsuite/gcc.dg/sibcall-9.c index 6df671da39d..c06acdbea35 100644 --- a/gcc/testsuite/gcc.dg/sibcall-9.c +++ b/gcc/testsuite/gcc.dg/sibcall-9.c @@ -5,7 +5,7 @@ Copyright (C) 2002 Free Software Foundation Inc. Contributed by Hans-Peter Nilsson */ -/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ +/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */ /* -mlongcall disables sibcall patterns. */ /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */ /* -msave-restore disables sibcall patterns. */ diff --git a/gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c b/gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c index 5ebde5ed544..77cee9f4278 100644 --- a/gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c +++ b/gcc/testsuite/gcc.dg/torture/cris-asm-mof-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target cris-*-* crisv32-*-* } } */ +/* { dg-do compile { target cris-*-* } } */ /* { dg-skip-if "" { cris*-*-* } { "-march*" } { "" } } */ /* { dg-options "-O2 -march=v10" } */ /* { dg-final { scan-assembler "in-asm: .mof" } } */ diff --git a/gcc/testsuite/gcc.dg/torture/cris-volatile-1.c b/gcc/testsuite/gcc.dg/torture/cris-volatile-1.c index 6b19852c274..7f613c4dc77 100644 --- a/gcc/testsuite/gcc.dg/torture/cris-volatile-1.c +++ b/gcc/testsuite/gcc.dg/torture/cris-volatile-1.c @@ -2,7 +2,7 @@ Check that size-optimizations for move insns (specifically peephole optimizations) aren't applied to volatile objects in the CRIS port. Origin: Hans-Peter Nilsson. */ -/* { dg-do compile { target cris-*-* crisv32-*-* } } */ +/* { dg-do compile { target cris-*-* } } */ /* { dg-final { scan-assembler-not {movu\...\[} } } */ /* { dg-final { scan-assembler-not {move\.[^d].\[} } } */ /* { dg-final { scan-assembler-not {and\.[^d].\[} } } */ diff --git a/gcc/testsuite/gcc.dg/torture/pr38948.c b/gcc/testsuite/gcc.dg/torture/pr38948.c index 90906eebf22..22cef3b356d 100644 --- a/gcc/testsuite/gcc.dg/torture/pr38948.c +++ b/gcc/testsuite/gcc.dg/torture/pr38948.c @@ -1,5 +1,4 @@ /* { dg-options "-fno-tree-sra" } */ -/* { dg-options "-fno-tree-sra -march=v32" { target cris-*-* } } */ typedef unsigned char byte; typedef unsigned int uint; typedef int bool; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c b/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c index 3e07a359b55..b7d50ecd6d6 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c @@ -33,4 +33,4 @@ void test55 (int x, int y) that the && should be emitted (based on BRANCH_COST). Fix this by teaching dom to look through && and register all components as true. */ -/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* visium-*-* x86_64-*-* riscv*-*-* or1k*-*-* msp430-*-* pru*-*-*" } } } } */ +/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* visium-*-* x86_64-*-* riscv*-*-* or1k*-*-* msp430-*-* pru*-*-*" } } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c index 39ee4dea883..a531b7584a6 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-1.c @@ -46,7 +46,7 @@ int xxx(void) /* CRIS and MSP430 keep the address in a register. */ /* m68k sometimes puts the address in a register, depending on CPU and PIC. */ -/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* amdgcn*-*-* } } } */ +/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* amdgcn*-*-* } } } */ /* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */ /* { dg-final { scan-assembler-times "= foo" 5 { target ia64*-*-* } } } */ /* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */ diff --git a/gcc/testsuite/gcc.dg/weak/typeof-2.c b/gcc/testsuite/gcc.dg/weak/typeof-2.c index 51995ca52fa..afce17f53cb 100644 --- a/gcc/testsuite/gcc.dg/weak/typeof-2.c +++ b/gcc/testsuite/gcc.dg/weak/typeof-2.c @@ -42,7 +42,6 @@ int bar3 (int x) // { dg-final { if [string match s390*-*-* $target_triplet ] {return} } } // Likewise for CRIS targets. // { dg-final { if [string match cris-*-* $target_triplet ] {return} } } -// { dg-final { if [string match crisv32-*-* $target_triplet ] {return} } } // Likewise for m68k targets. // { dg-final { if [string match fido-*-* $target_triplet ] {return} } } // { dg-final { if [string match m68k-*-* $target_triplet ] {return} } } diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f65a8100da9..627e26b4325 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -696,7 +696,6 @@ proc check_profiling_available { test_what } { || [istarget avr-*-*] || [istarget bfin-*-*] || [istarget cris-*-*] - || [istarget crisv32-*-*] || [istarget csky-*-elf] || [istarget fido-*-elf] || [istarget h8300-*-*] @@ -7253,7 +7252,7 @@ proc check_effective_target_sync_int_long { } { || [istarget hppa*-*linux*] || [istarget s390*-*-*] || [istarget powerpc*-*-*] - || [istarget crisv32-*-*] || [istarget cris-*-*] + || [istarget cris-*-*] || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9]) || ([istarget arc*-*-*] && [check_effective_target_arc_atomic]) || [check_effective_target_mips_llsc] }}] @@ -7276,7 +7275,7 @@ proc check_effective_target_sync_char_short { } { || [istarget hppa*-*linux*] || [istarget s390*-*-*] || [istarget powerpc*-*-*] - || [istarget crisv32-*-*] || [istarget cris-*-*] + || [istarget cris-*-*] || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9]) || ([istarget arc*-*-*] && [check_effective_target_arc_atomic]) || [check_effective_target_mips_llsc] }}] From patchwork Wed Jan 22 06:09:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226992 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517971-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=c4527qzI; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482Zk81cdwz9sRR for ; Wed, 22 Jan 2020 17:09:36 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; 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22 Jan 2020 06:09:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp1.axis.com Received: from smtp1.axis.com (HELO smtp1.axis.com) (195.60.68.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:09:27 +0000 IronPort-SDR: KYottIw3U1p3xayrgyDO4lp2L5DkD4rE2dJiYLW/Z+vlky1M2dVs2rH37umvndquxeZrJ/TutO 3F8a3fKE3sv/gRORp38jPXW8hpUgKMLUKUR1RM/cmv8ZKl3Vfk43A6c6ouZ6nudCTjBcXZt0yI Zbts18G68qiLcu1iS+V1fyjPaaE0B6tg1zdV1HHqHzhPAVv3Qk4toOfCqx80wh3iGghsVLH5Yg IejE22lBRi47XWfyv/JU3xMjM9++JN0hXI1MT98OjFkJn8BNi3xIcc+56vDmXg8lEBMsvSvK6M EzA= Date: Wed, 22 Jan 2020 07:09:24 +0100 Message-ID: <202001220609.00M69OYu018107@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 6/9] config/cris/t-elfmulti: Remove crisv32 multilib. MIME-Version: 1.0 X-IsSubscribed: yes gcc: * config/cris/t-elfmulti: Remove crisv32 multilib. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). --- gcc/config/cris/t-elfmulti | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/gcc/config/cris/t-elfmulti b/gcc/config/cris/t-elfmulti index 3c749c46377..84eb7a70825 100644 --- a/gcc/config/cris/t-elfmulti +++ b/gcc/config/cris/t-elfmulti @@ -16,8 +16,8 @@ # along with GCC; see the file COPYING3. If not see # . -MULTILIB_OPTIONS = march=v8/march=v10/march=v32 -MULTILIB_DIRNAMES = v8 v10 v32 +MULTILIB_OPTIONS = march=v8/march=v10 +MULTILIB_DIRNAMES = v8 v10 MULTILIB_MATCHES = \ march?v8=mcpu?v8 \ march?v10=mcpu?etrax100lx \ @@ -26,6 +26,5 @@ MULTILIB_MATCHES = \ march?v10=march?ng \ march?v10=march?v11 \ march?v10=mcpu?v11 \ - march?v10=mcpu?v10 \ - march?v32=mcpu?v32 + march?v10=mcpu?v10 MULTILIB_EXTRA_OPTS = mbest-lib-options From patchwork Wed Jan 22 06:10:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517972-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=kWJJG7R9; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482ZlX0j3kz9sRR for ; Wed, 22 Jan 2020 17:10:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=ZtQeSOWGKDXCdNJQ RPLvLlnsh2Yjn89Cm3oNTcHgDTIslLIZ4AO9++JYH6Kfja6Ool0YWkymQWmBuu7r T+UF+uLn1fToztceNAl5J+J5WZvIna9/60kAkd4pkJo4tsWHe9bBjsWz8jW4q8Ng Gdrn/3T5fOleoGBiGJ8NalMeMpA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=uW8l9Y6Qw0hM94+hiAPQpd Zwb1I=; b=kWJJG7R9BrDg3rqCjYUG1Vv8/B26rMVr3JO8aPEmMOMP4ljkcW8/p1 ownGPju/PZRK5KMyPLbYUq7v/8HZdx+TRAQrDBxt7deh/TgLL4MrV0Un/+GJ4u3d yCb1A/KKexUf6Vdi/MUVgQhK0dd6bUC1sPIcaCEnb55vonKZFuI8w= Received: (qmail 70526 invoked by alias); 22 Jan 2020 06:10:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 70513 invoked by uid 89); 22 Jan 2020 06:10:31 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, KAM_STOCKGEN, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp2.axis.com Received: from smtp2.axis.com (HELO smtp2.axis.com) (195.60.68.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:10:17 +0000 IronPort-SDR: MYiM3QjicqT580pALGxg8l3h6dwLFEj9F4s2xNLFeieIXSsGPpz0f74ZFZzDkCrBndgpMz7GX5 PFH1s9IA3Mz0dutbKby6WNsoS2YQ4vTR4UELXQSMjWa/UWA+54vvl5nuejzozYZQJoFjv22vTG cpy0A/ZPZphRs4LybxDeTvKbz9FKq8TdBk3VWtZ768GJY3Hv8RBlnn+loByUV8HlGZ1/qF9Tl+ kDWqcw7sEA79+iKuZjhrIjmGDkeSWW4XXGgzUl4T2Ic0OGN6OeRfewc4NI9p+SuIR/hGCaSK2j iZI= Date: Wed, 22 Jan 2020 07:10:12 +0100 Message-ID: <202001220610.00M6ACoj018193@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 7/9] gcc/config/cris: Remove shared-library and CRIS v32 support. MIME-Version: 1.0 X-IsSubscribed: yes gcc: * config/cris: Remove shared-library and CRIS v32 support. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). Essentially everything is gone, including functions and target-specific definitions and most obvious knock-on effects, like removing unused functions and arguments. There's one exception: the register-class effects of the CRIS v32 ACR register are deliberately excluded and left in (i.e. its use by-number is removed and the ACE_REGS regclass is always unusable - but present). Changing register class definitions to remove ACR_REGS and related classes (folding their uses into remaining classes), causes extra register moves in libgcc (as an immediate observation; actual net effect unknown), which is unwanted both for performance reasons and also causing extra work comparing before/after cc0-machinery-conversion changes ahead. The actual cause and solution for these negative effects of cleaing up the register-classes will at the moment have to remain to-be-investigated. If CRIS v32 support is reinstated, consider doing the .md part not as separate patterns with opposite conditions but merged patterns with necessarily-different alternatives using the "enabled" attribute (which was not invented back then). Also, a single ACR-related RTL-dump example in a cris.md comment, related to a strict_low_part issue is kept, but marked as obsolete. Note that the "b" register-constraint (non-ACR registers; can be used for post-increment) is left in, as that may have extant uses outside of gcc. Its availability is tested by gcc.target/cris/asm-b-1.c. When ACR register classes are removed, it's probably best to make it equal to GENERAL_REGS. --- gcc/config/cris/constraints.md | 24 +- gcc/config/cris/cris-protos.h | 8 - gcc/config/cris/cris.c | 854 ++----------------------- gcc/config/cris/cris.h | 114 +--- gcc/config/cris/cris.md | 1376 ++++------------------------------------ gcc/config/cris/cris.opt | 4 - gcc/config/cris/predicates.md | 60 +- gcc/config/cris/sync.md | 39 +- 8 files changed, 203 insertions(+), 2276 deletions(-) diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index 7e35083459d..e177a3c10fd 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -18,9 +18,6 @@ ;; . ;; Register constraints. -(define_register_constraint "a" "ACR_REGS" - "@internal") - (define_register_constraint "b" "GENNONACR_REGS" "@internal") @@ -106,7 +103,7 @@ (define_constraint "R" ;; A [reg] or (int) [reg], maybe with post-increment. (match_test "cris_bdap_index_p (op, reload_in_progress || reload_completed)") - (match_test "cris_constant_index_p (op)"))) + (match_test "CONSTANT_P (op)"))) (define_constraint "T" "Memory three-address operand." @@ -118,14 +115,14 @@ (define_constraint "T" reload_in_progress || reload_completed)")) ;; Just an explicit indirect reference: [const]? - (match_test "CRIS_CONSTANT_P (XEXP (op, 0))") + (match_test "CONSTANT_P (XEXP (op, 0))") ;; Something that is indexed; [...+...]? (and (match_code "plus" "0") ;; A BDAP constant: [reg+(8|16|32)bit offset]? (ior (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 0), reload_in_progress || reload_completed)") - (match_test "cris_constant_index_p (XEXP (XEXP (op, 0), 1))")) + (match_test "CONSTANT_P (XEXP (XEXP (op, 0), 1))")) ;; A BDAP register: [reg+[reg(+)].S]? (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 0), reload_in_progress @@ -149,18 +146,3 @@ (define_constraint "T" (match_test "cris_biap_index_p (XEXP (XEXP (op, 0), 0), reload_in_progress || reload_completed)"))))))) - -(define_constraint "S" - "PIC-constructs for symbols." - (and (match_test "flag_pic") - (match_code "const") - (match_test "cris_valid_pic_const (op, false)"))) - -(define_constraint "U" - "@internal" - (and (match_test "flag_pic") - ;; We're just interested in the ..._or_callable_symbol part. - ;; (Using CRIS_CONSTANT_P would exclude that too.) - (match_test "CONSTANT_P (op)") - (match_operand 0 "cris_nonmemory_operand_or_callable_symbol"))) - diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index 2105256cc78..98b24a26bb0 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -27,14 +27,8 @@ extern void cris_notice_update_cc (rtx, rtx_insn *); extern bool cris_reload_address_legitimized (rtx, machine_mode, int, int, int); extern int cris_side_effect_mode_ok (enum rtx_code, rtx *, int, int, int, int, int); -extern bool cris_cc0_user_requires_cmp (rtx_insn *); extern rtx cris_return_addr_rtx (int, rtx); extern rtx cris_split_movdx (rtx *); -extern int cris_legitimate_pic_operand (rtx); -extern enum cris_symbol_type cris_symbol_type_of (const_rtx); -extern bool cris_valid_pic_const (const_rtx, bool); -extern bool cris_legitimate_constant_p (machine_mode, rtx); -extern bool cris_constant_index_p (const_rtx); extern bool cris_base_p (const_rtx, bool); extern bool cris_base_or_autoincr_p (const_rtx, bool); extern bool cris_bdap_index_p (const_rtx, bool); @@ -43,11 +37,9 @@ extern bool cris_legitimate_address_p (machine_mode, rtx, bool); extern bool cris_store_multiple_op_p (rtx); extern bool cris_movem_load_rest_p (rtx, int); extern void cris_asm_output_symbol_ref (FILE *, rtx); -extern int cris_cfun_uses_pic_table (void); extern void cris_asm_output_case_end (FILE *, int, rtx_insn *); extern rtx cris_gen_movem_load (rtx, rtx, int); extern rtx cris_emit_movem_store (rtx, rtx, int, bool); -extern void cris_expand_pic_call_address (rtx *, rtx *); extern void cris_order_for_addsi3 (rtx *, int); extern void cris_emit_trap_for_misalignment (rtx); #endif /* RTX_CODE */ diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 01388b3d019..2f1deae2711 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -116,7 +116,7 @@ static int cris_initial_frame_pointer_offset (void); static void cris_operand_lossage (const char *, rtx); -static int cris_reg_saved_in_regsave_area (unsigned int, bool); +static int cris_reg_saved_in_regsave_area (unsigned int); static void cris_print_operand (FILE *, rtx, int); @@ -124,8 +124,6 @@ static void cris_print_operand_address (FILE *, machine_mode, rtx); static bool cris_print_operand_punct_valid_p (unsigned char code); -static bool cris_output_addr_const_extra (FILE *, rtx); - static void cris_conditional_register_usage (void); static void cris_asm_output_mi_thunk @@ -152,7 +150,6 @@ static void cris_function_arg_advance (cumulative_args_t, static rtx_insn *cris_md_asm_adjust (vec &, vec &, vec &, vec &, HARD_REG_SET &); -static bool cris_cannot_force_const_mem (machine_mode, rtx); static void cris_option_override (void); @@ -164,7 +161,6 @@ static void cris_trampoline_init (rtx, tree, rtx); static rtx cris_function_value(const_tree, const_tree, bool); static rtx cris_libcall_value (machine_mode, const_rtx); static bool cris_function_value_regno_p (const unsigned int); -static void cris_file_end (void); static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode); static bool cris_hard_regno_mode_ok (unsigned int, machine_mode); static HOST_WIDE_INT cris_static_rtx_alignment (machine_mode); @@ -202,8 +198,6 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p -#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA -#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra #undef TARGET_CONDITIONAL_REGISTER_USAGE #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage @@ -215,8 +209,6 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START cris_file_start -#undef TARGET_ASM_FILE_END -#define TARGET_ASM_FILE_END cris_file_end #undef TARGET_INIT_LIBFUNCS #define TARGET_INIT_LIBFUNCS cris_init_libfuncs @@ -227,9 +219,6 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p -#undef TARGET_LEGITIMATE_CONSTANT_P -#define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p - #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class @@ -268,9 +257,6 @@ int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION; #undef TARGET_MD_ASM_ADJUST #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust -#undef TARGET_CANNOT_FORCE_CONST_MEM -#define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem - #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required @@ -342,11 +328,8 @@ cris_movem_load_rest_p (rtx op, int offs) else i = offs + 1; - if (!TARGET_V32) - { - regno_dir = -1; - regno = reg_count - 1; - } + regno_dir = -1; + regno = reg_count - 1; elt = XVECEXP (op, 0, offs); src_addr = XEXP (SET_SRC (elt), 0); @@ -446,11 +429,8 @@ cris_store_multiple_op_p (rtx op) else i = 1; - if (!TARGET_V32) - { - regno_dir = -1; - regno = reg_count - 1; - } + regno_dir = -1; + regno = reg_count - 1; if (GET_CODE (elt) != SET || !REG_P (SET_SRC (elt)) @@ -501,26 +481,6 @@ cris_store_multiple_op_p (rtx op) static void cris_conditional_register_usage (void) { - /* FIXME: This isn't nice. We should be able to use that register for - something else if the PIC table isn't needed. */ - if (flag_pic) - fixed_regs[PIC_OFFSET_TABLE_REGNUM] - = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; - - /* Allow use of ACR (PC in pre-V32) and tweak order. */ - if (TARGET_V32) - { - static const int reg_alloc_order_v32[] = REG_ALLOC_ORDER_V32; - unsigned int i; - - fixed_regs[CRIS_ACR_REGNUM] = 0; - - for (i = 0; - i < sizeof (reg_alloc_order_v32)/sizeof (reg_alloc_order_v32[0]); - i++) - reg_alloc_order[i] = reg_alloc_order_v32[i]; - } - if (TARGET_HAS_MUL_INSNS) fixed_regs[CRIS_MOF_REGNUM] = 0; @@ -530,30 +490,6 @@ cris_conditional_register_usage (void) reg_names[CRIS_CC0_REGNUM] = "ccr"; } -/* Return crtl->uses_pic_offset_table. For use in cris.md, - since some generated files do not include function.h. */ - -int -cris_cfun_uses_pic_table (void) -{ - return crtl->uses_pic_offset_table; -} - -/* Worker function for TARGET_CANNOT_FORCE_CONST_MEM. - We can't put PIC addresses in the constant pool, not even the ones that - can be reached as pc-relative as we can't tell when or how to do that. */ - -static bool -cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) -{ - enum cris_symbol_type t = cris_symbol_type_of (x); - - return - t == cris_unspec - || t == cris_got_symbol - || t == cris_rel_symbol; -} - /* Given an rtx, return the text string corresponding to the CODE of X. Intended for use in the assembly language output section of a define_insn. */ @@ -637,7 +573,7 @@ cris_print_index (rtx index, FILE *file) if (REG_P (index)) fprintf (file, "$%s.b", reg_names[REGNO (index)]); - else if (CRIS_CONSTANT_P (index)) + else if (CONSTANT_P (index)) cris_output_addr_const (file, index); else if (GET_CODE (index) == MULT) { @@ -685,10 +621,7 @@ cris_print_base (rtx base, FILE *file) if (REG_P (base)) fprintf (file, "$%s", reg_names[REGNO (base)]); else if (GET_CODE (base) == POST_INC) - { - gcc_assert (REGNO (XEXP (base, 0)) != CRIS_ACR_REGNUM); - fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); - } + fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]); else cris_operand_lossage ("unexpected base-type in cris_print_base", base); @@ -712,17 +645,11 @@ cris_fatal (char *arg) wrapper for a complicated conditional. */ static int -cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used) +cris_reg_saved_in_regsave_area (unsigned int regno) { return (((df_regs_ever_live_p (regno) - && !call_used_or_fixed_reg_p (regno)) - || (regno == PIC_OFFSET_TABLE_REGNUM - && (got_really_used - /* It is saved anyway, if there would be a gap. */ - || (flag_pic - && df_regs_ever_live_p (regno + 1) - && !call_used_or_fixed_reg_p (regno + 1))))) + && !call_used_or_fixed_reg_p (regno))) && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed) && regno != CRIS_SRP_REGNUM) || (crtl->calls_eh_return @@ -866,16 +793,6 @@ cris_print_operand (FILE *file, rtx x, int code) putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file); return; - case 'Z': - /* If this is a GOT-symbol, print the size-letter corresponding to - -fpic/-fPIC. For everything else, print "d". */ - putc ((flag_pic == 1 - && GET_CODE (x) == CONST - && GET_CODE (XEXP (x, 0)) == UNSPEC - && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREAD) - ? 'w' : 'd', file); - return; - case '#': /* Output a 'nop' if there's nothing for the delay slot. This method stolen from the sparc files. */ @@ -900,13 +817,6 @@ cris_print_operand (FILE *file, rtx x, int code) : ".p2alignw 5,0x050f,2\n\t", file); return; - case ':': - /* The PIC register. */ - if (! flag_pic) - internal_error ("invalid use of %<:%> modifier"); - fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]); - return; - case 'H': /* Print high (most significant) part of something. */ switch (GET_CODE (operand)) @@ -1073,21 +983,6 @@ cris_print_operand (FILE *file, rtx x, int code) fprintf (file, ".d"); return; - case 'd': - /* If this is a GOT symbol, force it to be emitted as :GOT and - :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16). - Avoid making this too much of a special case. */ - if (flag_pic == 1 && CRIS_CONSTANT_P (operand)) - { - int flag_pic_save = flag_pic; - - flag_pic = 2; - cris_output_addr_const (file, operand); - flag_pic = flag_pic_save; - return; - } - break; - case 'D': /* When emitting an sub for the high part of a DImode constant, we want to use subq for 0 and subs.w for -1. */ @@ -1110,17 +1005,6 @@ cris_print_operand (FILE *file, rtx x, int code) fprintf (file, "%s", mults[INTVAL (operand)]); return; - case 'u': - /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */ - if (flag_pic == 1 - && GET_CODE (operand) == CONST - && GET_CODE (XEXP (operand, 0)) == UNSPEC - && XINT (XEXP (operand, 0), 1) == CRIS_UNSPEC_GOTREAD) - fprintf (file, "u.w"); - else - fprintf (file, ".d"); - return; - case 0: /* No code, print as usual. */ break; @@ -1162,8 +1046,6 @@ cris_print_operand (FILE *file, rtx x, int code) } return; - case UNSPEC: - /* Fall through. */ case CONST: cris_output_addr_const (file, operand); return; @@ -1194,7 +1076,7 @@ cris_print_operand (FILE *file, rtx x, int code) default: /* No need to handle all strange variants, let output_addr_const do it for us. */ - if (CRIS_CONSTANT_P (operand)) + if (CONSTANT_P (operand)) { cris_output_addr_const (file, operand); return; @@ -1207,7 +1089,7 @@ cris_print_operand (FILE *file, rtx x, int code) static bool cris_print_operand_punct_valid_p (unsigned char code) { - return (code == '#' || code == '!' || code == ':'); + return (code == '#' || code == '!'); } /* The PRINT_OPERAND_ADDRESS worker. */ @@ -1304,20 +1186,10 @@ cris_initial_frame_pointer_offset (void) /* Initial offset is 0 if we don't have a frame pointer. */ int offs = 0; - bool got_really_used = false; - - if (crtl->uses_pic_offset_table) - { - push_topmost_sequence (); - got_really_used - = reg_used_between_p (pic_offset_table_rtx, get_insns (), - NULL); - pop_topmost_sequence (); - } /* And 4 for each register pushed. */ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) - if (cris_reg_saved_in_regsave_area (regno, got_really_used)) + if (cris_reg_saved_in_regsave_area (regno)) offs += 4; /* And then, last, we add the locals allocated. */ @@ -1384,15 +1256,6 @@ reg_ok_for_index_p (const_rtx x, bool strict) return reg_ok_for_base_p (x, strict); } -/* No symbol can be used as an index (or more correct, as a base) together - with a register with PIC; the PIC register must be there. */ - -bool -cris_constant_index_p (const_rtx x) -{ - return (CRIS_CONSTANT_P (x) && (!flag_pic || cris_valid_pic_const (x, true))); -} - /* True if X is a valid base register. */ bool @@ -1416,8 +1279,7 @@ cris_base_or_autoincr_p (const_rtx x, bool strict) { return (cris_base_p (x, strict) || (GET_CODE (x) == POST_INC - && cris_base_p (XEXP (x, 0), strict) - && REGNO (XEXP (x, 0)) != CRIS_ACR_REGNUM)); + && cris_base_p (XEXP (x, 0), strict))); } /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */ @@ -1446,14 +1308,7 @@ cris_biap_index_p (const_rtx x, bool strict) && cris_scale_int_operand (XEXP (x, 1), VOIDmode))); } -/* Worker function for TARGET_LEGITIMATE_ADDRESS_P. - - A PIC operand looks like a normal symbol here. At output we dress it - in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local - symbol) so we exclude all addressing modes where we can't replace a - plain "symbol" with that. A global PIC symbol does not fit anywhere - here (but is thankfully a general_operand in itself). A local PIC - symbol is valid for the plain "symbol + offset" case. */ +/* Worker function for TARGET_LEGITIMATE_ADDRESS_P. */ bool cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) @@ -1462,10 +1317,7 @@ cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) if (cris_base_or_autoincr_p (x, strict)) return true; - else if (TARGET_V32) - /* Nothing else is valid then. */ - return false; - else if (cris_constant_index_p (x)) + else if (CONSTANT_P (x)) return true; /* Indexed? */ else if (GET_CODE (x) == PLUS) @@ -1473,8 +1325,8 @@ cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) x1 = XEXP (x, 0); x2 = XEXP (x, 1); /* BDAP o, Rd. */ - if ((cris_base_p (x1, strict) && cris_constant_index_p (x2)) - || (cris_base_p (x2, strict) && cris_constant_index_p (x1)) + if ((cris_base_p (x1, strict) && CONSTANT_P (x2)) + || (cris_base_p (x2, strict) && CONSTANT_P (x1)) /* BDAP Rs[+], Rd. */ || (GET_MODE_SIZE (mode) <= UNITS_PER_WORD && ((cris_base_p (x1, strict) @@ -1499,29 +1351,6 @@ cris_legitimate_address_p (machine_mode mode, rtx x, bool strict) return false; } -/* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle - PIC constants that aren't legitimized. FIXME: there used to be a - guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle - PIC constants, but no more (4.7 era); testcase: glibc init-first.c. - While that may be seen as a bug, that guarantee seems a wart by design, - so don't bother; fix the documentation instead. */ - -bool -cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) -{ - enum cris_symbol_type t; - - if (flag_pic) - return LEGITIMATE_PIC_OPERAND_P (x); - - t = cris_symbol_type_of (x); - - return - t == cris_no_symbol - || t == cris_offsettable_symbol - || t == cris_unspec; -} - /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */ bool @@ -1538,9 +1367,6 @@ cris_reload_address_legitimized (rtx x, if (GET_CODE (x) != PLUS) return false; - if (TARGET_V32) - return false; - op0 = XEXP (x, 0); op1 = XEXP (x, 1); op1p = &XEXP (x, 1); @@ -1689,7 +1515,7 @@ cris_normal_notice_update_cc (rtx exp, rtx insn) (set (reg) (...)): CC is (reg) and (...) - unless (...) is 0 or reg is a special - register or (v32 and (...) is -32..-1), then CC does not change. + register, then CC does not change. CC_NO_OVERFLOW unless (...) is reg or mem. (set (mem) (...)): @@ -1806,10 +1632,7 @@ cris_normal_notice_update_cc (rtx exp, rtx insn) else if (SET_SRC (exp) == const0_rtx || (REG_P (SET_SRC (exp)) && (REGNO (SET_SRC (exp)) - > CRIS_LAST_GENERAL_REGISTER)) - || (TARGET_V32 - && REG_P (SET_DEST (exp)) - && satisfies_constraint_I (SET_SRC (exp)))) + > CRIS_LAST_GENERAL_REGISTER))) { /* There's no CC0 change for this case. Just check for overlap. */ @@ -1841,11 +1664,6 @@ cris_normal_notice_update_cc (rtx exp, rtx insn) || GET_CODE (SET_SRC (exp)) == NEG) cc_status.flags |= CC_NO_OVERFLOW; - /* For V32, nothing with a register destination sets - C and V usefully. */ - if (TARGET_V32) - cc_status.flags |= CC_NO_OVERFLOW; - return; } } @@ -1889,10 +1707,6 @@ cris_normal_notice_update_cc (rtx exp, rtx insn) if (cris_reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) internal_error ("internal error: sideeffect-insn affecting main effect"); - - /* For V32, moves to registers don't set C and V. */ - if (TARGET_V32) - cc_status.flags |= CC_NO_OVERFLOW; return; } else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) @@ -1972,16 +1786,8 @@ cris_notice_update_cc (rtx exp, rtx_insn *insn) return; case CC_REV: - case CC_NOOV32: case CC_NORMAL: cris_normal_notice_update_cc (exp, insn); - - /* The "test" insn doesn't clear (carry and) overflow on V32. We - can change bge => bpl and blt => bmi by passing on to the cc0 - user that V should not be considered; bgt and ble are taken - care of by other methods (see {tst,cmp}{si,hi,qi}). */ - if (attrval == CC_NOOV32 && TARGET_V32) - cc_status.flags |= CC_NO_OVERFLOW; return; default: @@ -2000,7 +1806,6 @@ cris_simple_epilogue (void) { unsigned int regno; unsigned int reglimit = STACK_POINTER_REGNUM; - bool got_really_used = false; if (! reload_completed || frame_pointer_needed @@ -2015,21 +1820,9 @@ cris_simple_epilogue (void) || !TARGET_PROLOGUE_EPILOGUE) return false; - /* Can't return from stacked return address with v32. */ - if (TARGET_V32 && cris_return_address_on_stack ()) - return false; - - if (crtl->uses_pic_offset_table) - { - push_topmost_sequence (); - got_really_used - = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); - pop_topmost_sequence (); - } - /* No simple epilogue if there are saved registers. */ for (regno = 0; regno < reglimit; regno++) - if (cris_reg_saved_in_regsave_area (regno, got_really_used)) + if (cris_reg_saved_in_regsave_area (regno)) return false; return true; @@ -2273,7 +2066,7 @@ cris_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, return (2 + 2) / 2; /* A BDAP with some other constant is 2 bytes extra. */ - if (CRIS_CONSTANT_P (tem2)) + if (CONSTANT_P (tem2)) return (2 + 2 + 2) / 2; /* BDAP with something indirect should have a higher cost than @@ -2371,7 +2164,7 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, return 0; /* Check allowed cases, like [r(+)?].[bwd] and const. */ - if (CRIS_CONSTANT_P (val_rtx)) + if (CONSTANT_P (val_rtx)) return 1; if (MEM_P (val_rtx) @@ -2415,49 +2208,6 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); } -/* Whether next_cc0_user of insn is LE or GT or requires a real compare - insn for other reasons. */ - -bool -cris_cc0_user_requires_cmp (rtx_insn *insn) -{ - rtx_insn *cc0_user = NULL; - rtx body; - rtx set; - - gcc_assert (insn != NULL); - - if (!TARGET_V32) - return false; - - cc0_user = next_cc0_user (insn); - if (cc0_user == NULL) - return false; - - body = PATTERN (cc0_user); - set = single_set (cc0_user); - - /* Users can be sCC and bCC. */ - if (JUMP_P (cc0_user) - && GET_CODE (body) == SET - && SET_DEST (body) == pc_rtx - && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE - && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx) - { - return - GET_CODE (XEXP (SET_SRC (body), 0)) == GT - || GET_CODE (XEXP (SET_SRC (body), 0)) == LE; - } - else if (set) - { - return - GET_CODE (SET_SRC (body)) == GT - || GET_CODE (SET_SRC (body)) == LE; - } - - gcc_unreachable (); -} - /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) does not handle the case where the IN operand is strict_low_part; it does handle it for X. Test-case in Axis-20010516. This function takes @@ -2475,114 +2225,6 @@ cris_reg_overlap_mentioned_p (rtx x, rtx in) return reg_overlap_mentioned_p (x, in); } -/* Return TRUE iff X is a CONST valid for e.g. indexing. - ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1 - elsewhere. */ - -bool -cris_valid_pic_const (const_rtx x, bool any_operand) -{ - gcc_assert (flag_pic); - - switch (GET_CODE (x)) - { - case CONST_INT: - case CONST_DOUBLE: - return true; - default: - ; - } - - if (GET_CODE (x) != CONST) - return false; - - x = XEXP (x, 0); - - /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */ - if (GET_CODE (x) == PLUS - && GET_CODE (XEXP (x, 0)) == UNSPEC - && (XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL - || XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_PCREL) - && CONST_INT_P (XEXP (x, 1))) - x = XEXP (x, 0); - - if (GET_CODE (x) == UNSPEC) - switch (XINT (x, 1)) - { - /* A PCREL operand is only valid for call and movsi. */ - case CRIS_UNSPEC_PLT_PCREL: - case CRIS_UNSPEC_PCREL: - return !any_operand; - - case CRIS_UNSPEC_PLT_GOTREL: - case CRIS_UNSPEC_PLTGOTREAD: - case CRIS_UNSPEC_GOTREAD: - case CRIS_UNSPEC_GOTREL: - return true; - default: - gcc_unreachable (); - } - - return cris_symbol_type_of (x) == cris_no_symbol; -} - -/* Helper function to find the right symbol-type to generate, - given the original (non-PIC) representation. */ - -enum cris_symbol_type -cris_symbol_type_of (const_rtx x) -{ - switch (GET_CODE (x)) - { - case SYMBOL_REF: - return flag_pic - ? (SYMBOL_REF_LOCAL_P (x) - ? cris_rel_symbol : cris_got_symbol) - : cris_offsettable_symbol; - - case LABEL_REF: - return flag_pic ? cris_rel_symbol : cris_offsettable_symbol; - - case CONST: - return cris_symbol_type_of (XEXP (x, 0)); - - case PLUS: - case MINUS: - { - enum cris_symbol_type t1 = cris_symbol_type_of (XEXP (x, 0)); - enum cris_symbol_type t2 = cris_symbol_type_of (XEXP (x, 1)); - - gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol); - - if (t1 == cris_got_symbol || t2 == cris_got_symbol) - return cris_got_symbol_needing_fixup; - - return t1 != cris_no_symbol ? t1 : t2; - } - - case CONST_INT: - case CONST_DOUBLE: - return cris_no_symbol; - - case UNSPEC: - return cris_unspec; - - default: - fatal_insn ("unrecognized supposed constant", x); - } - - gcc_unreachable (); -} - -/* The LEGITIMATE_PIC_OPERAND_P worker. */ - -int -cris_legitimate_pic_operand (rtx x) -{ - /* Symbols are not valid PIC operands as-is; just constants. */ - return cris_valid_pic_const (x, true); -} - /* Queue an .ident string in the queue of top-level asm statements. If the front-end is done, we must be being called from toplev.c. In that case, do nothing. */ @@ -2604,31 +2246,13 @@ cris_asm_output_case_end (FILE *stream, int num, rtx_insn *table) assert that we find only what's expected. */ rtx_insn *whole_jump_insn = prev_nonnote_nondebug_insn (table); gcc_assert (whole_jump_insn != NULL_RTX && LABEL_P (whole_jump_insn)); + whole_jump_insn = prev_nonnote_nondebug_insn (whole_jump_insn); - gcc_assert (whole_jump_insn != NULL_RTX - && (JUMP_P (whole_jump_insn) - || (TARGET_V32 && INSN_P (whole_jump_insn) - && GET_CODE (PATTERN (whole_jump_insn)) == SEQUENCE))); + gcc_assert (whole_jump_insn != NULL_RTX && JUMP_P (whole_jump_insn)); + /* Get the pattern of the casejump, so we can extract the default label. */ rtx whole_jump_pat = PATTERN (whole_jump_insn); - if (TARGET_V32) - { - /* This can be a SEQUENCE, meaning the delay-slot of the jump is - filled. We also output the offset word a little differently. */ - rtx parallel_jump - = (GET_CODE (whole_jump_pat) == SEQUENCE - ? PATTERN (XVECEXP (whole_jump_pat, 0, 0)) : whole_jump_pat); - - asm_fprintf (stream, - "\t.word %LL%d-.%s\n", - CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP - (parallel_jump, 0, 0), - 1), 2), 0)), - (TARGET_PDEBUG ? "; default" : "")); - return; - } - asm_fprintf (stream, "\t.word %LL%d-%LL%d%s\n", CODE_LABEL_NUMBER (XEXP @@ -2679,7 +2303,7 @@ cris_option_override (void) || strcmp ("etrax100lx", cris_cpu_str) == 0) cris_cpu_version = 10; - if (cris_cpu_version < 0 || cris_cpu_version > 32) + if (cris_cpu_version < 0 || cris_cpu_version > 10) error ("unknown CRIS version specification in %<-march=%> or " "%<-mcpu=%> : %s", cris_cpu_str); @@ -2727,28 +2351,13 @@ cris_option_override (void) | MASK_DATA_ALIGN | MASK_ALIGN_BY_32); } - if (cris_cpu_version >= CRIS_CPU_V32) - target_flags &= ~(MASK_SIDE_EFFECT_PREFIXES|MASK_MUL_BUG); - if (flag_pic) { /* Use error rather than warning, so invalid use is easily detectable. Still change to the values we expect, to avoid further errors. */ - if (! TARGET_LINUX) - { - error ("%<-fPIC%> and %<-fpic%> are not supported " - "in this configuration"); - flag_pic = 0; - } - - /* Turn off function CSE. We need to have the addresses reach the - call expanders to get PLT-marked, as they could otherwise be - compared against zero directly or indirectly. After visiting the - call expanders they will then be cse:ed, as the call expanders - force_reg the addresses, effectively forcing flag_no_function_cse - to 0. */ - flag_no_function_cse = 1; + error ("%<-fPIC%> and %<-fpic%> are not supported on this target"); + flag_pic = 0; } /* Set the per-function-data initializer. */ @@ -2779,34 +2388,9 @@ cris_asm_output_mi_thunk (FILE *stream, ADDITIVE_SIZE_MODIFIER (-delta), -delta, reg_names[CRIS_FIRST_ARG_REG]); - if (flag_pic) - { - const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0); - - name = (* targetm.strip_name_encoding) (name); - - if (TARGET_V32) - { - fprintf (stream, "\tba "); - assemble_name (stream, name); - fprintf (stream, "%s\n\tnop\n", CRIS_PLT_PCOFFSET_SUFFIX); - } - else - { - fprintf (stream, "\tadd.d "); - assemble_name (stream, name); - fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX); - } - } - else - { - fprintf (stream, "\tjump "); - assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); - fprintf (stream, "\n"); - - if (TARGET_V32) - fprintf (stream, "\tnop\n"); - } + fprintf (stream, "\tjump "); + assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0)); + fprintf (stream, "\n"); final_end_function (); assemble_end_function (thunkdecl, fnname); @@ -2827,17 +2411,6 @@ cris_file_start (void) default_file_start (); } -/* Output that goes at the end of the file, similarly. */ - -static void -cris_file_end (void) -{ - /* For CRIS, the default is to assume *no* executable stack, so output - an executable-stack-note only when needed. */ - if (TARGET_LINUX && trampolines_created) - file_end_indicate_exec_stack (); -} - /* Rename the function calls for integer multiply and divide. */ static void cris_init_libfuncs (void) @@ -3066,7 +2639,6 @@ cris_expand_prologue (void) int framesize = 0; rtx mem, insn; int return_address_on_stack = cris_return_address_on_stack (); - int got_really_used = false; int n_movem_regs = 0; int pretend = crtl->args.pretend_args_size; @@ -3076,17 +2648,6 @@ cris_expand_prologue (void) CRIS_ASSERT (size >= 0); - if (crtl->uses_pic_offset_table) - { - /* A reference may have been optimized out (like the abort () in - fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that - it's still used. */ - push_topmost_sequence (); - got_really_used - = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); - pop_topmost_sequence (); - } - /* Align the size to what's best for the CPU model. */ if (TARGET_STACK_ALIGN) size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; @@ -3179,7 +2740,7 @@ cris_expand_prologue (void) to be saved. */ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { - if (cris_reg_saved_in_regsave_area (regno, got_really_used)) + if (cris_reg_saved_in_regsave_area (regno)) { n_movem_regs++; @@ -3309,23 +2870,6 @@ cris_expand_prologue (void) framesize += size + cfoa_size; } - /* Set up the PIC register, if it is used. */ - if (got_really_used) - { - rtx got - = gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT); - emit_move_insn (pic_offset_table_rtx, got); - - /* FIXME: This is a cover-up for flow2 messing up; it doesn't - follow exceptional paths and tries to delete the GOT load as - unused, if it isn't used on the non-exceptional paths. Other - ports have similar or other cover-ups, or plain bugs marking - the GOT register load as maybe-dead. To see this, remove the - line below and try libsupc++/vec.cc or a trivial - "static void y (); void x () {try {y ();} catch (...) {}}". */ - emit_use (pic_offset_table_rtx); - } - if (cris_max_stackframe && framesize > cris_max_stackframe) warning (0, "stackframe too big: %d bytes", framesize); } @@ -3345,23 +2889,11 @@ cris_expand_epilogue (void) /* A reference may have been optimized out (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that it's still used. */ - int got_really_used = false; int n_movem_regs = 0; if (!TARGET_PROLOGUE_EPILOGUE) return; - if (crtl->uses_pic_offset_table) - { - /* A reference may have been optimized out (like the abort () in - fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that - it's still used. */ - push_topmost_sequence (); - got_really_used - = reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL); - pop_topmost_sequence (); - } - /* Align byte count of stack frame. */ if (TARGET_STACK_ALIGN) size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1; @@ -3371,7 +2903,7 @@ cris_expand_epilogue (void) for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) - if (cris_reg_saved_in_regsave_area (regno, got_really_used)) + if (cris_reg_saved_in_regsave_area (regno)) { n_movem_regs++; @@ -3391,7 +2923,7 @@ cris_expand_epilogue (void) for (regno = FIRST_PSEUDO_REGISTER - 1; regno > last_movem_reg; regno--) - if (cris_reg_saved_in_regsave_area (regno, got_really_used)) + if (cris_reg_saved_in_regsave_area (regno)) { rtx insn; @@ -3491,7 +3023,7 @@ cris_expand_epilogue (void) the return address on the stack. */ if (return_address_on_stack && pretend == 0) { - if (TARGET_V32 || crtl->calls_eh_return) + if (crtl->calls_eh_return) { rtx mem; rtx insn; @@ -3568,20 +3100,12 @@ cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) unsigned int regno = nregs - 1; int regno_inc = -1; - if (TARGET_V32) - { - regno = 0; - regno_inc = 1; - } - if (GET_CODE (srcreg) == POST_INC) srcreg = XEXP (srcreg, 0); CRIS_ASSERT (REG_P (srcreg)); - /* Don't use movem for just one insn. The insns are equivalent except - for the pipeline hazard (on v32); movem does not forward the loaded - registers so there's a three cycles penalty for their use. */ + /* Don't use movem for just one insn. The insns are equivalent. */ if (nregs == 1) return gen_movsi (gen_rtx_REG (SImode, 0), src); @@ -3627,12 +3151,6 @@ cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, unsigned int regno = nregs - 1; int regno_inc = -1; - if (TARGET_V32) - { - regno = 0; - regno_inc = 1; - } - if (GET_CODE (destreg) == POST_INC) increment += nregs * 4; @@ -3641,9 +3159,7 @@ cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, CRIS_ASSERT (REG_P (destreg)); - /* Don't use movem for just one insn. The insns are equivalent except - for the pipeline hazard (on v32); movem does not forward the loaded - registers so there's a three cycles penalty for use. */ + /* Don't use movem for just one insn. The insns are equivalent. */ if (nregs == 1) { rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0)); @@ -3743,138 +3259,6 @@ cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, return insn; } -/* Worker function for expanding the address for PIC function calls. */ - -void -cris_expand_pic_call_address (rtx *opp, rtx *markerp) -{ - rtx op = *opp; - - gcc_assert (flag_pic && MEM_P (op)); - op = XEXP (op, 0); - - /* It might be that code can be generated that jumps to 0 (or to a - specific address). Don't die on that. (There is a - testcase.) */ - if (CONSTANT_P (op) && !CONST_INT_P (op)) - { - enum cris_symbol_type t = cris_symbol_type_of (op); - - CRIS_ASSERT (can_create_pseudo_p ()); - - /* For local symbols (non-PLT), just get the plain symbol - reference into a register. For symbols that can be PLT, make - them PLT. */ - if (t == cris_rel_symbol) - { - /* For v32, we're fine as-is; just PICify the symbol. Forcing - into a register caused performance regression for 3.2.1, - observable in __floatdidf and elsewhere in libgcc. */ - if (TARGET_V32) - { - rtx sym = GET_CODE (op) != CONST ? op : get_related_value (op); - HOST_WIDE_INT offs = get_integer_term (op); - - /* We can't get calls to sym+N, N integer, can we? */ - gcc_assert (offs == 0); - - op = gen_rtx_CONST (Pmode, - gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), - CRIS_UNSPEC_PCREL)); - } - else - op = force_reg (Pmode, op); - - /* A local call. */ - *markerp = const0_rtx; - } - else if (t == cris_got_symbol) - { - if (TARGET_AVOID_GOTPLT) - { - /* Change a "jsr sym" into (allocate register rM, rO) - "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM" - "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and - "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))" - for v32. */ - rtx tem, rm, ro; - - crtl->uses_pic_offset_table = 1; - tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), - TARGET_V32 - ? CRIS_UNSPEC_PLT_PCREL - : CRIS_UNSPEC_PLT_GOTREL); - tem = gen_rtx_CONST (Pmode, tem); - if (TARGET_V32) - op = tem; - else - { - rm = gen_reg_rtx (Pmode); - emit_move_insn (rm, tem); - ro = gen_reg_rtx (Pmode); - if (expand_binop (Pmode, add_optab, rm, - pic_offset_table_rtx, - ro, 0, OPTAB_LIB_WIDEN) != ro) - internal_error ("expand_binop failed in movsi got"); - op = ro; - } - } - else - { - /* Change a "jsr sym" into (allocate register rM, rO) - "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM" - "add.d rPIC,rM,rO" "jsr [rO]" with the memory access - marked as not trapping and not aliasing. No "move.d - [rO],rP" as that would invite to re-use of a value - that should not be reused. FIXME: Need a peephole2 - for cases when this is cse:d from the call, to change - back to just get the PLT entry address, so we don't - resolve the same symbol over and over (the memory - access of the PLTGOT isn't constant). */ - rtx tem, mem, rm, ro; - - gcc_assert (can_create_pseudo_p ()); - crtl->uses_pic_offset_table = 1; - tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), - CRIS_UNSPEC_PLTGOTREAD); - rm = gen_reg_rtx (Pmode); - emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); - ro = gen_reg_rtx (Pmode); - if (expand_binop (Pmode, add_optab, rm, - pic_offset_table_rtx, - ro, 0, OPTAB_LIB_WIDEN) != ro) - internal_error ("expand_binop failed in movsi got"); - mem = gen_rtx_MEM (Pmode, ro); - - /* This MEM doesn't alias anything. Whether it aliases - other same symbols is unimportant. */ - set_mem_alias_set (mem, new_alias_set ()); - MEM_NOTRAP_P (mem) = 1; - op = mem; - } - - /* We need to prepare this call to go through the PLT; we - need to make GOT available. */ - *markerp = pic_offset_table_rtx; - } - else - /* Can't possibly get anything else for a function-call, right? */ - fatal_insn ("unidentifiable call op", op); - - /* If the validizing variant is called, it will try to validize - the address as a valid any-operand constant, but as it's only - valid for calls and moves, it will fail and always be forced - into a register. */ - *opp = replace_equiv_address_nv (*opp, op); - } - else - /* Can't tell what locality a call to a non-constant address has; - better make the GOT register alive at it. - FIXME: Can we see whether the register has known constant - contents? */ - *markerp = pic_offset_table_rtx; -} - /* Make sure operands are in the right order for an addsi3 insn as generated by a define_split. Nothing but REG_P as the first operand is recognized by addsi3 after reload. OPERANDS contains @@ -3911,20 +3295,7 @@ void cris_asm_output_symbol_ref (FILE *file, rtx x) { gcc_assert (GET_CODE (x) == SYMBOL_REF); - - if (flag_pic && in_code > 0) - { - const char *origstr = XSTR (x, 0); - const char *str; - str = (* targetm.strip_name_encoding) (origstr); - assemble_name (file, str); - - /* Sanity check. */ - if (!TARGET_V32 && !crtl->uses_pic_offset_table) - output_operand_lossage ("PIC register isn't set up"); - } - else - assemble_name (file, XSTR (x, 0)); + assemble_name (file, XSTR (x, 0)); } /* Worker function for ASM_OUTPUT_LABEL_REF. */ @@ -3932,80 +3303,7 @@ cris_asm_output_symbol_ref (FILE *file, rtx x) void cris_asm_output_label_ref (FILE *file, char *buf) { - if (flag_pic && in_code > 0) - { - assemble_name (file, buf); - - /* Sanity check. */ - if (!TARGET_V32 && !crtl->uses_pic_offset_table) - internal_error ("emitting PIC operand, but PIC register " - "isn%'t set up"); - } - else - assemble_name (file, buf); -} - -/* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ - -static bool -cris_output_addr_const_extra (FILE *file, rtx xconst) -{ - switch (GET_CODE (xconst)) - { - rtx x; - - case UNSPEC: - x = XVECEXP (xconst, 0, 0); - CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF - || GET_CODE (x) == LABEL_REF - || GET_CODE (x) == CONST); - output_addr_const (file, x); - switch (XINT (xconst, 1)) - { - case CRIS_UNSPEC_PCREL: - /* We only get this with -fpic/PIC to tell it apart from an - invalid symbol. We can't tell here, but it should only - be the operand of a call or movsi. */ - gcc_assert (TARGET_V32 && flag_pic); - break; - - case CRIS_UNSPEC_PLT_PCREL: - gcc_assert (TARGET_V32); - fprintf (file, ":PLT"); - break; - - case CRIS_UNSPEC_PLT_GOTREL: - gcc_assert (!TARGET_V32); - fprintf (file, ":PLTG"); - break; - - case CRIS_UNSPEC_GOTREL: - gcc_assert (!TARGET_V32); - fprintf (file, ":GOTOFF"); - break; - - case CRIS_UNSPEC_GOTREAD: - if (flag_pic == 1) - fprintf (file, ":GOT16"); - else - fprintf (file, ":GOT"); - break; - - case CRIS_UNSPEC_PLTGOTREAD: - if (flag_pic == 1) - fprintf (file, CRIS_GOTPLT_SUFFIX "16"); - else - fprintf (file, CRIS_GOTPLT_SUFFIX); - break; - - default: - gcc_unreachable (); - } - return true; - - default: - return false; - } + assemble_name (file, buf); } /* Worker function for TARGET_STRUCT_VALUE_RTX. */ @@ -4229,51 +3527,12 @@ cris_frame_pointer_required (void) static void cris_asm_trampoline_template (FILE *f) { - if (TARGET_V32) - { - /* This normally-unused nop insn acts as an instruction to - the simulator to flush its instruction cache. None of - the other instructions in the trampoline template suits - as a trigger for V32. The pc-relative addressing mode - works nicely as a trigger for V10. - FIXME: Have specific V32 template (possibly avoiding the - use of a special instruction). */ - fprintf (f, "\tclearf x\n"); - /* We have to use a register as an intermediate, choosing - semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM), - so we can use it for address indirection and jsr target. */ - fprintf (f, "\tmove $r1,$mof\n"); - /* +4 */ - fprintf (f, "\tmove.d 0,$r1\n"); - fprintf (f, "\tmove.d $%s,[$r1]\n", reg_names[STATIC_CHAIN_REGNUM]); - fprintf (f, "\taddq 6,$r1\n"); - fprintf (f, "\tmove $mof,[$r1]\n"); - fprintf (f, "\taddq 6,$r1\n"); - fprintf (f, "\tmove $srp,[$r1]\n"); - /* +20 */ - fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); - /* +26 */ - fprintf (f, "\tmove.d 0,$r1\n"); - fprintf (f, "\tjsr $r1\n"); - fprintf (f, "\tsetf\n"); - /* +36 */ - fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); - /* +42 */ - fprintf (f, "\tmove.d 0,$r1\n"); - /* +48 */ - fprintf (f, "\tmove.d 0,$r9\n"); - fprintf (f, "\tjump $r9\n"); - fprintf (f, "\tsetf\n"); - } - else - { - fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); - fprintf (f, "\tmove $srp,[$pc+22]\n"); - fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); - fprintf (f, "\tjsr 0\n"); - fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); - fprintf (f, "\tjump 0\n"); - } + fprintf (f, "\tmove.d $%s,[$pc+20]\n", reg_names[STATIC_CHAIN_REGNUM]); + fprintf (f, "\tmove $srp,[$pc+22]\n"); + fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); + fprintf (f, "\tjsr 0\n"); + fprintf (f, "\tmove.d 0,$%s\n", reg_names[STATIC_CHAIN_REGNUM]); + fprintf (f, "\tjump 0\n"); } /* Implement TARGET_TRAMPOLINE_INIT. */ @@ -4282,28 +3541,15 @@ static void cris_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) { rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); - rtx tramp = XEXP (m_tramp, 0); rtx mem; emit_block_move (m_tramp, assemble_trampoline_template (), GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); - if (TARGET_V32) - { - mem = adjust_address (m_tramp, SImode, 6); - emit_move_insn (mem, plus_constant (Pmode, tramp, 38)); - mem = adjust_address (m_tramp, SImode, 22); - emit_move_insn (mem, chain_value); - mem = adjust_address (m_tramp, SImode, 28); - emit_move_insn (mem, fnaddr); - } - else - { - mem = adjust_address (m_tramp, SImode, 10); - emit_move_insn (mem, chain_value); - mem = adjust_address (m_tramp, SImode, 16); - emit_move_insn (mem, fnaddr); - } + mem = adjust_address (m_tramp, SImode, 10); + emit_move_insn (mem, chain_value); + mem = adjust_address (m_tramp, SImode, 16); + emit_move_insn (mem, fnaddr); /* Note that there is no need to do anything with the cache for sake of a trampoline. */ @@ -4332,7 +3578,7 @@ cris_hard_regno_mode_ok (unsigned int regno, machine_mode mode) { return ((mode == CCmode || regno != CRIS_CC0_REGNUM) && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD - || (regno != CRIS_MOF_REGNUM && regno != CRIS_ACR_REGNUM))); + || regno != CRIS_MOF_REGNUM)); } /* Return the preferred minimum alignment for a static object. */ diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 4eb5105ae97..4aa12b8c276 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -64,15 +64,6 @@ along with GCC; see the file COPYING3. If not see never clash with it for GCC purposes. */ #define CRIS_CANONICAL_CC0_REGNUM (16 + 13) -/* When generating PIC, these suffixes are added to the names of non-local - functions when being output. Contrary to other ports, we have offsets - relative to the GOT, not the PC. We might implement PC-relative PLT - semantics later for the general case; they are used in some cases right - now, such as MI thunks. */ -#define CRIS_GOTPLT_SUFFIX ":GOTPLT" -#define CRIS_PLT_GOTOFFSET_SUFFIX ":PLTG" -#define CRIS_PLT_PCOFFSET_SUFFIX ":PLT" - #define CRIS_FUNCTION_ARG_SIZE(MODE, TYPE) \ ((MODE) != BLKmode ? GET_MODE_SIZE (MODE) \ : (unsigned) int_size_in_bytes (TYPE)) @@ -115,19 +106,10 @@ extern int cris_cpu_version; #define CRIS_DEFAULT_ASM_ARCH_OPTION "" #ifdef TARGET_CPU_DEFAULT -#if TARGET_CPU_DEFAULT != 32 && TARGET_CPU_DEFAULT != 10 +#if TARGET_CPU_DEFAULT != 10 #error "Due to '()'; e.g. '#define TARGET_CPU_DEFAULT (10)', stringize TARGET_CPU_DEFAULT isn't useful: update manually." #endif -#if TARGET_CPU_DEFAULT == 32 -#undef CRIS_DEFAULT_TUNE -#define CRIS_DEFAULT_TUNE "32" -/* To enable use of "generic" cris-axis-elf binutils, always pass the - architecture option to GAS. (We don't do this for non-v32.) */ -#undef CRIS_DEFAULT_ASM_ARCH_OPTION -#define CRIS_DEFAULT_ASM_ARCH_OPTION "--march=v32" -#endif - #undef CRIS_ARCH_CPP_DEFAULT #define CRIS_ARCH_CPP_DEFAULT \ "%{!march=*:\ @@ -183,8 +165,7 @@ extern int cris_cpu_version; "%(asm_subtarget)\ %{march=*:%{mcpu=*:%edo not specify both -march=... and -mcpu=...}}\ %{march=v0|mcpu=v0|march=v3|mcpu=v3|march=v8|mcpu=v8:--march=v0_v10}\ - %{march=v10|mcpu=v10:--march=v10}\ - %{march=v32|mcpu=v32:--march=v32}" + %{march=v10|mcpu=v10:--march=v10}" /* For the cris-*-elf subtarget. */ #define CRIS_ASM_SUBTARGET_SPEC \ @@ -252,10 +233,6 @@ extern int cris_cpu_version; } \ while (0) -/* Previously controlled by target_flags. Note that this is *not* set - for -melinux. */ -#define TARGET_LINUX 0 - /* For the cris-*-elf subtarget. */ #define CRIS_SUBTARGET_DEFAULT 0 @@ -263,24 +240,17 @@ extern int cris_cpu_version; #define CRIS_CPU_ETRAX4 3 /* Just lz added. */ #define CRIS_CPU_SVINTO 8 /* Added swap, jsrc & Co., 32-bit accesses. */ #define CRIS_CPU_NG 10 /* Added mul[su]. */ -#define CRIS_CPU_V32 32 /* Major changes. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT CRIS_CPU_BASE #endif /* Default target_flags if no switches specified. - The alignment-by-32 is to make builtin atomic support for v10 and v32 + The alignment-by-32 is to make builtin atomic support for v10 work for *-elf for types without specified alignment (like plain "int"). See top comment in sync.md. */ #ifndef TARGET_DEFAULT -# if TARGET_CPU_DEFAULT == 32 -# define TARGET_DEFAULT \ - (MASK_STACK_ALIGN \ - + MASK_CONST_ALIGN + MASK_DATA_ALIGN \ - + MASK_ALIGN_BY_32 \ - + MASK_PROLOGUE_EPILOGUE) -# elif TARGET_CPU_DEFAULT == 10 +# if TARGET_CPU_DEFAULT == 10 # define TARGET_DEFAULT \ (MASK_SIDE_EFFECT_PREFIXES + MASK_STACK_ALIGN \ + MASK_CONST_ALIGN + MASK_DATA_ALIGN \ @@ -301,16 +271,15 @@ extern int cris_cpu_version; #define TARGET_HAS_LZ (cris_cpu_version >= CRIS_CPU_ETRAX4) #define TARGET_HAS_BREAK (cris_cpu_version >= CRIS_CPU_ETRAX4) #define TARGET_HAS_SWAP (cris_cpu_version >= CRIS_CPU_SVINTO) -#define TARGET_V32 (cris_cpu_version >= CRIS_CPU_V32) /* The "break" instruction was introduced with ETRAX 4. */ #define TARGET_TRAP_USING_BREAK8 \ (cris_trap_using_break8 == 2 ? TARGET_HAS_BREAK : cris_trap_using_break8) -/* Call library functions by default for GNU/Linux. */ +/* This condition controls whether to expand atomics inline or call + library functions. */ #define TARGET_ATOMICS_MAY_CALL_LIBFUNCS \ - (cris_atomics_calling_libfunc == 2 \ - ? TARGET_LINUX : cris_atomics_calling_libfunc) + (cris_atomics_calling_libfunc != 2 && cris_atomics_calling_libfunc != 0) /* The < v10 atomics turn off interrupts, so they don't need alignment. Incidentally, by default alignment is off there causing variables to @@ -319,7 +288,7 @@ extern int cris_cpu_version; specify as aligned. */ #define TARGET_TRAP_UNALIGNED_ATOMIC \ (cris_trap_unaligned_atomic == 2 \ - ? (TARGET_V32 || cris_cpu_version == 10) \ + ? cris_cpu_version == 10 \ : cris_trap_unaligned_atomic) /* Node: Storage Layout */ @@ -450,13 +419,6 @@ extern int cris_cpu_version; #define REG_ALLOC_ORDER \ {9, 13, 12, 11, 10, 0, 1, 2, 3, 4, 5, 6, 7, 8, 14, 15, 17, 16, 18, 19} -/* Use MOF and ACR. Prefer ACR before any other register. Prefer MOF - then SRP after saved registers. The *after* is because they're only - useful for storage, not for things being computed, which is - apparently more common. */ -#define REG_ALLOC_ORDER_V32 \ - {15, 9, 13, 12, 11, 10, 0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 16, 14, 18, 19} - /* Node: Leaf Functions */ /* (no definitions) */ @@ -542,14 +504,6 @@ enum reg_class || (unsigned) reg_renumber[REGNO] <= CRIS_LAST_GENERAL_REGISTER \ || (unsigned) reg_renumber[REGNO] == ARG_POINTER_REGNUM) -/* REGNO_OK_FOR_BASE_P seems to be obsolete wrt. this one, but not yet - documented as such. */ -#define REGNO_MODE_CODE_OK_FOR_BASE_P(REGNO, MODE, AS, OCODE, ICODE) \ - (REGNO_OK_FOR_BASE_P (REGNO) \ - && ((OCODE) != POST_INC \ - || !((REGNO) == CRIS_ACR_REGNUM \ - || (unsigned) reg_renumber[REGNO] == CRIS_ACR_REGNUM))) - /* See REGNO_OK_FOR_BASE_P. */ #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) @@ -566,11 +520,6 @@ enum reg_class GENERAL_REGS))) \ ? GENERAL_REGS : NO_REGS) -/* FIXME: Fix regrename.c; it should check validity of replacements, - not just with a silly pass-specific macro. We may miss some - opportunities, but we must stop regrename from creating acr++. */ -#define HARD_REGNO_RENAME_OK(FROM, TO) ((TO) != CRIS_ACR_REGNUM) - /* For CRIS, this is always the size of MODE in words, since all registers are the same size. To use omitted modes in patterns with reload constraints, you must say the widest size @@ -716,7 +665,7 @@ struct cum_args {int regs;}; /* Node: Trampolines */ -#define TRAMPOLINE_SIZE (TARGET_V32 ? 58 : 32) +#define TRAMPOLINE_SIZE 32 /* CRIS wants instructions on word-boundary. */ #define TRAMPOLINE_ALIGNMENT 16 @@ -735,8 +684,6 @@ struct cum_args {int regs;}; #define CONSTANT_ADDRESS_P(X) \ (CONSTANT_P (X) && cris_legitimate_address_p (QImode, X, false)) -/* Must be a compile-time constant, so we go with the highest value - among all CRIS variants. */ #define MAX_REGS_PER_ADDRESS 2 /* Fix reloads known to cause suboptimal spilling. */ @@ -748,12 +695,6 @@ struct cum_args {int regs;}; } \ while (0) -/* The mode argument to cris_legitimate_constant_p isn't used, so just - pass a cheap dummy. N.B. we have to cast away const from the - parameter rather than adjust the parameter, as it's type is mandated - by the TARGET_LEGITIMATE_CONSTANT_P target hook interface. */ -#define CRIS_CONSTANT_P(X) \ - (CONSTANT_P (X) && cris_legitimate_constant_p (VOIDmode, CONST_CAST_RTX (X))) /* Node: Condition Code */ @@ -789,25 +730,6 @@ struct cum_args {int regs;}; #define JUMP_TABLES_IN_TEXT_SECTION 1 -/* Node: PIC */ - -/* Helper type. */ - -enum cris_symbol_type - { - cris_no_symbol = 0, - cris_got_symbol = 1, - cris_rel_symbol = 2, - cris_got_symbol_needing_fixup = 3, - cris_unspec = 7, - cris_offsettable_symbol = 8 - }; - -#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? CRIS_GOT_REGNUM : INVALID_REGNUM) - -#define LEGITIMATE_PIC_OPERAND_P(X) cris_legitimate_pic_operand (X) - - /* Node: File Framework */ /* We don't want an .ident for gcc. To avoid that but still support @@ -898,10 +820,10 @@ enum cris_symbol_type #define REGISTER_NAMES \ {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \ - "r9", "r10", "r11", "r12", "r13", "sp", "acr", "srp", "mof", "faked_ap", "dccr"} + "r9", "r10", "r11", "r12", "r13", "sp", "pc", "srp", "mof", "faked_ap", "dccr"} #define ADDITIONAL_REGISTER_NAMES \ - {{"r14", 14}, {"r15", 15}, {"pc", 15}} + {{"r14", 14}, {"r15", 15}} /* Output an empty line to illustrate the presence of the delay slot. */ #define DBR_OUTPUT_SEQEND(FILE) \ @@ -922,10 +844,7 @@ enum cris_symbol_type #define USER_LABEL_PREFIX "_" #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ - fprintf (FILE, \ - TARGET_V32 \ - ? "\tsubq 4,$sp\n\tmove $%s,[$sp]\n" : "\tpush $%s\n", \ - reg_names[REGNO]) + fprintf (FILE, "\tpush $%s\n", reg_names[REGNO]) #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ fprintf (FILE, "\tmove [$sp+],$%s\n", reg_names[REGNO]) @@ -934,14 +853,7 @@ enum cris_symbol_type /* Node: Dispatch Tables */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - do \ - { \ - if (TARGET_V32) \ - asm_fprintf (FILE, "\t.word %LL%d-.\n", VALUE); \ - else \ - asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL); \ - } \ - while (0) + asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ asm_fprintf (FILE, "\t.dword %LL%d\n", VALUE) diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index b73ea8bb78e..1147d64681b 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -49,46 +49,8 @@ ;; ??? But it should be re-checked for gcc > 2.7.2 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x. -;; FIXME: When PIC, all [rX=rY+S] could be enabled to match -;; [rX=gotless_symbol]. -;; The movsi for a gotless symbol could be split (post reload). - - (define_c_enum "" [ - ;; PLT reference from call expansion: operand 0 is the address, - ;; the mode is VOIDmode. Always wrapped in CONST. - ;; The value is relative to the GOT. - CRIS_UNSPEC_PLT_GOTREL - - ;; PLT reference from call expansion: operand 0 is the address, - ;; the mode is VOIDmode. Always wrapped in CONST. - ;; The value is relative to the PC. It's arch-dependent whether - ;; the offset counts from the start or the end of the current item. - CRIS_UNSPEC_PLT_PCREL - - ;; The address of the global offset table as a source operand. - CRIS_UNSPEC_GOT - - ;; The offset from the global offset table to the operand. - CRIS_UNSPEC_GOTREL - - ;; The PC-relative offset to the operand. It's arch-dependent whether - ;; the offset counts from the start or the end of the current item. - CRIS_UNSPEC_PCREL - - ;; The index into the global offset table of a symbol, while - ;; also generating a GOT entry for the symbol. - CRIS_UNSPEC_GOTREAD - - ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry. - CRIS_UNSPEC_PLTGOTREAD - - ;; Condition for v32 casesi jump, since it needs to have if_then_else - ;; form with register as one branch and default label as other. - ;; Operand 0 is const_int 0. - CRIS_UNSPEC_CASESI - ;; Stack frame deallocation barrier. CRIS_UNSPEC_FRAME_DEALLOC @@ -98,8 +60,7 @@ (define_c_enum "" ;; Register numbers. (define_constants - [(CRIS_GOT_REGNUM 0) - (CRIS_STATIC_CHAIN_REGNUM 7) + [(CRIS_STATIC_CHAIN_REGNUM 7) (CRIS_FP_REGNUM 8) (CRIS_SP_REGNUM 14) (CRIS_ACR_REGNUM 15) @@ -125,10 +86,8 @@ (define_constants ;; In short, any "slottable" instruction must be 16 bit and not refer ;; to pc, or alter it. ;; -;; The possible values are "yes", "no", "has_slot", "has_return_slot" -;; and "has_call_slot". -;; Yes/no tells whether the insn is slottable or not. Has_call_slot means -;; that the insn is a call insn, which for CRIS v32 has a delay-slot. +;; The possible values are "yes", "no", "has_slot", and "has_return_slot". +;; Yes/no tells whether the insn is slottable or not. ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that ;; call delay slot, as it's located in the address *after* the call insn, ;; and the unwind machinery doesn't know about delay slots. @@ -157,13 +116,13 @@ (define_constants ;; constraint pattern for the slottable pattern. An alternative using ;; only "r" constraints is most often slottable. -(define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot" +(define_attr "slottable" "no,yes,has_slot,has_return_slot" (const_string "no")) ;; We also need attributes to sanely determine the condition code ;; state. See cris_notice_update_cc for how this is used. -(define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal")) +(define_attr "cc" "none,clobber,normal,rev" (const_string "normal")) ;; At the moment, this attribute is just used to help bb-reorder do its ;; work; the default 0 doesn't help it. Many insns have other lengths, @@ -181,19 +140,6 @@ (define_attr "length" "" (const_int 2)) (define_delay (eq_attr "slottable" "has_slot") [(eq_attr "slottable" "yes") (nil) (nil)]) -;; We can't put prologue insns in call-insn delay-slots when -;; DWARF2 unwind info is emitted, because the unwinder matches the -;; address after the insn. It must see the return address of a call at -;; a position at least *one byte after* the insn, or it'll think that -;; the insn hasn't been executed. If the insn is in a delay-slot of a -;; call, it's just *exactly* after the insn. - -(define_delay (eq_attr "slottable" "has_call_slot") - [(and (eq_attr "slottable" "yes") - (ior (not (match_test "RTX_FRAME_RELATED_P (insn)")) - (not (match_test "flag_exceptions")))) - (nil) (nil)]) - ;; The insn in the return insn slot must not be the ;; return-address-register restore. FIXME: Use has_slot and express ;; as a parallel with a use of the return-address-register (currently @@ -251,41 +197,14 @@ (define_code_attr roCC [(lt "pl") (ge "mi")]) ;; Normal named test patterns from SI on. -(define_insn "*tstsi" +(define_insn "tst" [(set (cc0) - (compare (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m") + (compare (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m") (const_int 0)))] "" -{ - if (which_alternative == 0 && TARGET_V32) - return "cmpq 0,%0"; - return "test.d %0"; -} + "test %0" [(set_attr "slottable" "yes,yes,no")]) -(define_insn "*tst_cmp" - [(set (cc0) - (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m") - (const_int 0)))] - "cris_cc0_user_requires_cmp (insn)" - "@ - cmp 0,%0 - test %0 - test %0" - [(set_attr "slottable" "no,yes,no")]) - -(define_insn "*tst_non_cmp" - [(set (cc0) - (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m") - (const_int 0)))] - "!cris_cc0_user_requires_cmp (insn)" - "@ - move %0,%0 - test %0 - test %0" - [(set_attr "slottable" "yes,yes,no") - (set_attr "cc" "noov32,*,*")]) - ;; It seems that the position of the sign-bit and the fact that 0.0 is ;; all 0-bits would make "tstsf" a straight-forward implementation; ;; either "test.d" it for positive/negative or "btstq 30,r" it for @@ -301,11 +220,11 @@ (define_insn "*tst_non_cmp" ;; DImode for anything else but a structure/block-mode. Just do the ;; obvious stuff for the straight-forward constraint letters. -(define_insn "*cmpdi_non_v32" +(define_insn "*cmpdi" [(set (cc0) (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o") (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))] - "!TARGET_V32" + "" "@ test.d %M0\;ax\;test.d %H0 cmpq %1,%M0\;ax\;cmpq 0,%H0 @@ -316,18 +235,6 @@ (define_insn "*cmpdi_non_v32" cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1") -(define_insn "*cmpdi_v32" - [(set (cc0) - (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r") - (match_operand:DI 1 "nonmemory_operand" "Kc,I,P,n,r")))] - "TARGET_V32" - "@ - cmpq %1,%M0\;ax\;cmpq 0,%H0 - cmpq %1,%M0\;ax\;cmpq -1,%H0 - cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0 - cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 - cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0") - ;; Note that compare insns with side effect addressing mode (e.g.): ;; ;; cmp.S [rx=ry+i],rz; @@ -450,8 +357,7 @@ (define_insn "*btst" btst %2,%0 clearf nz cmpq %p0,%2" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Move insns. @@ -499,8 +405,7 @@ (define_expand "movdi" { if (MEM_P (operands[0]) && operands[1] != const0_rtx - && can_create_pseudo_p () - && (!TARGET_V32 || !REG_P (operands[1]))) + && can_create_pseudo_p ()) operands[1] = copy_to_mode_reg (DImode, operands[1]); /* Some other ports (as of 2001-09-10 for example mcore and romp) also @@ -530,66 +435,16 @@ (define_expand "movdi" } }) -(define_insn_and_split "*movdi_insn_non_v32" +(define_insn_and_split "*movdi_insn" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m") (match_operand:DI 1 "general_operand" "rx,g,rxM"))] "(register_operand (operands[0], DImode) || register_operand (operands[1], DImode) - || operands[1] == const0_rtx) - && !TARGET_V32" + || operands[1] == const0_rtx)" "#" "&& reload_completed" [(match_dup 2)] "operands[2] = cris_split_movdx (operands);") - -;; Overlapping (but non-identical) source memory address and destination -;; register would be a compiler bug, so we don't have to specify that. -(define_insn "*movdi_v32" - [(set - (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m") - (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))] - "TARGET_V32" -{ - switch (which_alternative) - { - /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2, - particularly for cases where the address register is dead. */ - case 5: - if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0))) - return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0"; - gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0))); - return "move.d [%L1+],%M0\;move.d [%L1],%H0"; - case 2: - /* We could do away with the addq if we knew the address-register - isn't ACR. If we knew the address-register is dead, we could do - away with the subq too. */ - return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1"; - case 4: - return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0"; - case 6: - return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1"; - case 7: - return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0"; - - default: - return "#"; - } -} - ;; The non-split cases clobber cc0 because of their adds and subs. - ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens. - [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")]) - -;; Much like "*movdi_insn_non_v32". Overlapping registers and constants -;; is handled so much better in cris_split_movdx. -(define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "TARGET_V32 - && reload_completed - && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0))) - && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))" - [(match_dup 2)] - "operands[2] = cris_split_movdx (operands);") ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw ;; and move.S1 [rx=ry+i],rz @@ -917,11 +772,9 @@ (define_insn "*clear_side" (define_expand "movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "") - (match_operand:SI 1 "cris_general_operand_or_symbol" ""))] + (match_operand:SI 1 "general_operand" ""))] "" { - enum cris_symbol_type t; - /* If the output goes to a MEM, make sure we have zero or a register as input. */ if (MEM_P (operands[0]) @@ -929,151 +782,14 @@ (define_expand "movsi" && operands[1] != const0_rtx && can_create_pseudo_p ()) operands[1] = force_reg (SImode, operands[1]); - - /* If we're generating PIC and have an incoming symbol, validize it to a - general operand or something that will match a special pattern. - - FIXME: Do we *have* to recognize anything that would normally be a - valid symbol? Can we exclude global PIC addresses with an added - offset? */ - if (flag_pic - && CONSTANT_P (operands[1]) - && !cris_valid_pic_const (operands[1], false)) - { - t = cris_symbol_type_of (operands[1]); - - gcc_assert (t != cris_no_symbol && t != cris_offsettable_symbol); - - if (! REG_S_P (operands[0])) - { - /* We must have a register as destination for what we're about to - do, and for the patterns we generate. */ - CRIS_ASSERT (can_create_pseudo_p ()); - operands[1] = force_reg (SImode, operands[1]); - } - else - { - /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the - destination register for the symbol. It might not be - worth it. Measure. */ - crtl->uses_pic_offset_table = 1; - if (t == cris_rel_symbol) - { - /* Change a "move.d sym(+offs),rN" into (allocate register rM) - for pre-v32: - "move.d (const (plus (unspec [sym] - CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN" - and for v32: - "move.d (const (plus (unspec [sym] - CRIS_UNSPEC_PCREL) offs)),rN". */ - rtx tem, rm, rn = operands[0]; - rtx sym = GET_CODE (operands[1]) != CONST - ? operands[1] : get_related_value (operands[1]); - HOST_WIDE_INT offs = get_integer_term (operands[1]); - - gcc_assert (can_create_pseudo_p ()); - - if (TARGET_V32) - { - tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), - CRIS_UNSPEC_PCREL); - if (offs != 0) - tem = plus_constant (Pmode, tem, offs); - rm = rn; - emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); - } - else - { - /* We still uses GOT-relative addressing for - pre-v32. */ - crtl->uses_pic_offset_table = 1; - tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), - CRIS_UNSPEC_GOTREL); - if (offs != 0) - tem = plus_constant (Pmode, tem, offs); - rm = gen_reg_rtx (Pmode); - emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); - if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx, - rn, 0, OPTAB_LIB_WIDEN) != rn) - internal_error ("expand_binop failed in movsi gotrel"); - } - DONE; - } - else if (t == cris_got_symbol) - { - /* Change a "move.d sym,rN" into (allocate register rM, rO) - "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM" - "add.d rPIC,rM,rO", "move.d [rO],rN" with - the memory access marked as read-only. */ - rtx tem, mem, rm, ro, rn = operands[0]; - gcc_assert (can_create_pseudo_p ()); - tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), - CRIS_UNSPEC_GOTREAD); - rm = gen_reg_rtx (Pmode); - emit_move_insn (rm, gen_rtx_CONST (Pmode, tem)); - ro = gen_reg_rtx (Pmode); - if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx, - ro, 0, OPTAB_LIB_WIDEN) != ro) - internal_error ("expand_binop failed in movsi got"); - mem = gen_rtx_MEM (Pmode, ro); - - /* This MEM doesn't alias anything. Whether it - aliases other same symbols is unimportant. */ - set_mem_alias_set (mem, new_alias_set ()); - MEM_NOTRAP_P (mem) = 1; - - /* We can set the GOT memory read of a non-called symbol - to readonly, but not that of a call symbol, as those - are subject to lazy evaluation and usually have the value - changed from the first call to the second (but - constant thereafter). */ - MEM_READONLY_P (mem) = 1; - emit_move_insn (rn, mem); - DONE; - } - else - { - /* We get here when we have to change something that would - be recognizable if it wasn't PIC. A ``sym'' is ok for - PIC symbols both with and without a GOT entry. And ``sym - + offset'' is ok for local symbols, so the only thing it - could be, is a global symbol with an offset. Check and - abort if not. */ - rtx reg = gen_reg_rtx (Pmode); - rtx sym = get_related_value (operands[1]); - HOST_WIDE_INT offs = get_integer_term (operands[1]); - - gcc_assert (can_create_pseudo_p () - && t == cris_got_symbol_needing_fixup - && sym != NULL_RTX && offs != 0); - - emit_move_insn (reg, sym); - if (expand_binop (SImode, add_optab, reg, - GEN_INT (offs), operands[0], 0, - OPTAB_LIB_WIDEN) != operands[0]) - internal_error ("expand_binop failed in movsi got+offs"); - DONE; - } - } - } }) -(define_insn "*movsi_got_load" - [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))] - "flag_pic" -{ - return TARGET_V32 - ? "lapc _GLOBAL_OFFSET_TABLE_,%:" - : "move.d $pc,%:\;sub.d .:GOTOFF,%:"; -} - [(set_attr "cc" "clobber")]) - (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" - "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x") - (match_operand:SI 1 "cris_general_operand_or_pic_source" - "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))] + "=r,r, r,Q>,r,Q>,g,r,r,g,rQ>,x, m,x") + (match_operand:SI 1 "general_operand" + "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi"))] ;; Note that we prefer not to use the S alternative (if for some reason ;; it competes with others) above, but g matches S. "" @@ -1083,44 +799,18 @@ (define_insn "*movsi_internal" letters. FIXME: Check again. It seems this could shrink a bit. */ switch (which_alternative) { - case 9: - if (TARGET_V32) - { - if (!flag_pic - && (GET_CODE (operands[1]) == SYMBOL_REF - || GET_CODE (operands[1]) == LABEL_REF - || (GET_CODE (operands[1]) == CONST - && (GET_CODE (XEXP (operands[1], 0)) != UNSPEC - || (XINT (XEXP (operands[1], 0), 1) - == CRIS_UNSPEC_PLT_PCREL) - || (XINT (XEXP (operands[1], 0), 1) - == CRIS_UNSPEC_PCREL))))) - { - /* FIXME: Express this through (set_attr cc none) instead, - since we can't express the ``none'' at this point. FIXME: - Use lapc for everything except const_int and when next cc0 - user would want the flag setting. */ - CC_STATUS_INIT; - return "lapc %1,%0"; - } - if (flag_pic == 1 - && GET_CODE (operands[1]) == CONST - && GET_CODE (XEXP (operands[1], 0)) == UNSPEC - && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD) - return "movu.w %1,%0"; - } - /* FALLTHROUGH */ case 0: case 1: case 5: - case 10: + case 8: + case 9: return "move.d %1,%0"; + case 10: case 11: case 12: case 13: - case 14: - return "move %d1,%0"; + return "move %1,%0"; case 2: case 3: @@ -1147,54 +837,12 @@ (define_insn "*movsi_internal" } return "move.d %1,%0"; - case 8: - { - rtx tem = operands[1]; - gcc_assert (GET_CODE (tem) == CONST); - tem = XEXP (tem, 0); - if (GET_CODE (tem) == PLUS - && GET_CODE (XEXP (tem, 0)) == UNSPEC - && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL - || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL) - && CONST_INT_P (XEXP (tem, 1))) - tem = XEXP (tem, 0); - gcc_assert (GET_CODE (tem) == UNSPEC); - switch (XINT (tem, 1)) - { - case CRIS_UNSPEC_GOTREAD: - case CRIS_UNSPEC_PLTGOTREAD: - /* Using sign-extend mostly to be consistent with the - indexed addressing mode. */ - if (flag_pic == 1) - return "movs.w %1,%0"; - return "move.d %1,%0"; - - case CRIS_UNSPEC_GOTREL: - case CRIS_UNSPEC_PLT_GOTREL: - gcc_assert (!TARGET_V32); - return "move.d %1,%0"; - - case CRIS_UNSPEC_PCREL: - case CRIS_UNSPEC_PLT_PCREL: - gcc_assert (TARGET_V32); - /* LAPC doesn't set condition codes; clear them to make the - (equivalence-marked) result of this insn not presumed - present. This instruction can be a PIC symbol load (for - a hidden symbol) which for weak symbols will be followed - by a test for NULL. */ - CC_STATUS_INIT; - return "lapc %1,%0"; - - default: - gcc_unreachable (); - } - } default: - return "BOGUS: %1 to %0"; + gcc_unreachable (); } } - [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no") - (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")]) + [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,yes,yes,no,no") + (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,none,none,none,none")]) ;; Extend operations with side-effect from mem to register, using ;; MOVS/MOVU. These are from mem to register only. @@ -1431,66 +1079,9 @@ (define_insn "movsf" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")]) ;; Movem patterns. Primarily for use in function prologue and epilogue. -;; The V32 variants have an ordering matching the expectations of the -;; standard names "load_multiple" and "store_multiple"; pre-v32 movem -;; store R0 in the highest memory location. - -(define_expand "load_multiple" - [(match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "memory_operand" "") - (match_operand:SI 2 "const_int_operand" "")] - "TARGET_V32" -{ - rtx indreg; - - /* Apparently the predicate isn't checked, so we need to do so - manually. Once happened for libstdc++-v3 locale_facets.tcc. */ - if (!MEM_P (operands[1])) - FAIL; - - indreg = XEXP (operands[1], 0); - - if (GET_CODE (indreg) == POST_INC) - indreg = XEXP (indreg, 0); - if (!REG_P (indreg) - || GET_CODE (operands[2]) != CONST_INT - || !REG_P (operands[0]) - || REGNO (operands[0]) != 0 - || INTVAL (operands[2]) > CRIS_SP_REGNUM - || (int) REGNO (indreg) < INTVAL (operands[2])) - FAIL; - gcc_unreachable (); - emit_insn (cris_gen_movem_load (operands[1], operands[2], 0)); - DONE; -}) - -(define_expand "store_multiple" - [(match_operand:SI 0 "memory_operand" "") - (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "")] - "TARGET_V32" -{ - rtx indreg; - - /* See load_multiple. */ - if (!MEM_P (operands[0])) - FAIL; - - indreg = XEXP (operands[0], 0); - - if (GET_CODE (indreg) == POST_INC) - indreg = XEXP (indreg, 0); - if (!REG_P (indreg) - || GET_CODE (operands[2]) != CONST_INT - || !REG_P (operands[1]) - || REGNO (operands[1]) != 0 - || INTVAL (operands[2]) > CRIS_SP_REGNUM - || (int) REGNO (indreg) < INTVAL (operands[2])) - FAIL; - gcc_unreachable (); - cris_emit_movem_store (operands[0], operands[2], 0, false); - DONE; -}) +;; Unfortunately, movem stores R0 in the highest memory location, thus +;; the opposite of the expectation for the standard names "load_multiple" +;; and "store_multiple". (define_insn "*cris_load_multiple" [(match_parallel 0 "cris_load_multiple_op" @@ -1697,16 +1288,13 @@ (define_expand "adddi3" (plus:DI (match_operand:DI 1 "register_operand") (match_operand:DI 2 "general_operand")))] "" -{ - if (MEM_P (operands[2]) && TARGET_V32) - operands[2] = force_reg (DImode, operands[2]); -}) + "") -(define_insn "*adddi3_non_v32" +(define_insn "*adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r") (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] - "!TARGET_V32" + "" "@ addq %2,%M0\;ax\;addq 0,%H0 subq %n2,%M0\;ax\;subq 0,%H0 @@ -1714,20 +1302,6 @@ (define_insn "*adddi3_non_v32" add.d %M2,%M0\;ax\;add.d %H2,%H0 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0") -; It seems no use allowing a memory operand for this one, because we'd -; need a scratch register for incrementing the address. -(define_insn "*adddi3_v32" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r") - (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0") - (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))] - "TARGET_V32" - "@ - addq %2,%M0\;addc 0,%H0 - subq %n2,%M0\;ax\;subq 0,%H0 - add%e2.%z2 %2,%M0\;addc %H2,%H0 - add.d %M2,%M0\;addc %H2,%H0 - add.d %M2,%M0\;addc %H2,%H0") - (define_expand "add3" [(set (match_operand:BWD 0 "register_operand") (plus:BWD @@ -1736,18 +1310,18 @@ (define_expand "add3" "" "") -(define_insn "*addsi3_non_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r") +(define_insn "*addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r, r") (plus:SI - (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r") - (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))] + (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0,r, r") + (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))] ;; The last constraint is due to that after reload, the '%' is not ;; honored, and canonicalization doesn't care about keeping the same ;; register as in destination. This will happen after insn splitting. ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x - "!TARGET_V32" + "" { switch (which_alternative) { @@ -1777,78 +1351,22 @@ (define_insn "*addsi3_non_v32" } return "add.d %2,%0"; case 5: - { - rtx tem = operands[2]; - gcc_assert (GET_CODE (tem) == CONST); - tem = XEXP (tem, 0); - if (GET_CODE (tem) == PLUS - && GET_CODE (XEXP (tem, 0)) == UNSPEC - /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a - pc-relative operand in an add insn. */ - && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL - && CONST_INT_P (XEXP (tem, 1))) - tem = XEXP (tem, 0); - gcc_assert (GET_CODE (tem) == UNSPEC); - switch (XINT (tem, 1)) - { - case CRIS_UNSPEC_GOTREAD: - case CRIS_UNSPEC_PLTGOTREAD: - /* Using sign-extend mostly to be consistent with the - indexed addressing mode. */ - if (flag_pic == 1) - return "adds.w %2,%0"; - return "add.d %2,%0"; - - case CRIS_UNSPEC_PLT_GOTREL: - case CRIS_UNSPEC_GOTREL: - return "add.d %2,%0"; - default: - gcc_unreachable (); - } - } + return "add.d %2,%0"; case 6: - return "add%u2 %2,%0"; - case 7: return "add.d %2,%1,%0"; - case 8: + case 7: return "add.d %1,%0"; default: return "BOGUS addsi %2+%1 to %0"; } } - [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")]) - -; FIXME: Check what's best: having the three-operand ACR alternative -; before or after the corresponding-operand2 alternative. Check for -; *all* insns. FIXME: constant constraint letter for -128..127. -(define_insn "*addsi3_v32" - [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a") - (plus:SI - (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r") - (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))] - "TARGET_V32" - "@ - add.d %2,%0 - addi %2.b,%1,%0 - add.d %2,%0 - addo.d %2,%1,%0 - addq %2,%0 - subq %n2,%0 - addoq %2,%1,%0 - adds.w %2,%0 - addo %2,%1,%0 - addu.w %2,%0 - add.d %2,%0 - add%u2 %2,%0 - addo.%Z2 %2,%1,%0" - [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no") - (set_attr "cc" "*,none,*,none,*,*,none,*,none,*,*,*,none")]) + [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")]) -(define_insn "*addhi3_non_v32" +(define_insn "*addhi3" [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r") (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r") (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] - "!TARGET_V32" + "" "@ add.w %2,%0 add.w %2,%0 @@ -1859,30 +1377,11 @@ (define_insn "*addhi3_non_v32" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) -(define_insn "*addhi3_v32" - [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a") - (plus:HI - (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r") - (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))] - "TARGET_V32" - "@ - add.w %2,%0 - addi %2.b,%1,%0 - add.w %2,%0 - addo.w %2,%1,%0 - addq %2,%0 - subq %n2,%0 - addoq %2,%1,%0 - add.w %2,%0 - addo.w %2,%1,%0" - [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no") - (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")]) - -(define_insn "*addqi3_non_v32" +(define_insn "*addqi3" [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r") (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r") (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))] - "!TARGET_V32" + "" "@ add.b %2,%0 add.b %2,%0 @@ -1893,26 +1392,6 @@ (define_insn "*addqi3_non_v32" add.b %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no") (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")]) - -(define_insn "*addqi3_v32" - [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a") - (plus:QI - (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r") - (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))] - "TARGET_V32" - "@ - add.b %2,%0 - addi %2.b,%1,%0 - add.b %2,%0 - addo.b %2,%1,%0 - addq %2,%0 - subq %n2,%0 - addoq %2,%1,%0 - subQ -%b2,%0 - add.b %2,%0 - addo.b %2,%1,%0" - [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no") - (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")]) ;; Subtract. ;; @@ -1927,16 +1406,13 @@ (define_expand "subdi3" (minus:DI (match_operand:DI 1 "register_operand") (match_operand:DI 2 "general_operand")))] "" -{ - if (TARGET_V32 && MEM_P (operands[2])) - operands[2] = force_reg (DImode, operands[2]); -}) + "") -(define_insn "*subdi3_non_v32" +(define_insn "*subdi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r") (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] - "!TARGET_V32" + "" "@ subq %2,%M0\;ax\;subq 0,%H0 addq %n2,%M0\;ax\;addq 0,%H0 @@ -1944,17 +1420,6 @@ (define_insn "*subdi3_non_v32" sub.d %M2,%M0\;ax\;sub.d %H2,%H0 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0") -(define_insn "*subdi3_v32" - [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r") - (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0") - (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))] - "TARGET_V32" - "@ - subq %2,%M0\;ax\;subq 0,%H0 - addq %n2,%M0\;ax\;addq 0,%H0 - sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0 - sub.d %M2,%M0\;ax\;sub.d %H2,%H0") - (define_expand "sub3" [(set (match_operand:BWD 0 "register_operand") (minus:BWD @@ -1963,12 +1428,12 @@ (define_expand "sub3" "" "") -(define_insn "*subsi3_non_v32" +(define_insn "*subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r") (minus:SI (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r") (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))] - "!TARGET_V32" + "" ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative. ;; But then again, %2 should not be negative. @@ -1983,28 +1448,12 @@ (define_insn "*subsi3_non_v32" sub.d %2,%0 sub.d %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")]) - -(define_insn "*subsi3_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r") - (minus:SI - (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0") - (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))] - "TARGET_V32" - "@ - sub.d %2,%0 - sub.d %2,%0 - subq %2,%0 - addq %n2,%0 - sub%e2.%z2 %2,%0 - sub.d %2,%0 - sub.d %2,%0" - [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")]) -(define_insn "*sub3_nonv32" +(define_insn "*sub3" [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r") (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r") (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))] - "!TARGET_V32" + "" "@ sub %2,%0 sub %2,%0 @@ -2014,20 +1463,6 @@ (define_insn "*sub3_nonv32" sub %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) - -(define_insn "*sub3_v32" - [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r") - (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0") - (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))] - "TARGET_V32" - "@ - sub %2,%0 - sub %2,%0 - subq %2,%0 - addq %n2,%0 - sub %2,%0" - [(set_attr "slottable" "yes,yes,yes,yes,no") - (set_attr "cc" "normal,normal,clobber,clobber,normal")]) ;; CRIS has some add/sub-with-sign/zero-extend instructions. ;; Although these perform sign/zero-extension to SImode, they are @@ -2261,7 +1696,7 @@ (define_insn "*extopsi_swap_side" ;; QImode to HImode ;; FIXME: GCC should widen. -(define_insn "*extopqihi_non_v32" +(define_insn "*extopqihi" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") (match_operator:HI 3 "cris_additive_operand_extend_operator" @@ -2269,7 +1704,7 @@ (define_insn "*extopqihi_non_v32" (match_operator:HI 4 "cris_extend_operator" [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] - "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD + "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" "@ %x3%E4.%m4 %2,%0 @@ -2279,22 +1714,9 @@ (define_insn "*extopqihi_non_v32" [(set_attr "slottable" "yes,yes,no,no") (set_attr "cc" "clobber")]) -(define_insn "*extopqihi_v32" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI - 3 "cris_additive_operand_extend_operator" - [(match_operand:HI 1 "register_operand" "0,0") - (match_operator:HI - 4 "cris_extend_operator" - [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))] - "TARGET_V32" - "%x3%e4.%m4 %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "clobber")]) - ;; QImode to SImode -(define_insn "*extopsi_non_v32" +(define_insn "*extopsi" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (match_operator:SI 3 "cris_operand_extend_operator" @@ -2302,8 +1724,7 @@ (define_insn "*extopsi_non_v32" (match_operator:SI 4 "cris_extend_operator" [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] - "!TARGET_V32 - && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) + "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" "@ @@ -2312,32 +1733,20 @@ (define_insn "*extopsi_non_v32" %x3%E4 %2,%0 %x3%E4 %2,%1,%0" [(set_attr "slottable" "yes,yes,no,no")]) - -(define_insn "*extopsi_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 3 "cris_additive_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operator:SI - 4 "cris_extend_operator" - [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))] - "TARGET_V32" - "%x3%e4.%m4 %2,%0" - [(set_attr "slottable" "yes")]) ;; As with the side-effect patterns, may have to have swapped operands for add. ;; For commutative operands, these are the canonical forms. ;; QImode to HImode -(define_insn "*addxqihi_swap_non_v32" +(define_insn "*addxqihi_swap" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") (plus:HI (match_operator:HI 3 "cris_extend_operator" [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) (match_operand:HI 1 "register_operand" "0,0,0,r")))] - "!TARGET_V32 && operands[1] != frame_pointer_rtx" + "operands[1] != frame_pointer_rtx" "@ add%e3.b %2,%0 add%e3.b %2,%0 @@ -2346,35 +1755,7 @@ (define_insn "*addxqihi_swap_non_v32" [(set_attr "slottable" "yes,yes,no,no") (set_attr "cc" "clobber")]) -;; A case for v32, to catch the "addo" insn in addition to "adds". We -;; only care to match the canonical form; there should be no other. - -(define_insn "*addsbw_v32" - [(set (match_operand:HI 0 "register_operand" "=r,r,!a") - (plus:HI - (sign_extend:HI - (match_operand:QI 2 "nonimmediate_operand" "r,m,m")) - (match_operand:HI 1 "register_operand" "0,0,r")))] - "TARGET_V32" - "@ - adds.b %2,%0 - adds.b %2,%0 - addo.b %2,%1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "clobber,clobber,none")]) - -(define_insn "*addubw_v32" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (plus:HI - (zero_extend:HI - (match_operand:QI 2 "nonimmediate_operand" "r,m")) - (match_operand:HI 1 "register_operand" "0,0")))] - "TARGET_V32" - "addu.b %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "clobber")]) - -(define_insn "*extopsi_swap_non_v32" +(define_insn "*extopsi" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (match_operator:SI 4 "cris_plus_or_bound_operator" @@ -2382,8 +1763,7 @@ (define_insn "*extopsi_swap_non_v32" 3 "cris_extend_operator" [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")]) (match_operand:SI 1 "register_operand" "0,0,0,r")]))] - "!TARGET_V32 - && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) + "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) && operands[1] != frame_pointer_rtx" "@ %x4%E3 %2,%0 @@ -2391,40 +1771,6 @@ (define_insn "*extopsi_swap_non_v32" %x4%E3 %2,%0 %x4%E3 %2,%1,%0" [(set_attr "slottable" "yes,yes,no,no")]) - -(define_insn "*adds_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r,!a") - (plus:SI - (sign_extend:SI - (match_operand:BW 2 "nonimmediate_operand" "r,m,m")) - (match_operand:SI 1 "register_operand" "0,0,r")))] - "TARGET_V32" - "@ - adds %2,%0 - adds %2,%0 - addo %2,%1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "*,*,none")]) - -(define_insn "*addu_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI - (zero_extend:SI - (match_operand:BW 2 "nonimmediate_operand" "r,m")) - (match_operand:SI 1 "register_operand" "0,0")))] - "TARGET_V32 && operands[1] != frame_pointer_rtx" - "addu %2,%0" - [(set_attr "slottable" "yes")]) - -(define_insn "*bound_v32" - [(set (match_operand:SI 0 "register_operand" "=r") - (umin:SI - (zero_extend:SI - (match_operand:BW 2 "register_operand" "r")) - (match_operand:SI 1 "register_operand" "0")))] - "TARGET_V32 && operands[1] != frame_pointer_rtx" - "bound %2,%0" - [(set_attr "slottable" "yes")]) ;; This is the special case when we use what corresponds to the ;; instruction above in "casesi". Do *not* change it to use the generic @@ -2458,29 +1804,9 @@ (define_insn "*casesi_adds_w" (pc)) (label_ref (match_operand 2 "" "")))) (use (label_ref (match_operand 3 "" "")))] - "!TARGET_V32 && operands[0] != frame_pointer_rtx" + "operands[0] != frame_pointer_rtx" "adds.w [$pc+%0.w],$pc" [(set_attr "cc" "clobber")]) - -;; For V32, we just have a jump, but we need to mark the table as used, -;; and the jump insn must have the if_then_else form expected by core -;; GCC. Since we don't want to prolong the lifetime of the original -;; index value, we compare against "unspec 0". It's a pity we have to -;; jump through to get the default label in place and to keep the jump -;; table around. FIXME: Look into it some time. - -(define_insn "*casesi_jump_v32" - [(set (pc) - (if_then_else - (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) - (match_operand:SI 0 "const_int_operand" "n")) - (match_operand:SI 1 "register_operand" "r") - (label_ref (match_operand 2 "" "")))) - (use (label_ref (match_operand 3 "" "")))] - "TARGET_V32" - "jump %1%#" - [(set_attr "cc" "clobber") - (set_attr "slottable" "has_slot")]) ;; Multiply instructions. @@ -2520,24 +1846,18 @@ (define_insn "addi_mul" ;; The addi insn as it is normally used. -;; Make the ACR alternative taste bad enough to not choose it as a -;; preference to avoid spilling problems (unwind-dw2-fde.c at build). -;; FIXME: Revisit for new register allocator. - (define_insn "*addi" - [(set (match_operand:SI 0 "register_operand" "=r,!a") + [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 1 "register_operand" "0,r")))] + (mult:SI (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "const_int_operand" "n")) + (match_operand:SI 1 "register_operand" "0")))] "operands[0] != frame_pointer_rtx && operands[1] != frame_pointer_rtx && CONST_INT_P (operands[3]) && (INTVAL (operands[3]) == 1 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)" - "@ - addi %2%T3,%0 - addi %2%T3,%1,%0" + "addi %2%T3,%0" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) @@ -2554,7 +1874,7 @@ (define_insn "mstep_shift" (match_operand:SI 2 "register_operand" "r")) (ashift:SI (match_operand:SI 3 "register_operand" "0") (const_int 1))))] - "!TARGET_V32" + "" "mstep %2,%0" [(set_attr "slottable" "yes")]) @@ -2572,8 +1892,7 @@ (define_insn "mstep_mul" (match_operand:SI 2 "register_operand" "r")) (mult:SI (match_operand:SI 3 "register_operand" "0") (const_int 2))))] - "!TARGET_V32 - && operands[0] != frame_pointer_rtx + "operands[0] != frame_pointer_rtx && operands[1] != frame_pointer_rtx && operands[2] != frame_pointer_rtx && operands[3] != frame_pointer_rtx" @@ -2682,8 +2001,7 @@ (define_insn "dstep_shift" (const_int 1))))] "" "dstep %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Here's a variant with mult instead of ashift. ;; @@ -2705,8 +2023,7 @@ (define_insn "dstep_mul" && operands[2] != frame_pointer_rtx && operands[3] != frame_pointer_rtx" "dstep %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Logical operators. @@ -2800,11 +2117,11 @@ (define_insn "*andsi_clear" ;; pressure (worse code). That will hopefully change with an ;; improved reload pass. -(define_insn "*expanded_andsi_non_v32" +(define_insn "*expanded_andsi" [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r") (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r") (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))] - "!TARGET_V32" + "" "@ andq %2,%0 and.d %2,%0 @@ -2812,19 +2129,6 @@ (define_insn "*expanded_andsi_non_v32" and.d %2,%0 and.d %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,no,no")]) - -(define_insn "*expanded_andsi_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0") - (match_operand:SI 2 "general_operand" "I,r,Q>,g")))] - "TARGET_V32" - "@ - andq %2,%0 - and.d %2,%0 - and.d %2,%0 - and.d %2,%0" - [(set_attr "slottable" "yes,yes,yes,no") - (set_attr "cc" "noov32")]) ;; For both QI and HI we may use the quick patterns. This results in ;; useless condition codes, but that is used rarely enough for it to @@ -2887,7 +2191,7 @@ (define_insn "*andhi_clear" ;; Catch-all andhi3 pattern. -(define_insn "*expanded_andhi_non_v32" +(define_insn "*expanded_andhi" [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] @@ -2897,7 +2201,7 @@ (define_insn "*expanded_andhi_non_v32" ;; pressure (worse code). That will hopefully change with an ;; improved reload pass. - "!TARGET_V32" + "" "@ andq %2,%0 and.w %2,%0 @@ -2909,21 +2213,6 @@ (define_insn "*expanded_andhi_non_v32" [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) -(define_insn "*expanded_andhi_v32" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") - (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") - (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))] - "TARGET_V32" - "@ - andq %2,%0 - and.w %2,%0 - and.w %2,%0 - and.w %2,%0 - anDq %b2,%0 - and.w %2,%0" - [(set_attr "slottable" "yes,yes,yes,no,yes,no") - (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")]) - ;; A strict_low_part pattern. ;; Note the use of (match_dup 0) for the first operand of the operation @@ -2936,6 +2225,7 @@ (define_insn "*expanded_andhi_v32" ;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0) ;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32} ;; (nil)) +;; (Note: the example is obsolete.) ;; In theory, it could reload this as a movstrictqi of the register ;; operand at the and:QI to the destination register and change the ;; and:QI operand to the same as the read-write output operand and the @@ -2947,30 +2237,17 @@ (define_insn "*expanded_andhi_v32" ;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with ;; input-constraints matching input-output-constraints, e.g. "+r" <- "0". -(define_insn "*andhi_lowpart_non_v32" +(define_insn "*andhi_lowpart" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r,r,r")) (and:HI (match_dup 0) (match_operand:HI 1 "general_operand" "r,Q>,g")))] - "!TARGET_V32" + "" "@ and.w %1,%0 and.w %1,%0 and.w %1,%0" [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "*andhi_lowpart_v32" - [(set (strict_low_part - (match_operand:HI 0 "register_operand" "+r,r,r")) - (and:HI (match_dup 0) - (match_operand:HI 1 "general_operand" "r,Q>,g")))] - "TARGET_V32" - "@ - and.w %1,%0 - and.w %1,%0 - and.w %1,%0" - [(set_attr "slottable" "yes,yes,no") - (set_attr "cc" "noov32")]) (define_expand "andqi3" [(set (match_operand:QI 0 "register_operand") @@ -2979,11 +2256,11 @@ (define_expand "andqi3" "" "") -(define_insn "*andqi3_non_v32" +(define_insn "*andqi3" [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] - "!TARGET_V32" + "" "@ andq %2,%0 and.b %2,%0 @@ -2994,44 +2271,17 @@ (define_insn "*andqi3_non_v32" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) -(define_insn "*andqi3_v32" - [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") - (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))] - "TARGET_V32" - "@ - andq %2,%0 - and.b %2,%0 - and.b %2,%0 - andQ %b2,%0 - and.b %2,%0" - [(set_attr "slottable" "yes,yes,yes,yes,no") - (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")]) - -(define_insn "*andqi_lowpart_non_v32" +(define_insn "*andqi_lowpart" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r,r,r")) (and:QI (match_dup 0) (match_operand:QI 1 "general_operand" "r,Q>,g")))] - "!TARGET_V32" + "" "@ and.b %1,%0 and.b %1,%0 and.b %1,%0" [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "*andqi_lowpart_v32" - [(set (strict_low_part - (match_operand:QI 0 "register_operand" "+r,r,r")) - (and:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "r,Q>,g")))] - "TARGET_V32" - "@ - and.b %1,%0 - and.b %1,%0 - and.b %1,%0" - [(set_attr "slottable" "yes,yes,no") - (set_attr "cc" "noov32")]) ;; Bitwise or. @@ -3047,11 +2297,11 @@ (define_expand "ior3" "" "") -(define_insn "*iorsi3_non_v32" +(define_insn "*iorsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r") (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r") (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))] - "!TARGET_V32" + "" "@ orq %2,%0 or.d %2,%0 @@ -3062,25 +2312,11 @@ (define_insn "*iorsi3_non_v32" [(set_attr "slottable" "yes,yes,yes,no,no,no") (set_attr "cc" "normal,normal,normal,clobber,normal,normal")]) -(define_insn "*iorsi3_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") - (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0") - (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))] - "TARGET_V32" - "@ - orq %2,%0 - or.d %2,%0 - or.d %2,%0 - oR.%s2 %2,%0 - or.d %2,%0" - [(set_attr "slottable" "yes,yes,yes,no,no") - (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")]) - -(define_insn "*iorhi3_non_v32" +(define_insn "*iorhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] - "!TARGET_V32" + "" "@ orq %2,%0 or.w %2,%0 @@ -3092,26 +2328,11 @@ (define_insn "*iorhi3_non_v32" [(set_attr "slottable" "yes,yes,yes,no,yes,no,no") (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")]) -(define_insn "*iorhi3_v32" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") - (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") - (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))] - "TARGET_V32" - "@ - orq %2,%0 - or.w %2,%0 - or.w %2,%0 - or.w %2,%0 - oRq %b2,%0 - or.w %2,%0" - [(set_attr "slottable" "yes,yes,yes,no,yes,no") - (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")]) - -(define_insn "*iorqi3_non_v32" +(define_insn "*iorqi3" [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] - "!TARGET_V32" + "" "@ orq %2,%0 or.b %2,%0 @@ -3121,20 +2342,6 @@ (define_insn "*iorqi3_non_v32" or.b %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")]) - -(define_insn "*iorqi3_v32" - [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") - (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))] - "TARGET_V32" - "@ - orq %2,%0 - or.b %2,%0 - or.b %2,%0 - orQ %b2,%0 - or.b %2,%0" - [(set_attr "slottable" "yes,yes,yes,yes,no") - (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")]) ;; Exclusive-or @@ -3147,8 +2354,7 @@ (define_insn "xorsi3" (match_operand:SI 2 "register_operand" "r")))] "" "xor %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) (define_insn "xor3" [(set (match_operand:BW 0 "register_operand" "=r") @@ -3205,8 +2411,7 @@ (define_insn "one_cmplsi2" (not:SI (match_operand:SI 1 "register_operand" "0")))] "" "not %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) (define_insn "one_cmpl2" [(set (match_operand:BW 0 "register_operand" "=r") @@ -3229,8 +2434,7 @@ (define_insn "si3" return "q %2,%0"; } - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Since gcc gets lost, and forgets to zero-extend the source (or mask ;; the destination) when it changes shifts of lower modes into SImode, @@ -3280,8 +2484,7 @@ (define_insn "*expanded_" (match_operand:BW 2 "register_operand" "r")))] "" " %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) (define_insn "*_lowpart" [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) @@ -3289,8 +2492,7 @@ (define_insn "*_lowpart" (match_operand:BW 1 "register_operand" "r")))] "" " %1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Arithmetic/logical shift left. @@ -3311,7 +2513,7 @@ (define_insn "ashl3" ? "lslq %2,%0" : "lsl %2,%0"); } [(set_attr "slottable" "yes") - (set_attr "cc" "noov32,clobber")]) + (set_attr "cc" "*,clobber")]) ;; A strict_low_part matcher. @@ -3321,8 +2523,7 @@ (define_insn "*ashl_lowpart" (match_operand:HI 1 "register_operand" "r")))] "" "lsl %1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Various strange insns that gcc likes. @@ -3340,8 +2541,7 @@ (define_insn "abssi2" (abs:SI (match_operand:SI 1 "register_operand" "r")))] "" "abs %1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; FIXME: GCC should be able to do these expansions itself. @@ -3359,16 +2559,14 @@ (define_insn "clzsi2" (clz:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_HAS_LZ" "lz %1,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) (define_insn "bswapsi2" [(set (match_operand:SI 0 "register_operand" "=r") (bswap:SI (match_operand:SI 1 "register_operand" "0")))] "TARGET_HAS_SWAP" "swapwb %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; This instruction swaps all bits in a register. ;; That means that the most significant bit is put in the place @@ -3380,8 +2578,7 @@ (define_insn "cris_swap_bits" CRIS_UNSPEC_SWAP_BITS))] "TARGET_HAS_SWAP" "swapwbr %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "noov32")]) + [(set_attr "slottable" "yes")]) ;; Implement ctz using two instructions, one for bit swap and one for clz. ;; Defines a scratch register to avoid clobbering input. @@ -3405,16 +2602,13 @@ (define_expand "uminsi3" (umin:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "general_operand" "")))] "" -{ - if (MEM_P (operands[2]) && TARGET_V32) - operands[2] = force_reg (SImode, operands[2]); -}) + "") -(define_insn "*uminsi3_non_v32" +(define_insn "*uminsi3" [(set (match_operand:SI 0 "register_operand" "=r,r, r,r") (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r") (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))] - "!TARGET_V32" + "" { if (CONST_INT_P (operands[2])) { @@ -3435,30 +2629,6 @@ (define_insn "*uminsi3_non_v32" return "bound.d %2,%0"; } [(set_attr "slottable" "yes,yes,no,no")]) - -(define_insn "*uminsi3_v32" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (umin:SI (match_operand:SI 1 "register_operand" "%0,0") - (match_operand:SI 2 "nonmemory_operand" "r,i")))] - "TARGET_V32" -{ - if (GET_CODE (operands[2]) == CONST_INT) - { - /* Constant operands are zero-extended, so only 32-bit operands - may be negative. */ - if (INTVAL (operands[2]) >= 0) - { - if (INTVAL (operands[2]) < 256) - return "bound.b %2,%0"; - - if (INTVAL (operands[2]) < 65536) - return "bound.w %2,%0"; - } - } - - return "bound.d %2,%0"; -} - [(set_attr "slottable" "yes,no")]) ;; Jump and branch insns. @@ -3477,22 +2647,13 @@ (define_insn "jump" (define_expand "indirect_jump" [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))] "" -{ - if (TARGET_V32 && MEM_P (operands[0])) - operands[0] = force_reg (SImode, operands[0]); -}) + "") -(define_insn "*indirect_jump_non_v32" +(define_insn "*indirect_jump" [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] - "!TARGET_V32" + "" "jump %0") -(define_insn "*indirect_jump_v32" - [(set (pc) (match_operand:SI 0 "register_operand" "r"))] - "TARGET_V32" - "jump %0%#" - [(set_attr "slottable" "has_slot")]) - ;; Return insn. Used whenever the epilogue is very simple; if it is only ;; a single ret or jump [sp+]. No allocated stack space or saved ;; registers are allowed. @@ -3551,12 +2712,7 @@ (define_expand "cbranchdi4" (label_ref (match_operand 3 "" "")) (pc)))] "" -{ - if (TARGET_V32 && !REG_P (operands[1])) - operands[1] = force_reg (DImode, operands[1]); - if (TARGET_V32 && MEM_P (operands[2])) - operands[2] = force_reg (DImode, operands[2]); -}) + "") ;; We suffer from the same overflow-bit-gets-in-the-way problem as @@ -3651,12 +2807,7 @@ (define_expand "cstoredi4" (match_operator:SI 1 "ordered_comparison_operator" [(cc0) (const_int 0)]))] "" -{ - if (TARGET_V32 && !REG_P (operands[2])) - operands[2] = force_reg (DImode, operands[2]); - if (TARGET_V32 && MEM_P (operands[3])) - operands[3] = force_reg (DImode, operands[3]); -}) + "") (define_expand "cstore4" [(set (cc0) (compare @@ -3713,73 +2864,31 @@ (define_insn "s" ;; instructions is a different issue. (define_expand "call" - [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "") - (match_operand 1 "general_operand" "")) + [(parallel [(call (match_operand:SI 0 "indirect_operand") + (match_operand 1 "general_operand")) (clobber (reg:SI CRIS_SRP_REGNUM))])] "" { - gcc_assert (MEM_P (operands[0])); - if (flag_pic) - cris_expand_pic_call_address (&operands[0], &operands[1]); - else - operands[1] = const0_rtx; + operands[1] = const0_rtx; }) ;; Accept operands for operand 0 in order of preference. -(define_insn "*expanded_call_non_v32" +(define_insn "*expanded_call" [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g")) - (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM")) + (const_int 0)) (clobber (reg:SI CRIS_SRP_REGNUM))] - "!TARGET_V32" + "" "jsr %0") -(define_insn "*expanded_call_v32" - [(call - (mem:QI - (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i")) - (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM,rM")) - (clobber (reg:SI CRIS_SRP_REGNUM))] - "TARGET_V32" - "@ - jsr %0%# - jsr %0%# - bsr %0%# - bsr %0%#" - [(set_attr "slottable" "has_call_slot")]) - -;; Parallel when calculating and reusing address of indirect pointer -;; with simple offset. (Makes most sense with PIC.) It looks a bit -;; wrong not to have the clobber last, but that's the way combine -;; generates it (except it doesn't look into the *inner* mem, so this -;; just matches a peephole2). FIXME: investigate that. -(define_insn "*expanded_call_side" - [(call (mem:QI - (mem:SI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn")))) - (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM")) - (clobber (reg:SI CRIS_SRP_REGNUM)) - (set (match_operand:SI 3 "register_operand" "=*0,r,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - ;; Disabled until after reload until we can avoid an output reload for - ;; operand 3 (being forbidden for call insns). - "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32" - "jsr [%3=%0%S1]") - (define_expand "call_value" - [(parallel [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "cris_mem_call_operand" "") - (match_operand 2 "" ""))) + [(parallel [(set (match_operand 0 "") + (call (match_operand:SI 1 "indirect_operand") + (match_operand 2 ""))) (clobber (reg:SI CRIS_SRP_REGNUM))])] "" { - gcc_assert (MEM_P (operands[1])); - if (flag_pic) - cris_expand_pic_call_address (&operands[1], &operands[2]); - else - operands[2] = const0_rtx; + operands[2] = const0_rtx; }) ;; The validity other than "general" of @@ -3788,51 +2897,15 @@ (define_expand "call_value" ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather ;; than requiring getting rPIC + sym:PLT into a register. -(define_insn "*expanded_call_value_non_v32" +(define_insn "*expanded_call_value" [(set (match_operand 0 "nonimmediate_operand" "=g,g,g") (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g")) - (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM"))) + (const_int 0))) (clobber (reg:SI CRIS_SRP_REGNUM))] - "!TARGET_V32" + "" "Jsr %1" [(set_attr "cc" "clobber")]) -;; See similar call special-case. -(define_insn "*expanded_call_value_side" - [(set (match_operand 0 "nonimmediate_operand" "=g,g,g") - (call - (mem:QI - (mem:SI - (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) - (match_operand:SI 3 "cris_call_type_marker" "rM,rM,rM"))) - (clobber (reg:SI CRIS_SRP_REGNUM)) - (set (match_operand:SI 4 "register_operand" "=*1,r,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - ;; Disabled until after reload until we can avoid an output reload for - ;; operand 4 (being forbidden for call insns). - "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32" - "Jsr [%4=%1%S2]" - [(set_attr "cc" "clobber")]) - -(define_insn "*expanded_call_value_v32" - [(set - (match_operand 0 "nonimmediate_operand" "=g,g,g,g") - (call - (mem:QI - (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i")) - (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM,rM"))) - (clobber (reg:SI 16))] - "TARGET_V32" - "@ - Jsr %1%# - Jsr %1%# - Bsr %1%# - Bsr %1%#" - [(set_attr "cc" "clobber") - (set_attr "slottable" "has_call_slot")]) - ;; Used in debugging. No use for the direct pattern; unfilled ;; delayed-branches are taken care of by other means. @@ -3842,9 +2915,9 @@ (define_insn "nop" "nop" [(set_attr "cc" "none")]) -;; Same as the gdb trap breakpoint, will cause a SIGTRAP for -;; cris-linux* and crisv32-linux*, as intended. Will work in -;; freestanding environments with sufficient framework. +;; Same as the gdb trap breakpoint: would cause a SIGTRAP for +;; cris-linux* and will work in freestanding environments with +;; sufficient framework. (define_insn "trap" [(trap_if (const_int 1) (const_int 8))] "TARGET_TRAP_USING_BREAK8" @@ -3871,7 +2944,7 @@ (define_insn "cris_frame_deallocated_barrier" ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END ;; accordingly, to add the default case at the end of the jump-table. -(define_expand "cris_casesi_non_v32" +(define_expand "casesi" [(set (match_dup 5) (match_operand:SI 0 "general_operand" "")) (set (match_dup 6) (minus:SI (match_dup 5) @@ -3897,62 +2970,6 @@ (define_expand "cris_casesi_non_v32" operands[6] = gen_reg_rtx (SImode); operands[7] = gen_reg_rtx (SImode); }) - -;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION. -(define_expand "cris_casesi_v32" - [(set (match_dup 5) (match_operand:SI 0 "general_operand")) - (set (match_dup 6) - (minus:SI (match_dup 5) - (match_operand:SI 1 "const_int_operand"))) - (set (match_dup 7) - (umin:SI (match_dup 6) - (match_operand:SI 2 "const_int_operand"))) - (set (match_dup 8) (match_dup 11)) - (set (match_dup 9) - (plus:SI (mult:SI (match_dup 7) (const_int 2)) - (match_dup 8))) - (set (match_dup 10) - (plus:SI (sign_extend:SI (mem:HI (match_dup 9))) - (match_dup 9))) - (parallel - [(set (pc) - (if_then_else - (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2)) - (match_dup 10) - (label_ref (match_operand 4 "" "")))) - (use (label_ref (match_dup 3)))])] - "TARGET_V32" -{ - int i; - rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]); - for (i = 5; i <= 10; i++) - operands[i] = gen_reg_rtx (SImode); - operands[2] = plus_constant (SImode, operands[2], 1); - - /* Don't forget to decorate labels too, for PIC. */ - operands[11] = flag_pic - ? gen_rtx_CONST (Pmode, - gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel), - CRIS_UNSPEC_PCREL)) - : xlabel; -}) - -(define_expand "casesi" - [(match_operand:SI 0 "general_operand") - (match_operand:SI 1 "const_int_operand") - (match_operand:SI 2 "const_int_operand") - (match_operand 3 "" "") - (match_operand 4 "" "")] - "" -{ - if (TARGET_V32) - emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2], - operands[3], operands[4])); - else - emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2], - operands[3], operands[4])); - DONE; -}) ;; Split-patterns. Some of them have modes unspecified. This ;; should always be ok; if for no other reason sparc.md has it as @@ -3973,8 +2990,6 @@ (define_expand "casesi" ;; op [rx],rz ;; Lose if rz=ry or rx=rz. ;; Call this op-extend-split. -;; Do not match for V32; the addo and addi shouldn't be split -;; up. (define_split [(set (match_operand 0 "cris_nonsp_register_operand" "") @@ -3984,8 +2999,7 @@ (define_split (match_operator 3 "cris_extend_operator" [(match_operand 2 "memory_operand" "")])]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4014,8 +3028,7 @@ (define_split (match_operator 3 "cris_extend_operator" [(match_operand 2 "memory_operand" "")])]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4042,8 +3055,7 @@ (define_split 3 "cris_extend_operator" [(match_operand 2 "memory_operand" "")]) (match_operand 1 "register_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4068,8 +3080,7 @@ (define_split 3 "cris_extend_operator" [(match_operand 2 "memory_operand" "")]) (match_operand 1 "register_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4097,8 +3108,7 @@ (define_split 3 "cris_orthogonal_operator" [(match_operand 1 "register_operand" "") (match_operand 2 "memory_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4121,8 +3131,7 @@ (define_split 3 "cris_commutative_orth_op" [(match_operand 2 "memory_operand" "") (match_operand 1 "register_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD @@ -4145,8 +3154,7 @@ (define_split 3 "cris_commutative_orth_op" [(match_operand 1 "register_operand" "") (match_operand 2 "memory_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) && REG_P (operands[1]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && REG_P (XEXP (operands[2], 0)) @@ -4168,8 +3176,7 @@ (define_split 3 "cris_orthogonal_operator" [(match_operand 2 "memory_operand" "") (match_operand 1 "register_operand" "")]))] - "!TARGET_V32 - && REG_P (operands[0]) && REG_P (operands[1]) + "REG_P (operands[0]) && REG_P (operands[1]) && REGNO (operands[1]) != REGNO (operands[0]) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && REG_P (XEXP (operands[2], 0)) @@ -4846,7 +3853,7 @@ (define_peephole2 ; moverside (peephole casesi+38) /* Make sure we have canonical RTX so we match the insn pattern - not a constant in the first operand. We also require the order (plus reg mem) to match the final pattern. */ - if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop)) + if (CONSTANT_P (otherop) || MEM_P (otherop)) { operands[7] = operands[1]; operands[8] = otherop; @@ -4897,7 +3904,7 @@ (define_peephole2 ; movemside (peephole casesi+39) /* Make sure we have canonical RTX so we match the insn pattern - not a constant in the first operand. We also require the order (plus reg mem) to match the final pattern. */ - if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop)) + if (CONSTANT_P (otherop) || MEM_P (otherop)) { operands[7] = operands[1]; operands[8] = otherop; @@ -5042,127 +4049,6 @@ (define_peephole2 ; andqu (casesi+46) operands[3] = gen_rtx_ZERO_EXTEND (SImode, op1); operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode)); }) - -;; Try and avoid GOTPLT reads escaping a call: transform them into -;; PLT. Curiously (but thankfully), peepholes for instructions -;; *without side-effects* that just feed a call (or call_value) are -;; not matched neither in a build or test-suite, so those patterns are -;; omitted. - -;; A "normal" move where we don't check the consumer. - -(define_peephole2 ; gotplt-to-plt - [(set - (match_operand:SI 0 "register_operand" "") - (match_operator:SI - 1 "cris_mem_op" - [(plus:SI - (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")] - CRIS_UNSPEC_PLTGOTREAD)))]))] - "flag_pic - && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) - && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)" - [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL))) - (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))] - "") - -;; And one set with a side-effect getting the PLTGOT offset. -;; First call and call_value variants. - -(define_peephole2 ; gotplt-to-plt-side-call - [(parallel - [(set - (match_operand:SI 0 "register_operand" "") - (match_operator:SI - 1 "cris_mem_op" - [(plus:SI - (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_operand:SI - 2 "cris_general_operand_or_symbol" "")] - CRIS_UNSPEC_PLTGOTREAD)))])) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))]) - (parallel [(call (mem:QI (match_dup 0)) - (match_operand 4 "" "")) - (clobber (reg:SI CRIS_SRP_REGNUM))])] - "flag_pic - && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) - && peep2_reg_dead_p (2, operands[0])" - [(parallel [(call (mem:QI (match_dup 1)) - (match_dup 4)) - (clobber (reg:SI CRIS_SRP_REGNUM)) - (set (match_dup 3) - (plus:SI (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_dup 2)] - CRIS_UNSPEC_PLTGOTREAD))))])] - "") - -(define_peephole2 ; gotplt-to-plt-side-call-value - [(parallel - [(set - (match_operand:SI 0 "register_operand" "") - (match_operator:SI - 1 "cris_mem_op" - [(plus:SI - (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_operand:SI - 2 "cris_general_operand_or_symbol" "")] - CRIS_UNSPEC_PLTGOTREAD)))])) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))]) - (parallel [(set (match_operand 5 "" "") - (call (mem:QI (match_dup 0)) - (match_operand 4 "" ""))) - (clobber (reg:SI CRIS_SRP_REGNUM))])] - "flag_pic - && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) - && peep2_reg_dead_p (2, operands[0])" - [(parallel [(set (match_dup 5) - (call (mem:QI (match_dup 1)) - (match_dup 4))) - (clobber (reg:SI CRIS_SRP_REGNUM)) - (set (match_dup 3) - (plus:SI (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_dup 2)] - CRIS_UNSPEC_PLTGOTREAD))))])] - "") - -(define_peephole2 ; gotplt-to-plt-side - [(parallel - [(set - (match_operand:SI 0 "register_operand" "") - (match_operator:SI - 1 "cris_mem_op" - [(plus:SI - (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_operand:SI - 2 "cris_general_operand_or_symbol" "")] - CRIS_UNSPEC_PLTGOTREAD)))])) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (reg:SI CRIS_GOT_REGNUM) - (const:SI - (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])] - "flag_pic - && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true) - && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)" - [(set (match_dup 3) - (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))) - (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM))) - (set (match_dup 0) - (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL))) - (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))] - "") ;; Local variables: ;; mode:emacs-lisp diff --git a/gcc/config/cris/cris.opt b/gcc/config/cris/cris.opt index e216599912a..e574a0a4dbc 100644 --- a/gcc/config/cris/cris.opt +++ b/gcc/config/cris/cris.opt @@ -196,7 +196,3 @@ Mask(SVINTO) ; TARGET_ALIGN_BY_32: Say that all alignment specifications say ; to prefer 32 rather than 16 bits. Mask(ALIGN_BY_32) - -; TARGET_AVOID_GOTPLT is referred to in the .c and the .md so we -; need to allocate the flag and macros here. -Mask(AVOID_GOTPLT) diff --git a/gcc/config/cris/predicates.md b/gcc/config/cris/predicates.md index 93435e644c1..1fa22cda466 100644 --- a/gcc/config/cris/predicates.md +++ b/gcc/config/cris/predicates.md @@ -61,9 +61,7 @@ (define_predicate "cris_store_multiple_op" ;; Operand helper predicates. (define_predicate "cris_bdap_const_operand" - (and (match_code "label_ref, symbol_ref, const_int, const_double, const") - (ior (not (match_test "flag_pic")) - (match_test "cris_valid_pic_const (op, true)")))) + (match_operand 0 "immediate_operand")) (define_predicate "cris_simple_address_operand" (ior (match_operand:SI 0 "register_operand") @@ -132,59 +130,3 @@ (define_predicate "cris_bdap_operand" (define_predicate "cris_bdap_biap_operand" (ior (match_operand 0 "cris_bdap_operand") (match_operand 0 "cris_biap_mult_operand"))) - -;; Since with -fPIC, not all symbols are valid PIC symbols or indeed -;; general_operands, we have to have a predicate that matches it for the -;; "movsi" expander. -;; FIXME: Can s/special_// when PR 20413 is fixed. - -(define_special_predicate "cris_general_operand_or_symbol" - (ior (match_operand 0 "general_operand") - (and (match_code "const, symbol_ref, label_ref") - ; The following test is actually just an assertion. - (match_test "cris_symbol_type_of (op) != cris_no_symbol")))) - -;; A predicate for the anon movsi expansion, one that fits a PCREL -;; operand as well as general_operand. - -(define_special_predicate "cris_general_operand_or_pic_source" - (ior (match_operand 0 "general_operand") - (and (match_test "flag_pic") - (match_test "cris_valid_pic_const (op, false)")))) - -;; Since a PLT symbol is not a general_operand, we have to have a -;; predicate that matches it when we need it. We use this in the expanded -;; "call" and "call_value" anonymous patterns. - -(define_predicate "cris_nonmemory_operand_or_callable_symbol" - (ior (match_operand 0 "nonmemory_operand") - (and (match_code "const") - (and - (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") - (ior - (match_test "XINT (XEXP (op, 0), 1) == CRIS_UNSPEC_PLT_PCREL") - (match_test "XINT (XEXP (op, 0), 1) == CRIS_UNSPEC_PCREL")))))) - -;; This matches a (MEM (general_operand)) or -;; (MEM (cris_general_operand_or_symbol)). The second one isn't a valid -;; memory_operand, so we need this predicate to recognize call -;; destinations before we change them to a PLT operand (by wrapping in -;; UNSPEC CRIS_UNSPEC_PLT). - -(define_predicate "cris_mem_call_operand" - (and (match_code "mem") - (ior (match_operand 0 "memory_operand") - (match_test "cris_general_operand_or_symbol (XEXP (op, 0), - Pmode)")))) - -;; A marker for the call-insn: (const_int 0) for a call to a -;; hidden or static function and non-pic and -;; pic_offset_table_rtx for a call that *might* go through the -;; PLT. - -(define_predicate "cris_call_type_marker" - (ior (and (match_operand 0 "const_int_operand") - (match_test "op == const0_rtx")) - (and (and (match_operand 0 "register_operand") - (match_test "op == pic_offset_table_rtx")) - (match_test "flag_pic != 0")))) diff --git a/gcc/config/cris/sync.md b/gcc/config/cris/sync.md index 2e774577b82..d5bb11ddbcf 100644 --- a/gcc/config/cris/sync.md +++ b/gcc/config/cris/sync.md @@ -22,17 +22,12 @@ ;; ;; - Plain old CRIS v0 (..v8) ;; - CRIS v10 (as used in ETRAX 100 LX) -;; - CRIS v32 (as used in ETRAX FS) ;; -;; The last two alternatives are similar, of LL/SC type. They may +;; The second alternative is of LL/SC type. It may ;; fail for other reasons; an exception, a cache miss or a bus request -;; from other parts of the system. The difference between them is -;; just in what condition-codes are used to track LL and success or -;; failure for the store. See the chapter on integral read-write +;; from other parts of the system. See the chapter on integral read-write ;; operations, chapter 1.13 in "ETRAX 100LX Programmers Manual", -;; -;; and chapter 2.1 in "ETRAX FS Designer's reference", -;; . +;; . ;; Note that the datum being stored has to be contained fully within a ;; cache-line to be integral. A failure to store the data integrally ;; will be flagged, but the store may still have happened in part, @@ -134,18 +129,7 @@ (define_insn "cris_atomic_fetch__1" /* Can't be too sure; better ICE if this happens. */ gcc_assert (!reg_overlap_mentioned_p (operands[2], operands[1])); - if (TARGET_V32) - return - "clearf p\n" - ".Lsync.%=:\;" - "move %1,%0\;" - "move.d %0,%3\;" - ",%3\;" - "ax\;" - "move %3,%1\;" - "bcs .Lsync.%=\;" - "clearf p"; - else if (cris_cpu_version == 10) + if (cris_cpu_version == 10) return "clearf\n" ".Lsync.%=:\;" @@ -245,20 +229,7 @@ (define_insn "cris_atomic_compare_and_swap_1" CRIS_UNSPEC_ATOMIC_SWAP_MEM))] "mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS" { - if (TARGET_V32) - return - "\n.Lsync.repeat.%=:\;" - "clearf p\;" - "move %2,%1\;" - "cmp %3,%1\;" - "bne .Lsync.after.%=\;" - "ax\;" - - "move %4,%2\;" - "bcs .Lsync.repeat.%=\n" - ".Lsync.after.%=:\;" - "seq %0"; - else if (cris_cpu_version == 10) + if (cris_cpu_version == 10) return "\n.Lsync.repeat.%=:\;" "clearf\;" From patchwork Wed Jan 22 06:11:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517973-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=NWf5E/3D; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482Zmz5NxYz9sRR for ; Wed, 22 Jan 2020 17:12:03 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=LHw+nJjX+OwexbeY ELeCC/gNnW7+3mWvqgbgljiTdLUQFWGLHFrHnzprCgoySh/kBEF+FPvuK5BjHkmA H28dd2ytBloh33eDozDOC5+kPGP8GuySG4/mJwPkwg/CQFQsiY/YB2oB94199D7c xy+LMRT1DaD8h6H1C5gqC0mWtvA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=gnl7vfx0YLt+EbWcwhvlBw tuYGk=; b=NWf5E/3DGivz1rcrT7UMyDE6BvJWY9nMs69FrZ7HyGH8TGBSLAj4Ej UIbjHM1hP5mmYDWpdFXit6S0nwadg39m8j3E+T/oIdV08SPrlgZSebF72XNgpKcP Mgr0uEYVDSYzi7N3fv2NJRjAOO+y+E2LLY2fguSfylkzfs0oKXnVI= Received: (qmail 72921 invoked by alias); 22 Jan 2020 06:11:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 72910 invoked by uid 89); 22 Jan 2020 06:11:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp1.axis.com Received: from smtp1.axis.com (HELO smtp1.axis.com) (195.60.68.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:11:31 +0000 IronPort-SDR: OF3NnhysDQV74ISAy1eVR2rQw11jVK61+qCSoUxT40dTybReLHVdFPkkw21gSr0Jp9Y1rUKr1I 8+ExgvKHY3m9/4ocIxNV9IeB1gN7aaEQt21S2Jon/0sMVl7CXL9l/5vIU+Ot5wmwVdwbj81zHl kfPPjaLID0wVGdaPCGr/Nmwti0rfGx3SW9DsIUe+sAy+6uprgmVa6dFSvUI3BOiMOv0ewIYy6E zYbm7+RT2FTbGbcPfaE+zLJvWzkzwaY3L5RQiBYBu0C8gRPcgxZjmB9haHRQBzeLIPguQ6FBU5 2HQ= Date: Wed, 22 Jan 2020 07:11:27 +0100 Message-ID: <202001220611.00M6BRr8018258@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 8/9] cris: Move trivially from cc0 to reg:CC model, removing most optimizations. MIME-Version: 1.0 X-IsSubscribed: yes gcc: Move trivially from cc0 to reg:CC model, removing most optimizations. * config/cris/cris.md: Remove all side-effect patterns and their splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM to all but post-reload control-flow and movem insns. Remove constraints on all modified expanders. Remove obsoleted cc0-related references. (attr "cc"): Remove alternative "rev". (mode_iterator BWDD, DI_, SI_): New. (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New. ("tst"): Remove; fold as "M" alternative into compare insn. ("mstep_shift", "mstep_mul"): Remove patterns. ("s", "s", "s"): Anonymize. * config/cris/cris.c: Change all non-condition-code, non-control-flow emitted insns to add a parallel with clobber of CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with emit_insn to use of emit_move_insn, gen_add2_insn or cris_emit_insn, as convenient. (cris_reg_overlap_mentioned_p) (cris_normal_notice_update_cc, cris_notice_update_cc): Remove. (cris_movem_load_rest_p): Don't assume all elements in a PARALLEL are SETs. (cris_store_multiple_op_p): Ditto. (cris_emit_insn): New function. * cris/cris-protos.h (cris_emit_insn): Declare. In the parlance of , this is a basic "type 2" conversion, without condition-code-related optimizations (just plain CCmode), but with "cstore{M}4" defined. CRIS is somewhat similar to the m68k; most instructions affect condition-codes. To wit, it lacks sufficient instructions to compose an arbitrary valid address in a register, specifically from a valid address where involved registers have to be spilled or adjusted, without affecting condition-codes in CRIS_CC0_REGNUM aka. dccr. On the other hand, moving dccr to and from a stackpointer-plus- constant-offset-address *can* be done without additional register use, and moving to or from a general register does not affect it. There's no instruction to add a constant to a register or to put a constant in a register, without affecting dccr, but there *is* an instruction to add a register (optionally scaled) to another without affecting dccr (i.e. "addi"). Also, moves *to* memory from any register do not affect dccr, and likewise between another special registers and a general register. Maybe some of that opens up the solution-space to a better solution than clobbering dccr until reload_completed; to be investigated. FAOD: I know what to do in the direction of defining and using additional CCmodes, but prefer to do the full transition in smaller steps. Regarding the similarity to m68k, I didn't follow the steps of the m68k cc0 transition, making use of the final_postscan_insn hook as with the a NOTICE_UPDATE_CC machinery. For one, because it seems to be lacking in that it keeps compare-elimination restricted to output-time, but also because it seems a bad match considering that CRIS has delay-slots; better try to eliminate compares earlier. Another approach which I originally intended to implement, that of the visium port of defining three variants for most insns (not counting the define_subst expansions; unaffecting-before-reload, clobbering and setting), seems overworked and bloating the machine description. I may be proven wrong, but I prefer we fix gcc if some something bails on seeing a parallel with a clobber of that specific hard-register. Also, I chose to remove most anonymous combination-matching patterns; matchers, splitters and peepholes instead of converting them to add clobbers of CRIS_CC0_REGNUM. There are exclusions: those covered in the test-suite, if trivial enough. Many of these patterns are used to handle the side-effect- assignment addressing-modes as put together by combine: a "prefix instruction" before the main instruction, where the main instruction uses the post-incremented-register addressing-mode and the "left-over" instruction-field in the prefixed insn to assign a register. An example: the hopefully descriptive "move.d $r9,[$r0=$r1+1234]" compared to "move.d $r9,[$r1+1234]"; both formed by the prefix insn "biap.w 1234,$r1" before respectively "move.d $r9,[$r0+]" and "move.d $r9,[$r0]". Other prefix variants exist. Useful, but optional, except where side-effect assignment was used in a special case in the function prologue; adjusted to a less optimal combination. Support like the function cris_side_effect_mode_ok is kept. I intend to put back as many as I find use for, of those anonymous patterns in a controlled manner, with self-contained test-cases proving their usability, rather than symmetry with other instructions and similar addressing modes, which guided the original introduction. I've entered prXXXXX to track code performance regressions related to this transition, with focus on target-side causes and fixes; besides the function prologue special-case, there were some checking presence of the bit-test (btstq) instruction. The now-gone "tst" patterns deserve a comment too: they were an artefact from pre-"cbranch" era, now fully folded into the "cmp" patterns. I've left the now-unused "cc" insn attribute in, for the time being; to be removed, used or transformed to be useful with further work to fix prXXXXX. It can't be used as is, because "normal" doesn't mean "like a compare instruction" but "handled by NOTICE_UPDATE_CC" and may in fact be reflecting e.g. reverse operands, something that bit me during the conversion. --- gcc/config/cris/cris-protos.h | 5 +- gcc/config/cris/cris.c | 539 ++------- gcc/config/cris/cris.h | 7 +- gcc/config/cris/cris.md | 2594 ++++++++--------------------------------- gcc/config/cris/predicates.md | 2 +- gcc/config/cris/sync.md | 6 +- 6 files changed, 585 insertions(+), 2568 deletions(-) diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index 98b24a26bb0..5137d99d47d 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -35,11 +35,12 @@ extern bool cris_bdap_index_p (const_rtx, bool); extern bool cris_biap_index_p (const_rtx, bool); extern bool cris_legitimate_address_p (machine_mode, rtx, bool); extern bool cris_store_multiple_op_p (rtx); -extern bool cris_movem_load_rest_p (rtx, int); +extern bool cris_movem_load_rest_p (rtx); extern void cris_asm_output_symbol_ref (FILE *, rtx); extern void cris_asm_output_case_end (FILE *, int, rtx_insn *); -extern rtx cris_gen_movem_load (rtx, rtx, int); +extern rtx cris_gen_movem_load (rtx, rtx); extern rtx cris_emit_movem_store (rtx, rtx, int, bool); +extern rtx_insn *cris_emit_insn (rtx x); extern void cris_order_for_addsi3 (rtx *, int); extern void cris_emit_trap_for_misalignment (rtx); #endif /* RTX_CODE */ diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 2f1deae2711..2a0ce3e6513 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -90,9 +90,6 @@ static char cris_output_insn_is_bound = 0; goes in code or in a static initializer. */ static int in_code = 0; -/* Fix for reg_overlap_mentioned_p. */ -static int cris_reg_overlap_mentioned_p (rtx, rtx); - static machine_mode cris_promote_function_mode (const_tree, machine_mode, int *, const_tree, int); @@ -290,9 +287,9 @@ struct gcc_target targetm = TARGET_INITIALIZER; /* Helper for cris_load_multiple_op and cris_ret_movem_op. */ bool -cris_movem_load_rest_p (rtx op, int offs) +cris_movem_load_rest_p (rtx op) { - unsigned int reg_count = XVECLEN (op, 0) - offs; + unsigned int reg_count = XVECLEN (op, 0); rtx src_addr; int i; rtx elt; @@ -303,35 +300,36 @@ cris_movem_load_rest_p (rtx op, int offs) /* Perform a quick check so we don't blow up below. FIXME: Adjust for other than (MEM reg). */ if (reg_count <= 1 - || GET_CODE (XVECEXP (op, 0, offs)) != SET - || !REG_P (SET_DEST (XVECEXP (op, 0, offs))) - || !MEM_P (SET_SRC (XVECEXP (op, 0, offs)))) + || GET_CODE (XVECEXP (op, 0, 0)) != SET + || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) + || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))) return false; /* Check a possible post-inc indicator. */ - if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS) + if (GET_CODE (XVECEXP (op, 0, 1)) == SET + && GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) { - rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0); - rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1); + rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); + rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); reg_count--; if (reg_count == 1 || !REG_P (reg) - || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1))) - || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1))) + || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) + || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) || !CONST_INT_P (inc) || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4) return false; - i = offs + 2; + i = 2; } else - i = offs + 1; + i = 1; regno_dir = -1; regno = reg_count - 1; - elt = XVECEXP (op, 0, offs); + elt = XVECEXP (op, 0, 0); src_addr = XEXP (SET_SRC (elt), 0); if (GET_CODE (elt) != SET @@ -399,15 +397,15 @@ cris_store_multiple_op_p (rtx op) dest_addr = XEXP (dest, 0); /* Check a possible post-inc indicator. */ - if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) + if (GET_CODE (XVECEXP (op, 0, 1)) == SET + && GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS) { rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0); rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1); reg_count--; - if (reg_count == 1 - || !REG_P (reg) + if (!REG_P (reg) || !REG_P (SET_DEST (XVECEXP (op, 0, 1))) || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1))) || !CONST_INT_P (inc) @@ -1501,302 +1499,6 @@ cris_memory_move_cost (machine_mode mode, return 6; } -/* Worker for cris_notice_update_cc; handles the "normal" cases. - FIXME: this code is historical; its functionality should be - refactored to look at insn attributes and moved to - cris_notice_update_cc. Except, we better lose cc0 entirely. */ - -static void -cris_normal_notice_update_cc (rtx exp, rtx insn) -{ - /* "Normal" means, for: - (set (cc0) (...)): - CC is (...). - - (set (reg) (...)): - CC is (reg) and (...) - unless (...) is 0 or reg is a special - register, then CC does not change. - CC_NO_OVERFLOW unless (...) is reg or mem. - - (set (mem) (...)): - CC does not change. - - (set (pc) (...)): - CC does not change. - - (parallel - (set (reg1) (mem (bdap/biap))) - (set (reg2) (bdap/biap))): - CC is (reg1) and (mem (reg2)) - - (parallel - (set (mem (bdap/biap)) (reg1)) [or 0] - (set (reg2) (bdap/biap))): - CC does not change. - - (where reg and mem includes strict_low_parts variants thereof) - - For all others, assume CC is clobbered. - Note that we do not have to care about setting CC_NO_OVERFLOW, - since the overflow flag is set to 0 (i.e. right) for - instructions where it does not have any sane sense, but where - other flags have meanings. (This includes shifts; the carry is - not set by them). - - Note that there are other parallel constructs we could match, - but we don't do that yet. */ - - if (GET_CODE (exp) == SET) - { - /* FIXME: Check when this happens. It looks like we should - actually do a CC_STATUS_INIT here to be safe. */ - if (SET_DEST (exp) == pc_rtx) - return; - - /* Record CC0 changes, so we do not have to output multiple - test insns. */ - if (SET_DEST (exp) == cc0_rtx) - { - CC_STATUS_INIT; - - if (GET_CODE (SET_SRC (exp)) == COMPARE - && XEXP (SET_SRC (exp), 1) == const0_rtx) - cc_status.value1 = XEXP (SET_SRC (exp), 0); - else - cc_status.value1 = SET_SRC (exp); - - /* Handle flags for the special btstq on one bit. */ - if (GET_CODE (cc_status.value1) == ZERO_EXTRACT - && XEXP (cc_status.value1, 1) == const1_rtx) - { - if (CONST_INT_P (XEXP (cc_status.value1, 0))) - /* Using cmpq. */ - cc_status.flags = CC_INVERTED; - else - /* A one-bit btstq. */ - cc_status.flags = CC_Z_IN_NOT_N; - } - - else if (GET_CODE (SET_SRC (exp)) == COMPARE) - { - if (!REG_P (XEXP (SET_SRC (exp), 0)) - && XEXP (SET_SRC (exp), 1) != const0_rtx) - /* For some reason gcc will not canonicalize compare - operations, reversing the sign by itself if - operands are in wrong order. */ - /* (But NOT inverted; eq is still eq.) */ - cc_status.flags = CC_REVERSED; - - /* This seems to be overlooked by gcc. FIXME: Check again. - FIXME: Is it really safe? */ - cc_status.value2 - = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)), - XEXP (SET_SRC (exp), 0), - XEXP (SET_SRC (exp), 1)); - } - return; - } - else if (REG_P (SET_DEST (exp)) - || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART - && REG_P (XEXP (SET_DEST (exp), 0)))) - { - /* A register is set; normally CC is set to show that no - test insn is needed. Catch the exceptions. */ - - /* If not to cc0, then no "set"s in non-natural mode give - ok cc0... */ - if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD - || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT) - { - /* ... except add:s and sub:s in DImode. */ - if (GET_MODE (SET_DEST (exp)) == DImode - && (GET_CODE (SET_SRC (exp)) == PLUS - || GET_CODE (SET_SRC (exp)) == MINUS)) - { - CC_STATUS_INIT; - cc_status.value1 = SET_DEST (exp); - cc_status.value2 = SET_SRC (exp); - - if (cris_reg_overlap_mentioned_p (cc_status.value1, - cc_status.value2)) - cc_status.value2 = 0; - - /* Add and sub may set V, which gets us - unoptimizable results in "gt" and "le" condition - codes. */ - cc_status.flags |= CC_NO_OVERFLOW; - - return; - } - } - else if (SET_SRC (exp) == const0_rtx - || (REG_P (SET_SRC (exp)) - && (REGNO (SET_SRC (exp)) - > CRIS_LAST_GENERAL_REGISTER))) - { - /* There's no CC0 change for this case. Just check - for overlap. */ - if (cc_status.value1 - && modified_in_p (cc_status.value1, insn)) - cc_status.value1 = 0; - - if (cc_status.value2 - && modified_in_p (cc_status.value2, insn)) - cc_status.value2 = 0; - - return; - } - else - { - CC_STATUS_INIT; - cc_status.value1 = SET_DEST (exp); - cc_status.value2 = SET_SRC (exp); - - if (cris_reg_overlap_mentioned_p (cc_status.value1, - cc_status.value2)) - cc_status.value2 = 0; - - /* Some operations may set V, which gets us - unoptimizable results in "gt" and "le" condition - codes. */ - if (GET_CODE (SET_SRC (exp)) == PLUS - || GET_CODE (SET_SRC (exp)) == MINUS - || GET_CODE (SET_SRC (exp)) == NEG) - cc_status.flags |= CC_NO_OVERFLOW; - - return; - } - } - else if (MEM_P (SET_DEST (exp)) - || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART - && MEM_P (XEXP (SET_DEST (exp), 0)))) - { - /* When SET to MEM, then CC is not changed (except for - overlap). */ - if (cc_status.value1 - && modified_in_p (cc_status.value1, insn)) - cc_status.value1 = 0; - - if (cc_status.value2 - && modified_in_p (cc_status.value2, insn)) - cc_status.value2 = 0; - - return; - } - } - else if (GET_CODE (exp) == PARALLEL) - { - if (GET_CODE (XVECEXP (exp, 0, 0)) == SET - && GET_CODE (XVECEXP (exp, 0, 1)) == SET - && REG_P (XEXP (XVECEXP (exp, 0, 1), 0))) - { - if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0)) - && MEM_P (XEXP (XVECEXP (exp, 0, 0), 1))) - { - CC_STATUS_INIT; - - /* For "move.S [rx=ry+o],rz", say CC reflects - value1=rz and value2=[rx] */ - cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); - cc_status.value2 - = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1), - XEXP (XVECEXP (exp, 0, 1), 0)); - - /* Huh? A side-effect cannot change the destination - register. */ - if (cris_reg_overlap_mentioned_p (cc_status.value1, - cc_status.value2)) - internal_error ("internal error: sideeffect-insn affecting main effect"); - return; - } - else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1)) - || XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx) - && MEM_P (XEXP (XVECEXP (exp, 0, 0), 0))) - { - /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]", - say flags are not changed, except for overlap. */ - if (cc_status.value1 - && modified_in_p (cc_status.value1, insn)) - cc_status.value1 = 0; - - if (cc_status.value2 - && modified_in_p (cc_status.value2, insn)) - cc_status.value2 = 0; - - return; - } - } - } - - /* If we got here, the case wasn't covered by the code above. */ - CC_STATUS_INIT; -} - -/* This function looks into the pattern to see how this insn affects - condition codes. - - Used when to eliminate test insns before a condition-code user, - such as a "scc" insn or a conditional branch. This includes - checking if the entities that cc was updated by, are changed by the - operation. - - Currently a jumble of the old peek-inside-the-insn and the newer - check-cc-attribute methods. */ - -void -cris_notice_update_cc (rtx exp, rtx_insn *insn) -{ - enum attr_cc attrval = get_attr_cc (insn); - - /* Check if user specified "-mcc-init" as a bug-workaround. Remember - to still set CC_REVERSED as below, since that's required by some - compare insn alternatives. (FIXME: GCC should do this virtual - operand swap by itself.) A test-case that may otherwise fail is - gcc.c-torture/execute/20000217-1.c -O0 and -O1. */ - if (TARGET_CCINIT) - { - CC_STATUS_INIT; - - if (attrval == CC_REV) - cc_status.flags = CC_REVERSED; - return; - } - - /* Slowly, we're converting to using attributes to control the setting - of condition-code status. */ - switch (attrval) - { - case CC_NONE: - /* Even if it is "none", a setting may clobber a previous - cc-value, so check. */ - if (GET_CODE (exp) == SET) - { - if (cc_status.value1 - && modified_in_p (cc_status.value1, insn)) - cc_status.value1 = 0; - - if (cc_status.value2 - && modified_in_p (cc_status.value2, insn)) - cc_status.value2 = 0; - } - return; - - case CC_CLOBBER: - CC_STATUS_INIT; - return; - - case CC_REV: - case CC_NORMAL: - cris_normal_notice_update_cc (exp, insn); - return; - - default: - internal_error ("unknown cc_attr value"); - } - - CC_STATUS_INIT; -} - /* Return != 0 if the return sequence for the current function is short, like "ret" or "jump [sp+]". Prior to reloading, we can't tell if registers must be saved, so return 0 then. */ @@ -2208,23 +1910,6 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, internal_error ("internal error: cris_side_effect_mode_ok with bad operands"); } -/* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16) - does not handle the case where the IN operand is strict_low_part; it - does handle it for X. Test-case in Axis-20010516. This function takes - care of that for THIS port. FIXME: strict_low_part is going away - anyway. */ - -static int -cris_reg_overlap_mentioned_p (rtx x, rtx in) -{ - /* The function reg_overlap_mentioned now handles when X is - strict_low_part, but not when IN is a STRICT_LOW_PART. */ - if (GET_CODE (in) == STRICT_LOW_PART) - in = XEXP (in, 0); - - return reg_overlap_mentioned_p (x, in); -} - /* Queue an .ident string in the queue of top-level asm statements. If the front-end is done, we must be being called from toplev.c. In that case, do nothing. */ @@ -2480,22 +2165,20 @@ cris_split_movdx (rtx *operands) /* We normally copy the low-numbered register first. However, if the first register operand 0 is the same as the second register of operand 1, we must copy in the opposite order. */ - emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode), - operand_subword (src, reverse, TRUE, mode))); + emit_move_insn (operand_subword (dest, reverse, TRUE, mode), + operand_subword (src, reverse, TRUE, mode)); - emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode), - operand_subword (src, !reverse, TRUE, mode))); + emit_move_insn (operand_subword (dest, !reverse, TRUE, mode), + operand_subword (src, !reverse, TRUE, mode)); } /* Constant-to-reg copy. */ else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) { rtx words[2]; split_double (src, &words[0], &words[1]); - emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), - words[0])); + emit_move_insn (operand_subword (dest, 0, TRUE, mode), words[0]); - emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), - words[1])); + emit_move_insn (operand_subword (dest, 1, TRUE, mode), words[1]); } /* Mem-to-reg copy. */ else if (MEM_P (src)) @@ -2522,18 +2205,15 @@ cris_split_movdx (rtx *operands) addresses ourselves, we must add a post-inc note manually. */ mem = change_address (src, SImode, addr); - insn - = gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), mem); - insn = emit_insn (insn); + insn = emit_move_insn (operand_subword (dest, 0, TRUE, mode), + mem); if (GET_CODE (XEXP (mem, 0)) == POST_INC) REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), REG_NOTES (insn)); mem = copy_rtx (mem); - insn - = gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), mem); - insn = emit_insn (insn); + insn = emit_move_insn (operand_subword (dest, 1, TRUE, mode), mem); if (GET_CODE (XEXP (mem, 0)) == POST_INC) REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), @@ -2548,19 +2228,17 @@ cris_split_movdx (rtx *operands) if (side_effects_p (addr)) fatal_insn ("unexpected side-effects in address", addr); - emit_insn (gen_rtx_SET - (operand_subword (dest, reverse, TRUE, mode), - change_address - (src, SImode, - plus_constant (Pmode, addr, - reverse * UNITS_PER_WORD)))); - emit_insn (gen_rtx_SET - (operand_subword (dest, ! reverse, TRUE, mode), - change_address - (src, SImode, - plus_constant (Pmode, addr, - (! reverse) * - UNITS_PER_WORD)))); + emit_move_insn (operand_subword (dest, reverse, TRUE, mode), + change_address + (src, SImode, + plus_constant (Pmode, addr, + reverse * UNITS_PER_WORD))); + emit_move_insn (operand_subword (dest, ! reverse, TRUE, mode), + change_address + (src, SImode, + plus_constant (Pmode, addr, + (! reverse) * + UNITS_PER_WORD))); } } else @@ -2582,17 +2260,14 @@ cris_split_movdx (rtx *operands) /* Whenever we emit insns with post-incremented addresses ourselves, we must add a post-inc note manually. */ mem = change_address (dest, SImode, addr); - insn - = gen_rtx_SET (mem, operand_subword (src, 0, TRUE, mode)); - insn = emit_insn (insn); + insn = emit_move_insn (mem, operand_subword (src, 0, TRUE, mode)); if (GET_CODE (XEXP (mem, 0)) == POST_INC) REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), REG_NOTES (insn)); mem = copy_rtx (mem); - insn = gen_rtx_SET (mem, operand_subword (src, 1, TRUE, mode)); - insn = emit_insn (insn); + insn = emit_move_insn (mem, operand_subword (src, 1, TRUE, mode)); if (GET_CODE (XEXP (mem, 0)) == POST_INC) REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0), @@ -2606,15 +2281,13 @@ cris_split_movdx (rtx *operands) if (side_effects_p (addr)) fatal_insn ("unexpected side-effects in address", addr); - emit_insn (gen_rtx_SET - (change_address (dest, SImode, addr), - operand_subword (src, 0, TRUE, mode))); + emit_move_insn (change_address (dest, SImode, addr), + operand_subword (src, 0, TRUE, mode)); - emit_insn (gen_rtx_SET - (change_address (dest, SImode, - plus_constant (Pmode, addr, - UNITS_PER_WORD)), - operand_subword (src, 1, TRUE, mode))); + emit_move_insn (change_address (dest, SImode, + plus_constant (Pmode, addr, + UNITS_PER_WORD)), + operand_subword (src, 1, TRUE, mode)); } } @@ -2670,10 +2343,7 @@ cris_expand_prologue (void) stdarg_regs > 0; regno--, pretend -= 4, stdarg_regs--) { - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, - stack_pointer_rtx, - -4))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, GEN_INT (-4))); /* FIXME: When dwarf2 frame output and unless asynchronous exceptions, make dwarf2 bundle together all stack adjustments like it does for registers between stack @@ -2698,9 +2368,8 @@ cris_expand_prologue (void) /* Save SRP if not a leaf function. */ if (return_address_on_stack) { - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - -4 - pretend))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-4 - pretend))); pretend = 0; RTX_FRAME_RELATED_P (insn) = 1; @@ -2714,9 +2383,8 @@ cris_expand_prologue (void) /* Set up the frame pointer, if needed. */ if (frame_pointer_needed) { - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - -4 - pretend))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-4 - pretend))); pretend = 0; RTX_FRAME_RELATED_P (insn) = 1; @@ -2763,7 +2431,10 @@ cris_expand_prologue (void) side-effects insns are allowed. */ if ((last_movem_reg + 1) * 4 + size >= 64 && (last_movem_reg + 1) * 4 + size <= 128 - && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) + && cris_cpu_version >= CRIS_CPU_SVINTO + /* Don't use side-effect assignment for a single + move. */ + && n_saved > 1 && TARGET_SIDE_EFFECT_PREFIXES) { mem @@ -2779,10 +2450,9 @@ cris_expand_prologue (void) else { insn - = gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - -(n_saved * 4 + size))); - insn = emit_insn (insn); + = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-(n_saved * 4 + + size)))); RTX_FRAME_RELATED_P (insn) = 1; mem = gen_rtx_MEM (SImode, stack_pointer_rtx); @@ -2796,10 +2466,8 @@ cris_expand_prologue (void) size = 0; } - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, - stack_pointer_rtx, - -4 - size))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-4 - size))); RTX_FRAME_RELATED_P (insn) = 1; mem = gen_rtx_MEM (SImode, stack_pointer_rtx); @@ -2823,7 +2491,9 @@ cris_expand_prologue (void) do it if side-effects insns are allowed. */ if ((last_movem_reg + 1) * 4 + size >= 64 && (last_movem_reg + 1) * 4 + size <= 128 - && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1) + && cris_cpu_version >= CRIS_CPU_SVINTO + /* Don't use side-effect assignment for a single move. */ + && n_saved > 1 && TARGET_SIDE_EFFECT_PREFIXES) { mem @@ -2836,11 +2506,8 @@ cris_expand_prologue (void) } else { - insn - = gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - -(n_saved * 4 + size))); - insn = emit_insn (insn); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-(n_saved * 4 + size)))); RTX_FRAME_RELATED_P (insn) = 1; mem = gen_rtx_MEM (SImode, stack_pointer_rtx); @@ -2852,20 +2519,16 @@ cris_expand_prologue (void) /* We have to put outgoing argument space after regs. */ if (cfoa_size) { - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, - stack_pointer_rtx, - -cfoa_size))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-cfoa_size))); RTX_FRAME_RELATED_P (insn) = 1; framesize += cfoa_size; } } else if ((size + cfoa_size) > 0) { - insn = emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, - stack_pointer_rtx, - -(cfoa_size + size)))); + insn = emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (-(cfoa_size + size)))); RTX_FRAME_RELATED_P (insn) = 1; framesize += size + cfoa_size; } @@ -2931,9 +2594,8 @@ cris_expand_epilogue (void) { /* There is an area for outgoing parameters located before the saved registers. We have to adjust for that. */ - emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - argspace_offset))); + emit_insn (gen_add2_insn (stack_pointer_rtx, + GEN_INT (argspace_offset))); /* Make sure we only do this once. */ argspace_offset = 0; } @@ -2956,9 +2618,7 @@ cris_expand_epilogue (void) if (argspace_offset) { - emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - argspace_offset))); + emit_insn (gen_add2_insn (stack_pointer_rtx, GEN_INT (argspace_offset))); argspace_offset = 0; } @@ -2966,8 +2626,7 @@ cris_expand_epilogue (void) gen_rtx_POST_INC (SImode, stack_pointer_rtx)); set_mem_alias_set (mem, get_frame_alias_set ()); insn - = emit_insn (cris_gen_movem_load (mem, - GEN_INT (last_movem_reg + 1), 0)); + = emit_insn (cris_gen_movem_load (mem, GEN_INT (last_movem_reg + 1))); /* Whenever we emit insns with post-incremented addresses ourselves, we must add a post-inc note manually. */ if (side_effects_p (PATTERN (insn))) @@ -3014,8 +2673,7 @@ cris_expand_epilogue (void) yet. */ size += argspace_offset; - emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, size))); + emit_insn (gen_add2_insn (stack_pointer_rtx, GEN_INT (size))); } /* If this function has no pushed register parameters @@ -3040,9 +2698,8 @@ cris_expand_epilogue (void) = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); if (crtl->calls_eh_return) - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - gen_raw_REG (SImode, CRIS_STACKADJ_REG))); + emit_insn (gen_add2_insn (stack_pointer_rtx, + gen_raw_REG (SImode, CRIS_STACKADJ_REG))); cris_expand_return (false); } else @@ -3074,23 +2731,20 @@ cris_expand_epilogue (void) = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn)); } - emit_insn (gen_rtx_SET (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, - pretend))); + emit_insn (gen_add2_insn (stack_pointer_rtx, GEN_INT (pretend))); } /* Perform the "physical" unwinding that the EH machinery calculated. */ if (crtl->calls_eh_return) - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - gen_raw_REG (SImode, CRIS_STACKADJ_REG))); + emit_insn (gen_add2_insn (stack_pointer_rtx, + gen_raw_REG (SImode, CRIS_STACKADJ_REG))); cris_expand_return (false); } /* Worker function for generating movem from mem for load_multiple. */ rtx -cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) +cris_gen_movem_load (rtx src, rtx nregs_rtx) { int nregs = INTVAL (nregs_rtx); rtvec vec; @@ -3109,24 +2763,23 @@ cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) if (nregs == 1) return gen_movsi (gen_rtx_REG (SImode, 0), src); - vec = rtvec_alloc (nprefix + nregs - + (GET_CODE (XEXP (src, 0)) == POST_INC)); + vec = rtvec_alloc (nregs + (GET_CODE (XEXP (src, 0)) == POST_INC)); if (GET_CODE (XEXP (src, 0)) == POST_INC) { - RTVEC_ELT (vec, nprefix + 1) + RTVEC_ELT (vec, 1) = gen_rtx_SET (srcreg, plus_constant (Pmode, srcreg, nregs * 4)); eltno++; } src = replace_equiv_address (src, srcreg); - RTVEC_ELT (vec, nprefix) + RTVEC_ELT (vec, 0) = gen_rtx_SET (gen_rtx_REG (SImode, regno), src); regno += regno_inc; for (i = 1; i < nregs; i++, eltno++) { - RTVEC_ELT (vec, nprefix + eltno) + RTVEC_ELT (vec, eltno) = gen_rtx_SET (gen_rtx_REG (SImode, regno), adjust_address_nv (src, SImode, i * 4)); regno += regno_inc; @@ -3135,6 +2788,22 @@ cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix) return gen_rtx_PARALLEL (VOIDmode, vec); } +/* Convenience function for CRIS-local use of emit_insn, wrapping the + argument in a parallel with a clobber of CRIS_CC0_REGNUM before + passing on to emit_insn. */ + +rtx_insn * +cris_emit_insn (rtx x) +{ + rtvec vec = rtvec_alloc (2); + + RTVEC_ELT (vec, 0) = x; + RTVEC_ELT (vec, 1) + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CRIS_CC0_REGNUM)); + + return emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); +} + /* Worker function for generating movem to mem. If FRAME_RELATED, notes are added that the dwarf2 machinery understands. */ @@ -3162,11 +2831,9 @@ cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, /* Don't use movem for just one insn. The insns are equivalent. */ if (nregs == 1) { - rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0)); - if (increment == 0) { - insn = emit_insn (mov); + insn = emit_move_insn (dest, gen_rtx_REG (SImode, 0)); if (frame_related) RTX_FRAME_RELATED_P (insn) = 1; return insn; @@ -3174,11 +2841,15 @@ cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment, /* If there was a request for a side-effect, create the ordinary parallel. */ - vec = rtvec_alloc (2); + vec = rtvec_alloc (3); + rtx mov = gen_rtx_SET (dest, gen_rtx_REG (SImode, 0)); RTVEC_ELT (vec, 0) = mov; RTVEC_ELT (vec, 1) = gen_rtx_SET (destreg, plus_constant (Pmode, destreg, increment)); + RTVEC_ELT (vec, 2) + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CRIS_CC0_REGNUM)); + if (frame_related) { RTX_FRAME_RELATED_P (mov) = 1; diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 4aa12b8c276..e721d12d0a2 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -698,11 +698,8 @@ struct cum_args {int regs;}; /* Node: Condition Code */ -#define NOTICE_UPDATE_CC(EXP, INSN) cris_notice_update_cc (EXP, INSN) - -/* FIXME: Maybe define CANONICALIZE_COMPARISON later, when playing with - optimizations. It is needed; currently we do this with instruction - patterns and NOTICE_UPDATE_CC. */ +/* FIXME: Maybe define TARGET_CANONICALIZE_COMPARISON later, when + playing with optimizations. Definitely define SELECT_CC_MODE. */ /* Node: Costs */ diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 1147d64681b..6ff4d98c75a 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -23,9 +23,6 @@ ;; See files "md.texi" and "rtl.def" for documentation on define_insn, ;; match_*, et. al. -;; -;; The function cris_notice_update_cc in cris.c handles condition code -;; updates for most instructions, helped by the "cc" attribute. ;; There are several instructions that are orthogonal in size, and seems ;; they could be matched by a single pattern without a specified size @@ -120,9 +117,9 @@ (define_attr "slottable" "no,yes,has_slot,has_return_slot" (const_string "no")) ;; We also need attributes to sanely determine the condition code -;; state. See cris_notice_update_cc for how this is used. +;; state. -(define_attr "cc" "none,clobber,normal,rev" (const_string "normal")) +(define_attr "cc" "none,clobber,normal" (const_string "normal")) ;; At the moment, this attribute is just used to help bb-reorder do its ;; work; the default 0 doesn't help it. Many insns have other lengths, @@ -155,6 +152,13 @@ (define_delay (eq_attr "slottable" "has_return_slot") ;; For the "usual" pattern size alternatives. (define_mode_iterator BWD [SI HI QI]) +(define_mode_iterator BWDD [DI SI HI QI]) + +;; To be able to refer to the same mode_attr for both a multi-mode +;; and a mode-specific pattern, we use some singleton iterators. +(define_mode_iterator DI_ [DI]) +(define_mode_iterator SI_ [SI]) + (define_mode_iterator WD [SI HI]) (define_mode_iterator BW [HI QI]) (define_mode_attr S [(SI "HI") (HI "QI")]) @@ -189,42 +193,35 @@ (define_code_attr roCC [(lt "pl") (ge "mi")]) (include "predicates.md") (include "constraints.md") -;; Test insns. - -;; No test insns with side-effect on the mem addressing. -;; -;; See note on cmp-insns with side-effects (or lack of them) - -;; Normal named test patterns from SI on. - -(define_insn "tst" - [(set (cc0) - (compare (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m") - (const_int 0)))] - "" - "test %0" - [(set_attr "slottable" "yes,yes,no")]) - ;; It seems that the position of the sign-bit and the fact that 0.0 is ;; all 0-bits would make "tstsf" a straight-forward implementation; ;; either "test.d" it for positive/negative or "btstq 30,r" it for ;; zeroness. ;; -;; FIXME: Do that some time; check next_cc0_user to determine if -;; zero or negative is tested for. +;; FIXME: Do that some time. ;; Compare insns. +;; These are used for compare insn, cbranch and cstore. +;; FIXME: Port-local reversing of operands is not done. Still needed? +;; (It shouldn't be; it should be done as part of register allocation.) +(define_mode_attr sCC_destc + [(DI "r, r,r,r,r,r,r") (SI "r,r, r, r,r,r") (HI "r, r, r,r") (QI "r, r, r,r")]) +(define_mode_attr cmp_op1c + [(DI "rm,r,r,r,r,r,r") (SI "r,r, rQ>,r,r,m") (HI "r, rQ>,r,m") (QI "r, rQ>,r,m")]) +(define_mode_attr cmp_op2c + [(DI "M,Kc,I,P,n,r,o") (SI "I,rQ>,M, P,g,M") (HI "rQ>,M, g,M") (QI "rQ>,M, g,M")]) + ;; We could optimize the sizes of the immediate operands for various ;; cases, but that is not worth it because of the very little usage of ;; DImode for anything else but a structure/block-mode. Just do the ;; obvious stuff for the straight-forward constraint letters. (define_insn "*cmpdi" - [(set (cc0) - (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o") - (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))] - "" + [(set (reg:CC CRIS_CC0_REGNUM) + (compare:CC (match_operand:DI_ 0 "nonimmediate_operand" "") + (match_operand:DI_ 1 "general_operand" "")))] + "reload_completed" "@ test.d %M0\;ax\;test.d %H0 cmpq %1,%M0\;ax\;cmpq 0,%H0 @@ -232,8 +229,7 @@ (define_insn "*cmpdi" cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 - cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0 - cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1") + cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0") ;; Note that compare insns with side effect addressing mode (e.g.): ;; @@ -255,63 +251,44 @@ (define_insn "*cmpdi" ;; (memory) operands. Avoid side-effect patterns, though (see above). (define_insn "*cmp_ext" - [(set (cc0) - (compare + [(set (reg:CC CRIS_CC0_REGNUM) + (compare:CC (match_operand:SI 0 "register_operand" "r,r") (match_operator:SI 2 "cris_extend_operator" [(match_operand:BW 1 "memory_operand" "Q>,m")])))] - "" + "reload_completed" "cmp%e2 %1,%0" [(set_attr "slottable" "yes,no")]) - -;; Swap operands; it seems the canonical look (if any) is not enforced. -;; -;; FIXME: Investigate that. - -(define_insn "*cmp_swapext" - [(set (cc0) - (compare - (match_operator:SI 2 "cris_extend_operator" - [(match_operand:BW 0 "memory_operand" "Q>,m")]) - (match_operand:SI 1 "register_operand" "r,r")))] - "" - "cmp%e2 %0,%1" - [(set_attr "slottable" "yes,no") - (set_attr "cc" "rev")]) ;; The "normal" compare patterns, from SI on. Special-cases with zero ;; are covered above. (define_insn "*cmpsi" - [(set (cc0) - (compare - (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m") - (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))] - "" + [(set (reg:CC CRIS_CC0_REGNUM) + (compare:CC + (match_operand:SI_ 0 "nonimmediate_operand" "") + (match_operand:SI_ 1 "general_operand" "")))] + "reload_completed" "@ cmpq %1,%0 cmp.d %1,%0 - cmp.d %1,%0 - cmp.d %0,%1 + test.d %0 cmp%e1.%z1 %1,%0 cmp.d %1,%0 - cmp.d %0,%1" - [(set_attr "slottable" "yes,yes,yes,yes,no,no,no") - (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")]) + test.d %0" + [(set_attr "slottable" "yes,yes,yes,no,no,no")]) (define_insn "*cmp" - [(set (cc0) - (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m") - (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))] - "" + [(set (reg:CC CRIS_CC0_REGNUM) + (compare:CC (match_operand:BW 0 "nonimmediate_operand" "") + (match_operand:BW 1 "general_operand" "")))] + "reload_completed" "@ cmp %1,%0 + test %0 cmp %1,%0 - cmp %0,%1 - cmp %1,%0 - cmp %0,%1" - [(set_attr "slottable" "yes,yes,yes,no,no") - (set_attr "cc" "normal,normal,rev,normal,rev")]) + test %0" + [(set_attr "slottable" "yes,yes,no,no")]) ;; Pattern matching the BTST insn. ;; It is useful for "if (i & val)" constructs, where val is an exact @@ -321,8 +298,8 @@ (define_insn "*cmp" ;; SImode. This mode is the only one needed, since gcc automatically ;; extends subregs for lower-size modes. FIXME: Add testcase. (define_insn "*btst" - [(set (cc0) - (compare + [(set (reg:CC CRIS_CC0_REGNUM) + (compare:CC (zero_extract:SI (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp") (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n") @@ -330,7 +307,8 @@ (define_insn "*btst" (const_int 0)))] ;; Either it is a single bit, or consecutive ones starting at 0. ;; The btst ones depend on stuff in NOTICE_UPDATE_CC. - "CONST_INT_P (operands[1]) + "reload_completed + && CONST_INT_P (operands[1]) && (operands[1] == const1_rtx || operands[2] == const0_rtx) && (REG_S_P (operands[0]) || (operands[1] == const1_rtx @@ -399,8 +377,10 @@ (define_insn "*btst" ;; insn with pseudos that need more reloading. The question is where. (define_expand "movdi" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(parallel + [(set (match_operand:DI 0 "nonimmediate_operand") + (match_operand:DI 1 "general_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { if (MEM_P (operands[0]) @@ -437,7 +417,8 @@ (define_expand "movdi" (define_insn_and_split "*movdi_insn" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m") - (match_operand:DI 1 "general_operand" "rx,g,rxM"))] + (match_operand:DI 1 "general_operand" "rx,g,rxM")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "(register_operand (operands[0], DImode) || register_operand (operands[1], DImode) || operands[1] == const0_rtx)" @@ -446,333 +427,14 @@ (define_insn_and_split "*movdi_insn" [(match_dup 2)] "operands[2] = cris_split_movdx (operands);") -;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw -;; and move.S1 [rx=ry+i],rz -;; Then movs.S1 and movu.S1 for both modes. -;; -;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx -;; FIXME: These could have anonymous mode for operand 0. -;; FIXME: Special registers' alternatives too. - -(define_insn "*mov_side_biap" - [(set (match_operand:BW 0 "register_operand" "=r,r") - (mem:BW (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "n,n")) - (match_operand:SI 3 "register_operand" "r,r")))) - (set (match_operand:SI 4 "register_operand" "=*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - move [%4=%3+%1%T2],%0") - -(define_insn "*mov_sidesisf_biap" - [(set (match_operand 0 "register_operand" "=r,r,x,x") - (mem (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r") - (match_operand:SI 2 "const_int_operand" "n,n,n,n")) - (match_operand:SI 3 "register_operand" "r,r,r,r")))) - (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD - && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - move.%s0 [%4=%3+%1%T2],%0 - # - move [%4=%3+%1%T2],%0") - -;; move.S1 [rx=ry+i],rz -;; avoiding move.S1 [ry=ry+i],rz -;; and move.S1 [rz=ry+i],rz -;; Note that "i" is allowed to be a register. - -(define_insn "*mov_side" - [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r") - (mem:BW - (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))) - (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[2]) - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || satisfies_constraint_N (operands[2]) - || satisfies_constraint_J (operands[2]))) - return "#"; - if (which_alternative == 4) - return "move [%3=%2%S1],%0"; - return "move [%3=%1%S2],%0"; -}) - -(define_insn "*mov_sidesisf" - [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x") - (mem - (plus:SI - (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r")))) - (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD - && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" -{ - if ((which_alternative == 0 - || which_alternative == 3 - || which_alternative == 6 - || which_alternative == 8) - && (!CONST_INT_P (operands[2]) - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || satisfies_constraint_N (operands[2]) - || satisfies_constraint_J (operands[2]))) - return "#"; - if (which_alternative < 3) - return "move.%s0 [%3=%1%S2],%0"; - if (which_alternative == 7) - return "move.%s0 [%3=%2%S1],%0"; - if (which_alternative == 9) - return "move [%3=%2%S1],%0"; - return "move [%3=%1%S2],%0"; -}) - -;; Other way around; move to memory. - -;; Note that the condition (which for side-effect patterns is usually a -;; call to cris_side_effect_mode_ok), isn't consulted for register -;; allocation preferences -- constraints is the method for that. The -;; drawback is that we can't exclude register allocation to cause -;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or -;; rx==rz if we use an earlyclobber modifier for the constraint for rx. -;; Instead of that, we recognize and split the cases where dangerous -;; register combinations are spotted: where a register is set in the -;; side-effect, and used in the main insn. We don't handle the case where -;; the set in the main insn overlaps the set in the side-effect; that case -;; must be handled in gcc. We handle just the case where the set in the -;; side-effect overlaps the input operand of the main insn (i.e. just -;; moves to memory). - -;; -;; move.s rz,[ry=rx+rw.S] - -(define_insn "*mov_side_biap_mem" - [(set (mem:BW (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") - (match_operand:SI 1 "const_int_operand" "n,n,n")) - (match_operand:SI 2 "register_operand" "r,r,r"))) - (match_operand:BW 3 "register_operand" "r,r,r")) - (set (match_operand:SI 4 "register_operand" "=*2,!3,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" - "@ - # - # - move %3,[%4=%2+%0%T1]") - -(define_insn "*mov_sidesisf_biap_mem" - [(set (mem (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r") - (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n")) - (match_operand:SI 2 "register_operand" "r,r,r,r,r,r"))) - (match_operand 3 "register_operand" "r,r,r,x,x,x")) - (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD - && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" - "@ - # - # - move.%s3 %3,[%4=%2+%0%T1] - # - # - move %3,[%4=%2+%0%T1]") - -;; Split for the case above where we're out of luck with register -;; allocation (again, the condition isn't checked for that), and we end up -;; with the set in the side-effect getting the same register as the input -;; register. - -(define_split - [(parallel - [(set (match_operator - 6 "cris_mem_op" - [(plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "")) - (match_operand:SI 2 "register_operand" ""))]) - (match_operand 3 "register_operand" "")) - (set (match_operand:SI 4 "cris_nonsp_register_operand" "") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))])] - "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])" - [(set (match_dup 5) (match_dup 3)) - (set (match_dup 4) (match_dup 2)) - (set (match_dup 4) - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 4)))] - "operands[5] - = replace_equiv_address (operands[6], - gen_rtx_PLUS (SImode, - gen_rtx_MULT (SImode, - operands[0], - operands[1]), - operands[2]));") - -;; move.s rx,[ry=rz+i] -;; FIXME: These could have anonymous mode for operand 2. - -;; QImode - -(define_insn "*mov_side_mem" - [(set (mem:BW - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r"))) - (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r")) - (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" -{ - if ((which_alternative == 0 || which_alternative == 4) - && (!CONST_INT_P (operands[1]) - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || satisfies_constraint_N (operands[1]) - || satisfies_constraint_J (operands[1]))) - return "#"; - if (which_alternative == 1 || which_alternative == 5) - return "#"; - if (which_alternative == 6) - return "move.%s2 %2,[%3=%1%S0]"; - return "move %2,[%3=%0%S1]"; -}) - -;; SImode - -(define_insn "*mov_sidesisf_mem" - [(set (mem - (plus:SI - (match_operand:SI - 0 "cris_bdap_operand" - "%r, r, r,r, r, r,r, R,R, R,R, R") - (match_operand:SI - 1 "cris_bdap_operand" - "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r"))) - (match_operand 2 "register_operand" - "r, r, r,r, x, x,x, r,r, r,x, x")) - (set (match_operand:SI 3 "register_operand" - "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD - && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" -{ - if ((which_alternative == 0 || which_alternative == 4) - && (!CONST_INT_P (operands[1]) - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || satisfies_constraint_N (operands[1]) - || satisfies_constraint_J (operands[1]))) - return "#"; - if (which_alternative == 1 - || which_alternative == 7 - || which_alternative == 8 - || which_alternative == 10) - return "#"; - if (which_alternative < 4) - return "move.%s2 %2,[%3=%0%S1]"; - if (which_alternative == 9) - return "move.%s2 %2,[%3=%1%S0]"; - if (which_alternative == 11) - return "move %2,[%3=%1%S0]"; - return "move %2,[%3=%0%S1]"; -}) - -;; Like the biap case, a split where the set in the side-effect gets the -;; same register as the input register to the main insn, since the -;; condition isn't checked at register allocation. - -(define_split - [(parallel - [(set (match_operator - 4 "cris_mem_op" - [(plus:SI - (match_operand:SI 0 "cris_bdap_operand" "") - (match_operand:SI 1 "cris_bdap_operand" ""))]) - (match_operand 2 "register_operand" "")) - (set (match_operand:SI 3 "cris_nonsp_register_operand" "") - (plus:SI (match_dup 0) (match_dup 1)))])] - "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])" - [(set (match_dup 4) (match_dup 2)) - (set (match_dup 3) (match_dup 0)) - (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))] - "") - -;; Clear memory side-effect patterns. It is hard to get to the mode if -;; the MEM was anonymous, so there will be one for each mode. - -;; clear.[bwd] [ry=rx+rw.s2] - -(define_insn "*clear_side_biap" - [(set (mem:BWD (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "const_int_operand" "n,n")) - (match_operand:SI 2 "register_operand" "r,r"))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "=*2,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" - "@ - # - clear [%3=%2+%0%T1]") - -;; clear.[bwd] [ry=rz+i] - -(define_insn "*clear_side" - [(set (mem:BWD - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[1]) - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || satisfies_constraint_N (operands[1]) - || satisfies_constraint_J (operands[1]))) - return "#"; - if (which_alternative == 4) - return "clear [%2=%1%S0]"; - return "clear [%2=%0%S1]"; -}) - ;; Normal move patterns from SI on. (define_expand "movsi" - [(set - (match_operand:SI 0 "nonimmediate_operand" "") - (match_operand:SI 1 "general_operand" ""))] + [(parallel + [(set + (match_operand:SI 0 "nonimmediate_operand") + (match_operand:SI 1 "general_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { /* If the output goes to a MEM, make sure we have zero or a register as @@ -789,7 +451,8 @@ (define_insn "*movsi_internal" (match_operand:SI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,g,r,r,g,rQ>,x, m,x") (match_operand:SI 1 "general_operand" - "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi"))] + "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi")) + (clobber (reg:CC CRIS_CC0_REGNUM))] ;; Note that we prefer not to use the S alternative (if for some reason ;; it competes with others) above, but g matches S. "" @@ -844,108 +507,13 @@ (define_insn "*movsi_internal" [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,yes,yes,no,no") (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,none,none,none,none")]) -;; Extend operations with side-effect from mem to register, using -;; MOVS/MOVU. These are from mem to register only. -;; -;; [rx=ry+rz.S] -;; -;; QImode to HImode -;; -;; FIXME: Can we omit extend to HImode, since GCC should truncate for -;; HImode by itself? Perhaps use only anonymous modes? - -(define_insn "*ext_sideqihi_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI - 5 "cris_extend_operator" - [(mem:QI (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "n,n")) - (match_operand:SI 3 "register_operand" "r,r")))])) - (set (match_operand:SI 4 "register_operand" "=*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - mov%e5.%m5 [%4=%3+%1%T2],%0") - -(define_insn "*ext_sidesi_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 5 "cris_extend_operator" - [(mem:BW (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "n,n")) - (match_operand:SI 3 "register_operand" "r,r")))])) - (set (match_operand:SI 4 "register_operand" "=*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - mov%e5 [%4=%3+%1%T2],%0") - -;; Same but [rx=ry+i] - -;; QImode to HImode - -(define_insn "*ext_sideqihi" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") - (match_operator:HI - 4 "cris_extend_operator" - [(mem:QI (plus:SI - (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) - (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[2]) - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || satisfies_constraint_N (operands[2]) - || satisfies_constraint_J (operands[2]))) - return "#"; - if (which_alternative == 4) - return "mov%e4.%m4 [%3=%2%S1],%0"; - return "mov%e4.%m4 [%3=%1%S2],%0"; -}) - -(define_insn "*ext_sidesi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") - (match_operator:SI - 4 "cris_extend_operator" - [(mem:BW (plus:SI - (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) - (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[2]) - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || satisfies_constraint_N (operands[2]) - || satisfies_constraint_J (operands[2]))) - return "#"; - if (which_alternative == 4) - return "mov%e4 [%3=%2%S1],%0"; - return "mov%e4 [%3=%1%S2],%0"; -}) - ;; FIXME: See movsi. (define_insn "movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x") - (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))] + (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" { switch (which_alternative) @@ -987,7 +555,8 @@ (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g")) - (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))] + (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ move.w %1,%0 @@ -1018,7 +587,8 @@ (define_expand "reload_out" (define_insn "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x") - (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))] + (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ move.b %1,%0 @@ -1039,7 +609,8 @@ (define_insn "movqi" (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r")) - (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))] + (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ move.b %1,%0 @@ -1059,7 +630,8 @@ (define_insn "movstrictqi" (define_insn "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x") - (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))] + (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ move.d %1,%0 @@ -1117,19 +689,22 @@ (define_insn "*cris_store_multiple" (define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))] + (sign_extend:DI (match_operand:SI 1 "general_operand" "g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0") (define_insn "extenddi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))] + (sign_extend:DI (match_operand:BW 1 "general_operand" "g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "movs %1,%M0\;smi %H0\;neg.d %H0,%H0") (define_insn "extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))] + (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "movs %1,%0" [(set_attr "slottable" "yes,yes,no")]) @@ -1139,7 +714,8 @@ (define_insn "extendsi2" (define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))] + (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "movs.b %1,%0" [(set_attr "slottable" "yes,yes,no")]) @@ -1151,7 +727,8 @@ (define_insn "extendqihi2" (define_insn "zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI - (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))] + (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "movu %1,%0" [(set_attr "slottable" "yes,yes,no")]) @@ -1161,139 +738,31 @@ (define_insn "zero_extendsi2" (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (zero_extend:HI - (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] + (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "movu.b %1,%0" [(set_attr "slottable" "yes,yes,no")]) -;; All kinds of arithmetic and logical instructions. -;; -;; First, anonymous patterns to match addressing modes with -;; side-effects. -;; -;; op.S [rx=ry+I],rz; (add, sub, or, and, bound). -;; -;; [rx=ry+rz.S] - -(define_insn "*op_side_biap" - [(set (match_operand:BWD 0 "register_operand" "=r,r") - (match_operator:BWD - 6 "cris_orthogonal_operator" - [(match_operand:BWD 1 "register_operand" "0,0") - (mem:BWD (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6 [%5=%4+%2%T3],%0") - -;; [rx=ry+i] ([%4=%2+%3]) - -(define_insn "*op_side" - [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r") - (match_operator:BWD - 5 "cris_orthogonal_operator" - [(match_operand:BWD 1 "register_operand" "0,0,0,0,0") - (mem:BWD (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return "%x5.%s0 [%4=%3%S2],%0"; - return "%x5 [%4=%2%S3],%0"; -}) - -;; To match all cases for commutative operations we may have to have the -;; following pattern for add, or & and. I do not know really, but it does -;; not break anything. -;; -;; FIXME: This really ought to be checked. -;; -;; op.S [rx=ry+I],rz; -;; -;; [rx=ry+rz.S] - -(define_insn "*op_swap_side_biap" - [(set (match_operand:BWD 0 "register_operand" "=r,r") - (match_operator:BWD - 6 "cris_commutative_orth_op" - [(mem:BWD (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r"))) - (match_operand:BWD 1 "register_operand" "0,0")])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6 [%5=%4+%2%T3],%0") - -;; [rx=ry+i] ([%4=%2+%3]) -;; FIXME: These could have anonymous mode for operand 0. - -;; QImode - -(define_insn "*op_swap_side" - [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r") - (match_operator:BWD - 5 "cris_commutative_orth_op" - [(mem:BWD - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))) - (match_operand:BWD 1 "register_operand" "0,0,0,0,0")])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return "%x5 [%4=%3%S2],%0"; - return "%x5 [%4=%2%S3],%0"; -}) - ;; Add operations, standard names. ;; Note that for the 'P' constraint, the high part can be -1 or 0. We ;; output the insn through the 'A' output modifier as "adds.w" and "addq", ;; respectively. (define_expand "adddi3" - [(set (match_operand:DI 0 "register_operand") - (plus:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "general_operand")))] + [(parallel + [(set (match_operand:DI 0 "register_operand") + (plus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") (define_insn "*adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r") - (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] + (match_operand:DI 2 "general_operand" "J,N,P,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ addq %2,%M0\;ax\;addq 0,%H0 @@ -1303,10 +772,12 @@ (define_insn "*adddi3" add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0") (define_expand "add3" - [(set (match_operand:BWD 0 "register_operand") - (plus:BWD - (match_operand:BWD 1 "register_operand") - (match_operand:BWD 2 "general_operand")))] + [(parallel + [(set (match_operand:BWD 0 "register_operand") + (plus:BWD + (match_operand:BWD 1 "register_operand") + (match_operand:BWD 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") @@ -1314,7 +785,8 @@ (define_insn "*addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r, r") (plus:SI (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0,r, r") - (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))] + (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] ;; The last constraint is due to that after reload, the '%' is not ;; honored, and canonicalization doesn't care about keeping the same @@ -1365,7 +837,8 @@ (define_insn "*addsi3" (define_insn "*addhi3" [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r") (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r") - (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] + (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ add.w %2,%0 @@ -1380,7 +853,8 @@ (define_insn "*addhi3" (define_insn "*addqi3" [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r") (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r") - (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))] + (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ add.b %2,%0 @@ -1402,16 +876,19 @@ (define_insn "*addqi3" ;; output the insn through the 'D' output modifier as "subs.w" and "subq", ;; respectively. (define_expand "subdi3" - [(set (match_operand:DI 0 "register_operand") - (minus:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "general_operand")))] + [(parallel + [(set (match_operand:DI 0 "register_operand") + (minus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") (define_insn "*subdi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r") (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r") - (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))] + (match_operand:DI 2 "general_operand" "J,N,P,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ subq %2,%M0\;ax\;subq 0,%H0 @@ -1421,10 +898,12 @@ (define_insn "*subdi3" sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0") (define_expand "sub3" - [(set (match_operand:BWD 0 "register_operand") - (minus:BWD - (match_operand:BWD 1 "register_operand") - (match_operand:BWD 2 "general_operand")))] + [(parallel + [(set (match_operand:BWD 0 "register_operand") + (minus:BWD + (match_operand:BWD 1 "register_operand") + (match_operand:BWD 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") @@ -1432,7 +911,8 @@ (define_insn "*subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r") (minus:SI (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r") - (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))] + (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative. @@ -1452,7 +932,8 @@ (define_insn "*subsi3" (define_insn "*sub3" [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r") (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r") - (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))] + (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ sub %2,%0 @@ -1464,314 +945,6 @@ (define_insn "*sub3" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) -;; CRIS has some add/sub-with-sign/zero-extend instructions. -;; Although these perform sign/zero-extension to SImode, they are -;; equally applicable for the HImode case. -;; FIXME: Check; GCC should handle the widening. -;; Note that these must be located after the normal add/sub patterns, -;; so not to get constants into any less specific operands. -;; -;; Extend with add/sub and side-effect. -;; -;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend -;; -;; adds/subs/addu/subu bound [rx=ry+rz.S] - -;; QImode to HImode -;; FIXME: GCC should widen. - -(define_insn "*extopqihi_side_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI - 6 "cris_additive_operand_extend_operator" - [(match_operand:HI 1 "register_operand" "0,0") - (match_operator:HI - 7 "cris_extend_operator" - [(mem:QI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6%e7.%m7 [%5=%4+%2%T3],%0") - -(define_insn "*extopsi_side_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 6 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operator:SI - 7 "cris_extend_operator" - [(mem:BW (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6%e7 [%5=%4+%2%T3],%0") - - -;; [rx=ry+i] - -;; QImode to HImode - -(define_insn "*extopqihi_side" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") - (match_operator:HI - 5 "cris_additive_operand_extend_operator" - [(match_operand:HI 1 "register_operand" "0,0,0,0,0") - (match_operator:HI - 6 "cris_extend_operator" - [(mem:QI - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r") - ))])])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return "%x5%E6.%m6 [%4=%3%S2],%0"; - return "%x5%E6.%m6 [%4=%2%S3],%0"; -}) - -(define_insn "*extopsi_side" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") - (match_operator:SI - 5 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0,0,0,0") - (match_operator:SI - 6 "cris_extend_operator" - [(mem:BW - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r") - ))])])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return "%x5%E6 [%4=%3%S2],%0"; - return "%x5%E6 [%4=%2%S3],%0"; -}) - - -;; As with op.S we may have to add special pattern to match commuted -;; operands to adds/addu and bound -;; -;; adds/addu/bound [rx=ry+rz.S] - -;; QImode to HImode -;; FIXME: GCC should widen. - -(define_insn "*extopqihi_swap_side_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (plus:HI - (match_operator:HI - 6 "cris_extend_operator" - [(mem:QI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))]) - (match_operand:HI 1 "register_operand" "0,0"))) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - add%e6.b [%5=%4+%2%T3],%0") - -(define_insn "*extopsi_swap_side_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 7 "cris_plus_or_bound_operator" - [(match_operator:SI - 6 "cris_extend_operator" - [(mem:BW (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))]) - (match_operand:SI 1 "register_operand" "0,0")])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x7%E6 [%5=%4+%2%T3],%0") - -;; [rx=ry+i] -;; FIXME: GCC should widen. - -;; QImode to HImode - -(define_insn "*extopqihi_swap_side" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") - (plus:HI - (match_operator:HI - 5 "cris_extend_operator" - [(mem:QI (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]) - (match_operand:HI 1 "register_operand" "0,0,0,0,0"))) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return "add%e5.b [%4=%3%S2],%0"; - return "add%e5.b [%4=%2%S3],%0"; -}) - -(define_insn "*extopsi_swap_side" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") - (match_operator:SI - 6 "cris_plus_or_bound_operator" - [(match_operator:SI - 5 "cris_extend_operator" - [(mem:BW (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]) - (match_operand:SI 1 "register_operand" "0,0,0,0,0")])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" -{ - if ((which_alternative == 0 || which_alternative == 3) - && (!CONST_INT_P (operands[3]) - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || satisfies_constraint_N (operands[3]) - || satisfies_constraint_J (operands[3]))) - return "#"; - if (which_alternative == 4) - return \"%x6%E5.%m5 [%4=%3%S2],%0\"; - return "%x6%E5 [%4=%2%S3],%0"; -}) - -;; Extend versions (zero/sign) of normal add/sub (no side-effects). - -;; QImode to HImode -;; FIXME: GCC should widen. - -(define_insn "*extopqihi" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") - (match_operator:HI - 3 "cris_additive_operand_extend_operator" - [(match_operand:HI 1 "register_operand" "0,0,0,r") - (match_operator:HI - 4 "cris_extend_operator" - [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] - "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" - "@ - %x3%E4.%m4 %2,%0 - %x3%E4.%m4 %2,%0 - %x3%E4.%m4 %2,%0 - %x3%E4.%m4 %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no") - (set_attr "cc" "clobber")]) - -;; QImode to SImode - -(define_insn "*extopsi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (match_operator:SI - 3 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0,0,r") - (match_operator:SI - 4 "cris_extend_operator" - [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] - "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" - "@ - %x3%E4 %2,%0 - %x3%E4 %2,%0 - %x3%E4 %2,%0 - %x3%E4 %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no")]) - -;; As with the side-effect patterns, may have to have swapped operands for add. -;; For commutative operands, these are the canonical forms. - -;; QImode to HImode - -(define_insn "*addxqihi_swap" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") - (plus:HI - (match_operator:HI - 3 "cris_extend_operator" - [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) - (match_operand:HI 1 "register_operand" "0,0,0,r")))] - "operands[1] != frame_pointer_rtx" - "@ - add%e3.b %2,%0 - add%e3.b %2,%0 - add%e3.b %2,%0 - add%e3.b %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no") - (set_attr "cc" "clobber")]) - -(define_insn "*extopsi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (match_operator:SI - 4 "cris_plus_or_bound_operator" - [(match_operator:SI - 3 "cris_extend_operator" - [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")]) - (match_operand:SI 1 "register_operand" "0,0,0,r")]))] - "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) - && operands[1] != frame_pointer_rtx" - "@ - %x4%E3 %2,%0 - %x4%E3 %2,%0 - %x4%E3 %2,%0 - %x4%E3 %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no")]) - ;; This is the special case when we use what corresponds to the ;; instruction above in "casesi". Do *not* change it to use the generic ;; pattern and "REG 15" as pc; I did that and it led to madness and @@ -1803,7 +976,8 @@ (define_insn "*casesi_adds_w" (pc)))) (pc)) (label_ref (match_operand 2 "" "")))) - (use (label_ref (match_operand 3 "" "")))] + (use (label_ref (match_operand 3 "" ""))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "operands[0] != frame_pointer_rtx" "adds.w [$pc+%0.w],$pc" [(set_attr "cc" "clobber")]) @@ -1821,7 +995,8 @@ (define_insn "addi_mul" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "const_int_operand" "n")))] + (match_operand:SI 2 "const_int_operand" "n"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "operands[0] != frame_pointer_rtx && operands[1] != frame_pointer_rtx && CONST_INT_P (operands[2]) @@ -1861,50 +1036,13 @@ (define_insn "*addi" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) -;; The mstep instruction. Probably not useful by itself; it's to -;; non-linear wrt. the other insns. We used to expand to it, so at least -;; it's correct. - -(define_insn "mstep_shift" - [(set (match_operand:SI 0 "register_operand" "=r") - (if_then_else:SI - (lt:SI (cc0) (const_int 0)) - (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") - (const_int 1)) - (match_operand:SI 2 "register_operand" "r")) - (ashift:SI (match_operand:SI 3 "register_operand" "0") - (const_int 1))))] - "" - "mstep %2,%0" - [(set_attr "slottable" "yes")]) - -;; When illegitimate addresses are legitimized, sometimes gcc forgets -;; to canonicalize the multiplications. -;; -;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc. - -(define_insn "mstep_mul" - [(set (match_operand:SI 0 "register_operand" "=r") - (if_then_else:SI - (lt:SI (cc0) (const_int 0)) - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") - (const_int 2)) - (match_operand:SI 2 "register_operand" "r")) - (mult:SI (match_operand:SI 3 "register_operand" "0") - (const_int 2))))] - "operands[0] != frame_pointer_rtx - && operands[1] != frame_pointer_rtx - && operands[2] != frame_pointer_rtx - && operands[3] != frame_pointer_rtx" - "mstep %2,%0" - [(set_attr "slottable" "yes")]) - (define_insn "mul3" [(set (match_operand:WD 0 "register_operand" "=r") (mult:WD (szext:WD (match_operand: 1 "register_operand" "%0")) (szext:WD (match_operand: 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] + (clobber (match_scratch:SI 3 "=h")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_MUL_INSNS" "%!mul %2,%0" [(set (attr "slottable") @@ -1927,7 +1065,8 @@ (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "r"))) - (clobber (match_scratch:SI 3 "=h"))] + (clobber (match_scratch:SI 3 "=h")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_MUL_INSNS" "%!muls.d %2,%0" [(set (attr "slottable") @@ -1941,16 +1080,14 @@ (define_insn "mulsi3" ;; When needed, we can get the high 32 bits from the overflow ;; register. We don't care to split and optimize these. -;; -;; Note that cc0 is still valid after the move-from-overflow-register -;; insn; no special precaution need to be taken in cris_notice_update_cc. (define_insn "mulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (szext:DI (match_operand:SI 1 "register_operand" "%0")) (szext:DI (match_operand:SI 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] + (clobber (match_scratch:SI 3 "=h")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_MUL_INSNS" "%!mul.d %2,%M0\;move $mof,%H0") @@ -1976,7 +1113,8 @@ (define_insn "mulsi3_highpart" (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r")) (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=1,2,h,h"))] + (clobber (match_scratch:SI 3 "=1,2,h,h")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_MUL_INSNS" "@ %!mul.d %2,%1 @@ -1998,7 +1136,8 @@ (define_insn "dstep_shift" (const_int 1)) (match_operand:SI 4 "register_operand" "2")) (ashift:SI (match_operand:SI 5 "register_operand" "0") - (const_int 1))))] + (const_int 1)))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "dstep %2,%0" [(set_attr "slottable" "yes")]) @@ -2017,7 +1156,8 @@ (define_insn "dstep_mul" (const_int 2)) (match_operand:SI 4 "register_operand" "2")) (mult:SI (match_operand:SI 5 "register_operand" "0") - (const_int 2))))] + (const_int 2)))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "operands[0] != frame_pointer_rtx && operands[1] != frame_pointer_rtx && operands[2] != frame_pointer_rtx @@ -2041,9 +1181,11 @@ (define_insn "dstep_mul" ;; FIXME: This should be made obsolete. (define_expand "andsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (and:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "general_operand" "")))] + [(parallel + [(set (match_operand:SI 0 "nonimmediate_operand") + (and:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:SI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { if (! (CONST_INT_P (operands[2]) @@ -2072,7 +1214,8 @@ (define_expand "andsi3" reg1 = reg0; } - emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (SImode, reg1, operands[2]))); + cris_emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (SImode, reg1, + operands[2]))); /* Make sure we get the right *final* destination. */ if (! REG_P (operands[0])) @@ -2087,16 +1230,20 @@ (define_expand "andsi3" (define_insn "*andsi_movu" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To") - (match_operand:SI 2 "const_int_operand" "n,n,n")))] + (match_operand:SI 2 "const_int_operand" "n,n,n"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535) && !side_effects_p (operands[1])" "movu.%z2 %1,%0" [(set_attr "slottable" "yes,yes,no")]) +;; FIXME: Remember, this does *not* actually affect condition codes; +;; get rid of the clobber. (define_insn "*andsi_clear" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") - (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))] + (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256) && !side_effects_p (operands[0])" "@ @@ -2120,7 +1267,8 @@ (define_insn "*andsi_clear" (define_insn "*expanded_andsi" [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r") (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r") - (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))] + (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ andq %2,%0 @@ -2132,15 +1280,17 @@ (define_insn "*expanded_andsi" ;; For both QI and HI we may use the quick patterns. This results in ;; useless condition codes, but that is used rarely enough for it to -;; normally be a win (could check ahead for use of cc0, but seems to be -;; more pain than win). +;; normally be a win (could check ahead for use of CRIS_CC0_REGNUM, but +;; seems to be more pain than win). ;; FIXME: See note for andsi3 (define_expand "andhi3" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (and:HI (match_operand:HI 1 "nonimmediate_operand" "") - (match_operand:HI 2 "general_operand" "")))] + [(parallel + [(set (match_operand:HI 0 "nonimmediate_operand") + (and:HI (match_operand:HI 1 "nonimmediate_operand") + (match_operand:HI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { if (! (CONST_INT_P (operands[2]) @@ -2160,7 +1310,8 @@ (define_expand "andhi3" reg1 = reg0; } - emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (HImode, reg1, operands[2]))); + cris_emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (HImode, reg1, + operands[2]))); /* Make sure we get the right destination. */ if (! REG_P (operands[0])) @@ -2175,7 +1326,8 @@ (define_expand "andhi3" (define_insn "*andhi_movu" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To") - (const_int 255)))] + (const_int 255))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "!side_effects_p (operands[1])" "mOvu.b %1,%0" [(set_attr "slottable" "yes,yes,no")]) @@ -2183,7 +1335,8 @@ (define_insn "*andhi_movu" (define_insn "*andhi_clear" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To") (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0") - (const_int -256)))] + (const_int -256))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "!side_effects_p (operands[0])" "cLear.b %0" [(set_attr "slottable" "yes,yes,no") @@ -2194,7 +1347,8 @@ (define_insn "*andhi_clear" (define_insn "*expanded_andhi" [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") - (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] + (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] ;; Sidenote: the tightening from "general_operand" to ;; "register_operand" for operand 1 actually increased the register @@ -2241,7 +1395,8 @@ (define_insn "*andhi_lowpart" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r,r,r")) (and:HI (match_dup 0) - (match_operand:HI 1 "general_operand" "r,Q>,g")))] + (match_operand:HI 1 "general_operand" "r,Q>,g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ and.w %1,%0 @@ -2250,16 +1405,19 @@ (define_insn "*andhi_lowpart" [(set_attr "slottable" "yes,yes,no")]) (define_expand "andqi3" - [(set (match_operand:QI 0 "register_operand") - (and:QI (match_operand:QI 1 "register_operand") - (match_operand:QI 2 "general_operand")))] + [(parallel + [(set (match_operand:QI 0 "register_operand") + (and:QI (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") (define_insn "*andqi3" [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") - (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] + (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ andq %2,%0 @@ -2275,7 +1433,8 @@ (define_insn "*andqi_lowpart" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r,r,r")) (and:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "r,Q>,g")))] + (match_operand:QI 1 "general_operand" "r,Q>,g"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ and.b %1,%0 @@ -2291,16 +1450,19 @@ (define_insn "*andqi_lowpart" ;; with andsi3. (define_expand "ior3" - [(set (match_operand:BWD 0 "register_operand") - (ior:BWD (match_operand:BWD 1 "register_operand") - (match_operand:BWD 2 "general_operand")))] + [(parallel + [(set (match_operand:BWD 0 "register_operand") + (ior:BWD (match_operand:BWD 1 "register_operand") + (match_operand:BWD 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") (define_insn "*iorsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r") (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r") - (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))] + (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ orq %2,%0 @@ -2315,7 +1477,8 @@ (define_insn "*iorsi3" (define_insn "*iorhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r") (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r") - (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))] + (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ orq %2,%0 @@ -2331,7 +1494,8 @@ (define_insn "*iorhi3" (define_insn "*iorqi3" [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r") (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r") - (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))] + (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "@ orq %2,%0 @@ -2351,7 +1515,8 @@ (define_insn "*iorqi3" (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "register_operand" "r")))] + (match_operand:SI 2 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "xor %2,%0" [(set_attr "slottable" "yes")]) @@ -2359,7 +1524,8 @@ (define_insn "xorsi3" (define_insn "xor3" [(set (match_operand:BW 0 "register_operand" "=r") (xor:BW (match_operand:BW 1 "register_operand" "%0") - (match_operand:BW 2 "register_operand" "r")))] + (match_operand:BW 2 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "xor %2,%0" [(set_attr "slottable" "yes") @@ -2371,12 +1537,13 @@ (define_insn "xor3" ;; example. (define_expand "negsf2" - [(set (match_dup 2) - (match_dup 3)) - (parallel [(set (match_operand:SF 0 "register_operand" "=r") - (neg:SF (match_operand:SF 1 - "register_operand" "0"))) - (use (match_dup 2))])] + [(parallel + [(set (match_dup 2) (match_dup 3)) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel [(set (match_operand:SF 0 "register_operand") + (neg:SF (match_operand:SF 1 "register_operand"))) + (use (match_dup 2)) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { operands[2] = gen_reg_rtx (SImode); @@ -2386,7 +1553,8 @@ (define_expand "negsf2" (define_insn "*expanded_negsf2" [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (match_operand:SF 1 "register_operand" "0"))) - (use (match_operand:SI 2 "register_operand" "r"))] + (use (match_operand:SI 2 "register_operand" "r")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "xor %2,%0" [(set_attr "slottable" "yes")]) @@ -2396,7 +1564,8 @@ (define_insn "*expanded_negsf2" (define_insn "neg2" [(set (match_operand:BWD 0 "register_operand" "=r") - (neg:BWD (match_operand:BWD 1 "register_operand" "r")))] + (neg:BWD (match_operand:BWD 1 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "neg %1,%0" [(set_attr "slottable" "yes")]) @@ -2408,14 +1577,16 @@ (define_insn "neg2" (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (match_operand:SI 1 "register_operand" "0")))] + (not:SI (match_operand:SI 1 "register_operand" "0"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "not %0" [(set_attr "slottable" "yes")]) (define_insn "one_cmpl2" [(set (match_operand:BW 0 "register_operand" "=r") - (not:BW (match_operand:BW 1 "register_operand" "0")))] + (not:BW (match_operand:BW 1 "register_operand" "0"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "not %0" [(set_attr "slottable" "yes") @@ -2426,7 +1597,8 @@ (define_insn "one_cmpl2" (define_insn "si3" [(set (match_operand:SI 0 "register_operand" "=r") (shift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "Kcr")))] + (match_operand:SI 2 "nonmemory_operand" "Kcr"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" { if (REG_S_P (operands[2])) @@ -2447,13 +1619,21 @@ (define_insn "si3" ;; FIXME: Can't parametrize sign_extend and zero_extend (before ;; mentioning "shiftrt"), so we need two patterns. (define_expand "ashr3" - [(set (match_dup 3) - (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) - (set (match_dup 4) - (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) - (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:BW 0 "general_operand" "") - (subreg:BW (match_dup 5) 0))] + [(parallel + [(set (match_dup 3) + (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 4) + (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_operand:BW 0 "general_operand") + (subreg:BW (match_dup 5) 0)) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { int i; @@ -2463,13 +1643,21 @@ (define_expand "ashr3" }) (define_expand "lshr3" - [(set (match_dup 3) - (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) - (set (match_dup 4) - (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) - (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:BW 0 "general_operand" "") - (subreg:BW (match_dup 5) 0))] + [(parallel + [(set (match_dup 3) + (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 4) + (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_operand:BW 0 "general_operand") + (subreg:BW (match_dup 5) 0)) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { int i; @@ -2481,7 +1669,8 @@ (define_expand "lshr3" (define_insn "*expanded_" [(set (match_operand:BW 0 "register_operand" "=r") (shiftrt:BW (match_operand:BW 1 "register_operand" "0") - (match_operand:BW 2 "register_operand" "r")))] + (match_operand:BW 2 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" " %2,%0" [(set_attr "slottable" "yes")]) @@ -2489,7 +1678,8 @@ (define_insn "*expanded_" (define_insn "*_lowpart" [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) (shiftrt:BW (match_dup 0) - (match_operand:BW 1 "register_operand" "r")))] + (match_operand:BW 1 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" " %1,%0" [(set_attr "slottable" "yes")]) @@ -2503,7 +1693,8 @@ (define_insn "*_lowpart" (define_insn "ashl3" [(set (match_operand:BW 0 "register_operand" "=r,r") (ashift:BW (match_operand:BW 1 "register_operand" "0,0") - (match_operand:BW 2 "nonmemory_operand" "r,Kc")))] + (match_operand:BW 2 "nonmemory_operand" "r,Kc"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" { return @@ -2520,7 +1711,8 @@ (define_insn "ashl3" (define_insn "*ashl_lowpart" [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) (ashift:BW (match_dup 0) - (match_operand:HI 1 "register_operand" "r")))] + (match_operand:HI 1 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "lsl %1,%0" [(set_attr "slottable" "yes")]) @@ -2532,13 +1724,15 @@ (define_insn "*ashl_lowpart" (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=r") - (abs:SF (match_operand:SF 1 "register_operand" "0")))] + (abs:SF (match_operand:SF 1 "register_operand" "0"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "lslq 1,%0\;lsrq 1,%0") (define_insn "abssi2" [(set (match_operand:SI 0 "register_operand" "=r") - (abs:SI (match_operand:SI 1 "register_operand" "r")))] + (abs:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" "abs %1,%0" [(set_attr "slottable" "yes")]) @@ -2546,24 +1740,32 @@ (define_insn "abssi2" ;; FIXME: GCC should be able to do these expansions itself. (define_expand "abs2" - [(set (match_dup 2) - (sign_extend:SI (match_operand:BW 1 "general_operand" ""))) - (set (match_dup 3) (abs:SI (match_dup 2))) - (set (match_operand:BW 0 "register_operand" "") - (subreg:BW (match_dup 3) 0))] + [(parallel + [(set (match_dup 2) + (sign_extend:SI (match_operand:BW 1 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 3) (abs:SI (match_dup 2))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_operand:BW 0 "register_operand") + (subreg:BW (match_dup 3) 0)) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") (define_insn "clzsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (clz:SI (match_operand:SI 1 "register_operand" "r")))] + (clz:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_LZ" "lz %1,%0" [(set_attr "slottable" "yes")]) (define_insn "bswapsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (bswap:SI (match_operand:SI 1 "register_operand" "0")))] + (bswap:SI (match_operand:SI 1 "register_operand" "0"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_SWAP" "swapwb %0" [(set_attr "slottable" "yes")]) @@ -2575,7 +1777,8 @@ (define_insn "bswapsi2" (define_insn "cris_swap_bits" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "0")] - CRIS_UNSPEC_SWAP_BITS))] + CRIS_UNSPEC_SWAP_BITS)) + (clobber (reg:CC CRIS_CC0_REGNUM))] "TARGET_HAS_SWAP" "swapwbr %0" [(set_attr "slottable" "yes")]) @@ -2584,12 +1787,18 @@ (define_insn "cris_swap_bits" ;; Defines a scratch register to avoid clobbering input. (define_expand "ctzsi2" - [(set (match_dup 2) - (match_operand:SI 1 "register_operand")) - (set (match_dup 2) - (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS)) - (set (match_operand:SI 0 "register_operand") - (clz:SI (match_dup 2)))] + [(parallel + [(set (match_dup 2) + (match_operand:SI 1 "register_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 2) + (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS)) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_operand:SI 0 "register_operand") + (clz:SI (match_dup 2))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "TARGET_HAS_LZ && TARGET_HAS_SWAP" "operands[2] = gen_reg_rtx (SImode);") @@ -2598,16 +1807,19 @@ (define_expand "ctzsi2" ;; normal code too. (define_expand "uminsi3" - [(set (match_operand:SI 0 "register_operand" "") - (umin:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "general_operand" "")))] + [(parallel + [(set (match_operand:SI 0 "register_operand") + (umin:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "general_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") (define_insn "*uminsi3" [(set (match_operand:SI 0 "register_operand" "=r,r, r,r") (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r") - (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))] + (match_operand:SI 2 "general_operand" "r,Q>,g,!To"))) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" { if (CONST_INT_P (operands[2])) @@ -2691,27 +1903,35 @@ (define_expand "epilogue" ;; Conditional branches. (define_expand "cbranch4" - [(set (cc0) (compare - (match_operand:BWD 1 "nonimmediate_operand") - (match_operand:BWD 2 "general_operand"))) - (set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" - [(cc0) (const_int 0)]) - (label_ref (match_operand 3 "" "")) - (pc)))] + [(parallel + [(set (pc) + (if_then_else + (match_operator 0 "ordered_comparison_operator" + [(match_operand:BWDD 1 "nonimmediate_operand") + (match_operand:BWDD 2 "general_operand")]) + (label_ref (match_operand 3 "")) + (pc))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") -(define_expand "cbranchdi4" - [(set (cc0) - (compare (match_operand:DI 1 "nonimmediate_operand" "") - (match_operand:DI 2 "general_operand" ""))) +(define_insn_and_split "*cbranch4" + [(set (pc) + (if_then_else + (match_operator 0 "ordered_comparison_operator" + [(match_operand:BWDD 1 "nonimmediate_operand" "") + (match_operand:BWDD 2 "general_operand" "")]) + (label_ref (match_operand 3 "")) + (pc))) + (clobber (reg:CC CRIS_CC0_REGNUM))] + "" + "#" + "&& reload_completed" + [(set (reg:CC CRIS_CC0_REGNUM) (compare:CC (match_dup 1) (match_dup 2))) (set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" - [(cc0) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (if_then_else (match_op_dup 0 [(reg:CC CRIS_CC0_REGNUM) (const_int 0)]) + (label_ref (match_dup 3)) (pc)))] - "" "") @@ -2721,136 +1941,123 @@ (define_expand "cbranchdi4" (define_insn "b" [(set (pc) - (if_then_else (ncond (cc0) + (if_then_else (ncond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "" + "reload_completed" "b %l0%#" [(set_attr "slottable" "has_slot")]) (define_insn "b" [(set (pc) - (if_then_else (ocond (cc0) + (if_then_else (ocond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : "b %l0%#"; -} + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "b %l0%#" [(set_attr "slottable" "has_slot")]) (define_insn "b" [(set (pc) - (if_then_else (rcond (cc0) + (if_then_else (rcond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? "b %l0%#" : "b %l0%#"; -} + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "b %l0%#" [(set_attr "slottable" "has_slot")]) ;; Reversed anonymous patterns to the ones above, as mandated. (define_insn "*b_reversed" [(set (pc) - (if_then_else (ncond (cc0) + (if_then_else (ncond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] - "" + "reload_completed" "b %l0%#" [(set_attr "slottable" "has_slot")]) (define_insn "*b_reversed" [(set (pc) - (if_then_else (ocond (cc0) + (if_then_else (ocond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : "b %l0%#"; -} + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "b %l0%#" [(set_attr "slottable" "has_slot")]) (define_insn "*b_reversed" [(set (pc) - (if_then_else (rcond (cc0) + (if_then_else (rcond (reg:CC CRIS_CC0_REGNUM) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? "b %l0%#" : "b %l0%#"; -} + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "b %l0%#" [(set_attr "slottable" "has_slot")]) ;; Set on condition: sCC. -(define_expand "cstoredi4" - [(set (cc0) (compare - (match_operand:DI 2 "nonimmediate_operand") - (match_operand:DI 3 "general_operand"))) - (set (match_operand:SI 0 "register_operand") - (match_operator:SI 1 "ordered_comparison_operator" - [(cc0) (const_int 0)]))] +(define_expand "cstore4" + [(parallel + [(set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:BWDD 2 "nonimmediate_operand") + (match_operand:BWDD 3 "general_operand")])) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" "") -(define_expand "cstore4" - [(set (cc0) (compare - (match_operand:BWD 2 "nonimmediate_operand") - (match_operand:BWD 3 "general_operand"))) - (set (match_operand:SI 0 "register_operand") +(define_insn_and_split "*cstore4" + [(set (match_operand:SI 0 "register_operand" "=") (match_operator:SI 1 "ordered_comparison_operator" - [(cc0) (const_int 0)]))] + [(match_operand:BWDD 2 "nonimmediate_operand" "") + (match_operand:BWDD 3 "general_operand" "")])) + (clobber (reg:CC CRIS_CC0_REGNUM))] "" + "#" + "&& reload_completed" + [(set (reg:CC CRIS_CC0_REGNUM) (compare:CC (match_dup 2) (match_dup 3))) + (set (match_operand:SI 0 "register_operand") + (match_operator:SI 1 "ordered_comparison_operator" + [(reg:CC CRIS_CC0_REGNUM) (const_int 0)]))] "") ;; Like bCC, we have to check the overflow bit for ;; signed conditions. -(define_insn "s" +(define_insn "*s" [(set (match_operand:SI 0 "register_operand" "=r") - (ncond:SI (cc0) (const_int 0)))] - "" + (ncond:SI (reg:CC CRIS_CC0_REGNUM) (const_int 0)))] + "reload_completed" "s %0" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) -(define_insn "s" +(define_insn "*s" [(set (match_operand:SI 0 "register_operand" "=r") - (rcond:SI (cc0) (const_int 0)))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? "s %0" : "s %0"; -} + (rcond:SI (reg:CC CRIS_CC0_REGNUM) (const_int 0)))] + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "s %0" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) -(define_insn "s" +(define_insn "*s" [(set (match_operand:SI 0 "register_operand" "=r") - (ocond:SI (cc0) (const_int 0)))] - "" -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : "s %0"; -} + (ocond:SI (reg:CC CRIS_CC0_REGNUM) (const_int 0)))] + "reload_completed" + ;; FIXME: optimize out the compare and handle CC_NO_OVERFLOW. + "s %0" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) @@ -2945,13 +2152,19 @@ (define_insn "cris_frame_deallocated_barrier" ;; accordingly, to add the default case at the end of the jump-table. (define_expand "casesi" - [(set (match_dup 5) (match_operand:SI 0 "general_operand" "")) - (set (match_dup 6) - (minus:SI (match_dup 5) - (match_operand:SI 1 "const_int_operand" "n"))) - (set (match_dup 7) - (umin:SI (match_dup 6) - (match_operand:SI 2 "const_int_operand" "n"))) + [(parallel + [(set (match_dup 5) (match_operand:SI 0 "general_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 6) + (minus:SI (match_dup 5) + (match_operand:SI 1 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 7) + (umin:SI (match_dup 6) + (match_operand:SI 2 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) (parallel [(set (pc) (if_then_else @@ -2961,8 +2174,9 @@ (define_expand "casesi" (plus:SI (mult:SI (match_dup 7) (const_int 2)) (pc)))) (pc)) - (label_ref (match_operand 4 "" "")))) - (use (label_ref (match_operand 3 "" "")))])] + (label_ref (match_operand 4 "")))) + (use (label_ref (match_operand 3 ""))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "" { operands[2] = plus_constant (SImode, operands[2], 1); @@ -2970,658 +2184,11 @@ (define_expand "casesi" operands[6] = gen_reg_rtx (SImode); operands[7] = gen_reg_rtx (SImode); }) - -;; Split-patterns. Some of them have modes unspecified. This -;; should always be ok; if for no other reason sparc.md has it as -;; well. -;; -;; When register_operand is specified for an operand, we can get a -;; subreg as well (Axis-990331), so don't just assume that REG_P is true -;; for a register_operand and that REGNO can be used as is. It is best to -;; guard with REG_P, unless it is worth it to adjust for the subreg case. - -;; op [rx + 0],ry,rz -;; The index to rx is optimized into zero, and gone. - -;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended, -;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx]. -;; Split this into: -;; move ry,rz -;; op [rx],rz -;; Lose if rz=ry or rx=rz. -;; Call this op-extend-split. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 4 "cris_operand_extend_operator" - [(match_operand 1 "register_operand" "") - (match_operator - 3 "cris_extend_operator" - [(match_operand 2 "memory_operand" "")])]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 1)) - (set (match_dup 0) - (match_op_dup - 4 [(match_dup 0) - (match_op_dup 3 [(match_dup 2)])]))] - "") - -;; As op-extend-split, but recognize and split op [rz],ry,rz into -;; ext [rz],rz -;; op ry,rz -;; Do this for plus or bound only, being commutative operations, since we -;; have swapped the operands. -;; Call this op-extend-split-rx=rz - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 4 "cris_plus_or_bound_operator" - [(match_operand 1 "register_operand" "") - (match_operator - 3 "cris_extend_operator" - [(match_operand 2 "memory_operand" "")])]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" - [(set (match_dup 0) - (match_op_dup 3 [(match_dup 2)])) - (set (match_dup 0) - (match_op_dup - 4 [(match_dup 0) - (match_dup 1)]))] - "") - -;; As the op-extend-split, but swapped operands, and only for -;; plus or bound, being the commutative extend-operators. FIXME: Why is -;; this needed? Is it? -;; Call this op-extend-split-swapped - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 4 "cris_plus_or_bound_operator" - [(match_operator - 3 "cris_extend_operator" - [(match_operand 2 "memory_operand" "")]) - (match_operand 1 "register_operand" "")]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 1)) - (set (match_dup 0) - (match_op_dup - 4 [(match_dup 0) - (match_op_dup 3 [(match_dup 2)])]))] - "") - -;; As op-extend-split-rx=rz, but swapped operands, only for plus or -;; bound. Call this op-extend-split-swapped-rx=rz. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 4 "cris_plus_or_bound_operator" - [(match_operator - 3 "cris_extend_operator" - [(match_operand 2 "memory_operand" "")]) - (match_operand 1 "register_operand" "")]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" - [(set (match_dup 0) - (match_op_dup 3 [(match_dup 2)])) - (set (match_dup 0) - (match_op_dup - 4 [(match_dup 0) - (match_dup 1)]))] - "") - -;; As op-extend-split, but the mem operand is not extended. -;; -;; op [rx],ry,rz changed into -;; move ry,rz -;; op [rx],rz -;; lose if ry=rz or rx=rz -;; Call this op-extend. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 3 "cris_orthogonal_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "memory_operand" "")]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 1)) - (set (match_dup 0) - (match_op_dup - 3 [(match_dup 0) - (match_dup 2)]))] - "") - -;; As op-extend-split-rx=rz, non-extended. -;; Call this op-split-rx=rz - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 3 "cris_commutative_orth_op" - [(match_operand 2 "memory_operand" "") - (match_operand 1 "register_operand" "")]))] - "REG_P (operands[0]) - && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 1)) - (set (match_dup 0) - (match_op_dup - 3 [(match_dup 0) - (match_dup 2)]))] - "") - -;; As op-extend-split-swapped, nonextended. -;; Call this op-split-swapped. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 3 "cris_commutative_orth_op" - [(match_operand 1 "register_operand" "") - (match_operand 2 "memory_operand" "")]))] - "REG_P (operands[0]) && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 2)) - (set (match_dup 0) - (match_op_dup - 3 [(match_dup 0) - (match_dup 1)]))] - "") - -;; As op-extend-split-swapped-rx=rz, non-extended. -;; Call this op-split-swapped-rx=rz. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 3 "cris_orthogonal_operator" - [(match_operand 2 "memory_operand" "") - (match_operand 1 "register_operand" "")]))] - "REG_P (operands[0]) && REG_P (operands[1]) - && REGNO (operands[1]) != REGNO (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && REG_P (XEXP (operands[2], 0)) - && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])" - [(set (match_dup 0) - (match_dup 2)) - (set (match_dup 0) - (match_op_dup - 3 [(match_dup 0) - (match_dup 1)]))] - "") (include "sync.md") -;; Splits for all cases in side-effect insns where (possibly after reload -;; and register allocation) rx and ry in [rx=ry+i] are equal. - -;; move.S1 [rx=rx+rz.S2],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_mem_op" - [(plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "register_operand" ""))])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))])] - "REG_P (operands[3]) && REG_P (operands[4]) - && REGNO (operands[3]) == REGNO (operands[4])" - [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) (match_dup 5))] - "operands[5] = replace_equiv_address (operands[6], operands[3]);") - -;; move.S1 [rx=rx+i],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 5 "cris_mem_op" - [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "") - (match_operand:SI 2 "cris_bdap_operand" ""))])) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (match_dup 1) - (match_dup 2)))])] - "(rtx_equal_p (operands[3], operands[1]) - || rtx_equal_p (operands[3], operands[2]))" - [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) (match_dup 4))] -{ - operands[4] = replace_equiv_address (operands[5], operands[3]); - cris_order_for_addsi3 (operands, 1); -}) - -;; move.S1 ry,[rx=rx+rz.S2] - -(define_split - [(parallel - [(set (match_operator - 6 "cris_mem_op" - [(plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "")) - (match_operand:SI 2 "register_operand" ""))]) - (match_operand 3 "register_operand" "")) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))])] - "REG_P (operands[2]) && REG_P (operands[4]) - && REGNO (operands[4]) == REGNO (operands[2])" - [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) - (match_dup 2))) - (set (match_dup 5) (match_dup 3))] - "operands[5] = replace_equiv_address (operands[6], operands[4]);") - -;; move.S1 ry,[rx=rx+i] - -(define_split - [(parallel - [(set (match_operator - 6 "cris_mem_op" - [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "") - (match_operand:SI 1 "cris_bdap_operand" ""))]) - (match_operand 2 "register_operand" "")) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (match_dup 0) - (match_dup 1)))])] - "(rtx_equal_p (operands[3], operands[0]) - || rtx_equal_p (operands[3], operands[1]))" - [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1))) - (set (match_dup 5) (match_dup 2))] -{ - operands[5] = replace_equiv_address (operands[6], operands[3]); - cris_order_for_addsi3 (operands, 0); -}) - -;; clear.[bwd] [rx=rx+rz.S2] - -(define_split - [(parallel - [(set (mem:BWD (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "")) - (match_operand:SI 2 "register_operand" ""))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))])] - "REG_P (operands[2]) && REG_P (operands[3]) - && REGNO (operands[3]) == REGNO (operands[2])" - [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) - (match_dup 2))) - (set (mem:BWD (match_dup 3)) (const_int 0))] - "") - -;; clear.[bwd] [rx=rx+i] - -(define_split - [(parallel - [(set (mem:BWD - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") - (match_operand:SI 1 "cris_bdap_operand" ""))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "") - (plus:SI (match_dup 0) - (match_dup 1)))])] - "(rtx_equal_p (operands[0], operands[2]) - || rtx_equal_p (operands[2], operands[1]))" - [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) - (set (mem:BWD (match_dup 2)) (const_int 0))] - "cris_order_for_addsi3 (operands, 0);") - -;; mov(s|u).S1 [rx=rx+rz.S2],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 5 "cris_extend_operator" - [(mem (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "")) - (match_operand:SI 3 "register_operand" "")))])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))])] - "REG_P (operands[3]) - && REG_P (operands[4]) - && REGNO (operands[3]) == REGNO (operands[4])" - [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) - (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))] - "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);") - -;; mov(s|u).S1 [rx=rx+i],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 4 "cris_extend_operator" - [(mem (plus:SI - (match_operand:SI 1 "cris_bdap_operand" "") - (match_operand:SI 2 "cris_bdap_operand" "")))])) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (match_dup 1) - (match_dup 2)))])] - "(rtx_equal_p (operands[1], operands[3]) - || rtx_equal_p (operands[2], operands[3]))" - [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))] -{ - operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]); - cris_order_for_addsi3 (operands, 1); -}) - -;; op.S1 [rx=rx+i],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 5 "cris_orthogonal_operator" - [(match_operand 1 "register_operand" "") - (mem (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "") - (match_operand:SI 3 "cris_bdap_operand" "")))])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (match_dup 2) - (match_dup 3)))])] - "(rtx_equal_p (operands[4], operands[2]) - || rtx_equal_p (operands[4], operands[3]))" - [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) - (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))] -{ - operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]); - cris_order_for_addsi3 (operands, 2); -}) - -;; op.S1 [rx=rx+rz.S2],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_orthogonal_operator" - [(match_operand 1 "register_operand" "") - (mem (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (match_operand:SI 4 "register_operand" "")))])) - (set (match_operand:SI 5 "register_operand" "") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))])] - "REG_P (operands[4]) - && REG_P (operands[5]) - && REGNO (operands[5]) == REGNO (operands[4])" - [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) - (match_dup 4))) - (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))] - "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);") - -;; op.S1 [rx=rx+rz.S2],ry (swapped) - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_commutative_orth_op" - [(mem (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (match_operand:SI 4 "register_operand" ""))) - (match_operand 1 "register_operand" "")])) - (set (match_operand:SI 5 "register_operand" "") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))])] - "REG_P (operands[4]) - && REG_P (operands[5]) - && REGNO (operands[5]) == REGNO (operands[4])" - [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) - (match_dup 4))) - (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] - "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);") - -;; op.S1 [rx=rx+i],ry (swapped) - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 5 "cris_commutative_orth_op" - [(mem - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") - (match_operand:SI 3 "cris_bdap_operand" ""))) - (match_operand 1 "register_operand" "")])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (match_dup 2) - (match_dup 3)))])] - "(rtx_equal_p (operands[4], operands[2]) - || rtx_equal_p (operands[4], operands[3]))" - [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) - (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))] -{ - operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]); - cris_order_for_addsi3 (operands, 2); -}) - -;; op(s|u).S1 [rx=rx+rz.S2],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_operand_extend_operator" - [(match_operand 1 "register_operand" "") - (match_operator - 7 "cris_extend_operator" - [(mem (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (match_operand:SI 4 "register_operand" "")))])])) - (set (match_operand:SI 5 "register_operand" "") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))])] - "REG_P (operands[4]) - && REG_P (operands[5]) - && REGNO (operands[5]) == REGNO (operands[4])" - [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) - (match_dup 4))) - (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))] - "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]), - replace_equiv_address (XEXP (operands[7], 0), - operands[5]));") - -;; op(s|u).S1 [rx=rx+i],ry - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 5 "cris_operand_extend_operator" - [(match_operand 1 "register_operand" "") - (match_operator - 6 "cris_extend_operator" - [(mem - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "") - (match_operand:SI 3 "cris_bdap_operand" "") - ))])])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (match_dup 2) - (match_dup 3)))])] - "(rtx_equal_p (operands[4], operands[2]) - || rtx_equal_p (operands[4], operands[3]))" - [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) - (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))] -{ - operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), - replace_equiv_address (XEXP (operands[6], 0), - operands[4])); - cris_order_for_addsi3 (operands, 2); -}) - -;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound) - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 7 "cris_plus_or_bound_operator" - [(match_operator - 6 "cris_extend_operator" - [(mem (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "const_int_operand" "")) - (match_operand:SI 4 "register_operand" "")))]) - (match_operand 1 "register_operand" "")])) - (set (match_operand:SI 5 "register_operand" "") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))])] - "REG_P (operands[4]) && REG_P (operands[5]) - && REGNO (operands[5]) == REGNO (operands[4])" - [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3)) - (match_dup 4))) - (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))] - "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]), - replace_equiv_address (XEXP (operands[6], 0), - operands[5]));") - -;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound) - -(define_split - [(parallel - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_plus_or_bound_operator" - [(match_operator - 5 "cris_extend_operator" - [(mem (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "") - (match_operand:SI 3 "cris_bdap_operand" "")))]) - (match_operand 1 "register_operand" "")])) - (set (match_operand:SI 4 "register_operand" "") - (plus:SI (match_dup 2) - (match_dup 3)))])] - "(rtx_equal_p (operands[4], operands[2]) - || rtx_equal_p (operands[4], operands[3]))" - [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3))) - (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))] -{ - operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]), - replace_equiv_address (XEXP (operands[5], 0), - operands[4])); - cris_order_for_addsi3 (operands, 2); -}) - -;; Splits for addressing prefixes that have no side-effects, so we can -;; fill a delay slot. Never split if we lose something, though. - -;; If we have a -;; move [indirect_ref],rx -;; where indirect ref = {const, [r+], [r]}, it costs as much as -;; move indirect_ref,rx -;; move [rx],rx -;; Take care not to allow indirect_ref = register. - -;; We're not allowed to generate copies of registers with different mode -;; until after reload; copying pseudos upsets reload. CVS as of -;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in -;; cselib_invalidate_regno. Also, don't do this for the stack-pointer, -;; as we don't want it set temporarily to an invalid value. - -(define_split ; indir_to_reg_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operand 1 "indirect_operand" ""))] - "reload_completed - && REG_P (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0))) - && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER" - [(set (match_dup 2) (match_dup 4)) - (set (match_dup 0) (match_dup 3))] - "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); - operands[3] = replace_equiv_address (operands[1], operands[2]); - operands[4] = XEXP (operands[1], 0);") - -;; As the above, but MOVS and MOVU. - -(define_split - [(set (match_operand 0 "cris_nonsp_register_operand" "") - (match_operator - 4 "cris_extend_operator" - [(match_operand 1 "indirect_operand" "")]))] - "reload_completed - && REG_P (operands[0]) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && (MEM_P (XEXP (operands[1], 0)) - || CONSTANT_P (XEXP (operands[1], 0)))" - [(set (match_dup 2) (match_dup 5)) - (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))] - "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0])); - operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]); - operands[5] = XEXP (operands[1], 0);") - ;; Various peephole optimizations. ;; -;; Watch out: when you exchange one set of instructions for another, the -;; condition codes setting must be the same, or you have to CC_INIT or -;; whatever is appropriate, in the pattern before you emit the -;; assembly text. This is best done here, not in cris_notice_update_cc, -;; to keep changes local to their cause. -;; ;; Do not add patterns that you do not know will be matched. ;; Please also add a self-contained testcase. @@ -3630,13 +2197,17 @@ (define_split ;; suboptimal when not having extzv insns. ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c -(define_peephole2 ; asrandb (peephole casesi+31) - [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_dup 0) - (match_operand:SI 1 "const_int_operand" ""))) - (set (match_dup 0) +(define_peephole2 ; asrandb + [(parallel + [(set (match_operand:SI 0 "register_operand") + (ashiftrt:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) (and:SI (match_dup 0) - (match_operand 2 "const_int_operand" "")))] + (match_operand 2 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 255 && INTVAL (operands[1]) > 23 @@ -3644,20 +2215,27 @@ (define_peephole2 ; asrandb (peephole casesi+31) && (INTVAL (operands[2]) & ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U << (32 - INTVAL (operands[1]))))) == 0" - [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) - (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))] - ;; FIXME: CC0 is valid except for the M bit. + [(parallel + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { operands[3] = gen_rtx_REG (QImode, REGNO (operands[0])); operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode)); }) -(define_peephole2 ; asrandw (peephole casesi+32) - [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_dup 0) - (match_operand:SI 1 "const_int_operand" ""))) - (set (match_dup 0) - (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] +(define_peephole2 ; asrandw + [(parallel + [(set (match_operand:SI 0 "register_operand") + (ashiftrt:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) + (and:SI (match_dup 0) (match_operand 2 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535 && INTVAL (operands[2]) != 255 @@ -3666,311 +2244,64 @@ (define_peephole2 ; asrandw (peephole casesi+32) && (INTVAL (operands[2]) & ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U << (32 - INTVAL (operands[1]))))) == 0" - [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) - (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))] - ;; FIXME: CC0 is valid except for the M bit. + [(parallel + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode)); }) -(define_peephole2 ; lsrandb (peephole casesi+33) - [(set (match_operand:SI 0 "register_operand" "") - (lshiftrt:SI (match_dup 0) - (match_operand:SI 1 "const_int_operand" ""))) - (set (match_dup 0) - (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] +(define_peephole2 ; lsrandb + [(parallel + [(set (match_operand:SI 0 "register_operand") + (lshiftrt:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) + (and:SI (match_dup 0) (match_operand 2 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 255 && INTVAL (operands[1]) > 23" - [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) - (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))] - ;; FIXME: CC0 is valid except for the M bit. + [(parallel + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { operands[3] = gen_rtx_REG (QImode, REGNO (operands[0])); operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode)); }) -(define_peephole2 ; lsrandw (peephole casesi+34) - [(set (match_operand:SI 0 "register_operand" "") +(define_peephole2 ; lsrandw + [(parallel + [(set (match_operand:SI 0 "register_operand") (lshiftrt:SI (match_dup 0) - (match_operand:SI 1 "const_int_operand" ""))) - (set (match_dup 0) - (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))] + (match_operand:SI 1 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) + (and:SI (match_dup 0) (match_operand 2 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535 && INTVAL (operands[2]) != 255 && INTVAL (operands[1]) > 15" - [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) - (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))] - ;; FIXME: CC0 is valid except for the M bit. + [(parallel + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode)); }) - - -;; Change -;; add.d n,rx -;; move [rx],ry -;; into -;; move [rx=rx+n],ry -;; when -128 <= n <= 127. -;; This will reduce the size of the assembler code for n = [-128..127], -;; and speed up accordingly. Don't match if the previous insn is -;; (set rx rz) because that combination is matched by another peephole. -;; No stable test-case. - -(define_peephole2 ; moversideqi (peephole casesi+35) - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) - (set (match_operand 3 "register_operand" "") - (match_operator 4 "cris_mem_op" [(match_dup 0)]))] - "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD - && REGNO (operands[3]) != REGNO (operands[0]) - && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true)) - && !satisfies_constraint_J (operands[2]) - && !satisfies_constraint_N (operands[2]) - && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128) - && TARGET_SIDE_EFFECT_PREFIXES" - [(parallel - [(set (match_dup 3) (match_dup 5)) - (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] - ;; Checking the previous insn is a bit too awkward for the condition. -{ - rtx_insn *prev = prev_nonnote_insn (curr_insn); - if (prev != NULL_RTX) - { - rtx set = single_set (prev); - if (set != NULL_RTX - && REG_S_P (SET_DEST (set)) - && REGNO (SET_DEST (set)) == REGNO (operands[0]) - && REG_S_P (SET_SRC (set))) - FAIL; - } - operands[5] - = replace_equiv_address (operands[4], - gen_rtx_PLUS (SImode, - operands[1], operands[2])); -}) - -;; Vice versa: move ry,[rx=rx+n] - -(define_peephole2 ; movemsideqi (peephole casesi+36) - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) - (set (match_operator 3 "cris_mem_op" [(match_dup 0)]) - (match_operand 4 "register_operand" ""))] - "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD - && REGNO (operands[4]) != REGNO (operands[0]) - && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true)) - && !satisfies_constraint_J (operands[2]) - && !satisfies_constraint_N (operands[2]) - && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128) - && TARGET_SIDE_EFFECT_PREFIXES" - [(parallel - [(set (match_dup 5) (match_dup 4)) - (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] - "operands[5] - = replace_equiv_address (operands[3], - gen_rtx_PLUS (SImode, - operands[1], operands[2]));") - -;; As above, change: -;; add.d n,rx -;; op.d [rx],ry -;; into: -;; op.d [rx=rx+n],ry -;; Saves when n = [-128..127]. -;; -;; Splitting and joining combinations for side-effect modes are slightly -;; out of hand. They probably will not save the time they take typing in, -;; not to mention the bugs that creep in. FIXME: Get rid of as many of -;; the splits and peepholes as possible. -;; No stable test-case. - -(define_peephole2 ; mover2side (peephole casesi+37) - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) - (set (match_operand 3 "register_operand" "") - (match_operator 4 "cris_orthogonal_operator" - [(match_dup 3) - (match_operator - 5 "cris_mem_op" [(match_dup 0)])]))] - ;; FIXME: What about DFmode? - ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD? - "GET_MODE (operands[3]) != DImode - && REGNO (operands[0]) != REGNO (operands[3]) - && !satisfies_constraint_J (operands[2]) - && !satisfies_constraint_N (operands[2]) - && INTVAL (operands[2]) >= -128 - && INTVAL (operands[2]) <= 127 - && TARGET_SIDE_EFFECT_PREFIXES" - [(parallel - [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)])) - (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])] - "operands[6] - = replace_equiv_address (operands[5], - gen_rtx_PLUS (SImode, - operands[1], operands[2]));") - -;; Sometimes, for some reason the pattern -;; move x,rx -;; add y,rx -;; move [rx],rz -;; will occur. Solve this, and likewise for to-memory. -;; No stable test-case. - -(define_peephole2 ; moverside (peephole casesi+38) - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "cris_bdap_biap_operand" "")) - (set (match_dup 0) - (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "") - (match_operand:SI 3 "cris_bdap_biap_operand" ""))) - (set (match_operand 4 "register_operand" "") - (match_operator 5 "cris_mem_op" [(match_dup 0)]))] - "(rtx_equal_p (operands[2], operands[0]) - || rtx_equal_p (operands[3], operands[0])) - && cris_side_effect_mode_ok (PLUS, operands, 0, - (REG_S_P (operands[1]) - ? 1 - : (rtx_equal_p (operands[2], operands[0]) - ? 3 : 2)), - (! REG_S_P (operands[1]) - ? 1 - : (rtx_equal_p (operands[2], operands[0]) - ? 3 : 2)), - -1, 4)" - [(parallel - [(set (match_dup 4) (match_dup 6)) - (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])] -{ - rtx otherop - = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2]; - - /* Make sure we have canonical RTX so we match the insn pattern - - not a constant in the first operand. We also require the order - (plus reg mem) to match the final pattern. */ - if (CONSTANT_P (otherop) || MEM_P (otherop)) - { - operands[7] = operands[1]; - operands[8] = otherop; - } - else - { - operands[7] = otherop; - operands[8] = operands[1]; - } - operands[6] - = replace_equiv_address (operands[5], - gen_rtx_PLUS (SImode, - operands[7], operands[8])); -}) - -;; As above but to memory. -;; FIXME: Split movemside and moverside into variants and prune -;; the ones that don't trig. -;; No stable test-case. - -(define_peephole2 ; movemside (peephole casesi+39) - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "cris_bdap_biap_operand" "")) - (set (match_dup 0) - (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "") - (match_operand:SI 3 "cris_bdap_biap_operand" ""))) - (set (match_operator 4 "cris_mem_op" [(match_dup 0)]) - (match_operand 5 "register_operand" ""))] - "(rtx_equal_p (operands[2], operands[0]) - || rtx_equal_p (operands[3], operands[0])) - && cris_side_effect_mode_ok (PLUS, operands, 0, - (REG_S_P (operands[1]) - ? 1 - : (rtx_equal_p (operands[2], operands[0]) - ? 3 : 2)), - (! REG_S_P (operands[1]) - ? 1 - : (rtx_equal_p (operands[2], operands[0]) - ? 3 : 2)), - -1, 5)" - [(parallel - [(set (match_dup 6) (match_dup 5)) - (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])] -{ - rtx otherop - = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2]; - - /* Make sure we have canonical RTX so we match the insn pattern - - not a constant in the first operand. We also require the order - (plus reg mem) to match the final pattern. */ - if (CONSTANT_P (otherop) || MEM_P (otherop)) - { - operands[7] = operands[1]; - operands[8] = otherop; - } - else - { - operands[7] = otherop; - operands[8] = operands[1]; - } - operands[6] - = replace_equiv_address (operands[4], - gen_rtx_PLUS (SImode, - operands[7], operands[8])); -}) - -;; Another spotted bad code: -;; move rx,ry -;; move [ry],ry -;; No stable test-case. - -(define_peephole2 ; movei (peephole casesi+42) - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")) - (set (match_operand 2 "register_operand" "") - (match_operator 3 "cris_mem_op" [(match_dup 0)]))] - "REGNO (operands[0]) == REGNO (operands[2]) - && (REGNO_REG_CLASS (REGNO (operands[0])) - == REGNO_REG_CLASS (REGNO (operands[1]))) - && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD" - [(set (match_dup 2) (match_dup 4))] - "operands[4] = replace_equiv_address (operands[3], operands[1]);") - -;; move.d [r10+16],r9 -;; and.d r12,r9 -;; change to -;; and.d [r10+16],r12,r9 -;; With generalization of the operation, the size and the addressing mode. -;; This seems to be the result of a quirk in register allocation -;; missing the three-operand cases when having different predicates. -;; Maybe that it matters that it is a commutative operation. -;; This pattern helps that situation, but there's still the increased -;; register pressure. -;; Note that adding the noncommutative variant did not show any matches -;; in ipps and cc1, so it's not here. -;; No stable test-case. - -(define_peephole2 ; op3 (peephole casesi+44) - [(set (match_operand 0 "register_operand" "") - (match_operator - 6 "cris_mem_op" - [(plus:SI - (match_operand:SI 1 "cris_bdap_biap_operand" "") - (match_operand:SI 2 "cris_bdap_biap_operand" ""))])) - (set (match_dup 0) - (match_operator - 5 "cris_commutative_orth_op" - [(match_operand 3 "register_operand" "") - (match_operand 4 "register_operand" "")]))] - "(rtx_equal_p (operands[3], operands[0]) - || rtx_equal_p (operands[4], operands[0])) - && ! rtx_equal_p (operands[3], operands[4]) - && (REG_S_P (operands[1]) || REG_S_P (operands[2])) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD" - [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))] - "operands[7] - = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];") ;; There seems to be no other way to make GCC (including 4.8/trunk at ;; r186932) optimally reload an instruction that looks like @@ -3985,12 +2316,16 @@ (define_peephole2 ; op3 (peephole casesi+44) ;; Fix it with these two peephole2's. ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c -(define_peephole2 ; andu (casesi+45) - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "nonimmediate_operand" "")) - (set (match_operand:SI 2 "register_operand" "") - (and:SI (match_dup 0) - (match_operand:SI 3 "const_int_operand" "")))] +(define_peephole2 ; andu + [(parallel + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "nonimmediate_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_operand:SI 2 "register_operand") + (and:SI (match_dup 0) + (match_operand:SI 3 "const_int_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] ;; Since the size of the memory access could be made different here, ;; don't do this for a mem-volatile access. "REGNO (operands[2]) == REGNO (operands[0]) @@ -3999,9 +2334,12 @@ (define_peephole2 ; andu (casesi+45) && !side_effects_p (operands[1]) && (!REG_P (operands[1]) || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)" - ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE). - [(set (match_dup 0) (match_dup 4)) - (set (match_dup 5) (match_dup 6))] + [(parallel + [(set (match_dup 0) (match_dup 4)) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 5) (match_dup 6)) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode; machine_mode amode @@ -4028,18 +2366,26 @@ (define_peephole2 ; andu (casesi+45) ;; movu.b $r10,$r9 ;; andq -2,$r9. ;; Only do this for values fitting the quick immediate operand. -(define_peephole2 ; andqu (casesi+46) - [(set (match_operand:SI 0 "register_operand") - (match_operand:SI 1 "const_int_operand")) - (set (match_dup 0) - (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand")))] +(define_peephole2 ; andqu + [(parallel + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "const_int_operand")) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) + (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand"))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] ;; Since the size of the memory access will be made different here, ;; don't do this for a volatile access or a post-incremented address. "satisfies_constraint_O (operands[1]) && !side_effects_p (operands[2]) && !reg_overlap_mentioned_p (operands[0], operands[2])" - [(set (match_dup 0) (match_dup 3)) - (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] + [(parallel + [(set (match_dup 0) (match_dup 3)) + (clobber (reg:CC CRIS_CC0_REGNUM))]) + (parallel + [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4))) + (clobber (reg:CC CRIS_CC0_REGNUM))])] { machine_mode zmode = INTVAL (operands[1]) <= 255 ? QImode : HImode; rtx op1 diff --git a/gcc/config/cris/predicates.md b/gcc/config/cris/predicates.md index 1fa22cda466..2b55c05931b 100644 --- a/gcc/config/cris/predicates.md +++ b/gcc/config/cris/predicates.md @@ -51,7 +51,7 @@ (define_predicate "cris_mem_op" (define_predicate "cris_load_multiple_op" (and (match_code "parallel") - (match_test "cris_movem_load_rest_p (op, 0)"))) + (match_test "cris_movem_load_rest_p (op)"))) (define_predicate "cris_store_multiple_op" (and (match_code "parallel") diff --git a/gcc/config/cris/sync.md b/gcc/config/cris/sync.md index d5bb11ddbcf..30b5ea075af 100644 --- a/gcc/config/cris/sync.md +++ b/gcc/config/cris/sync.md @@ -123,7 +123,8 @@ (define_insn "cris_atomic_fetch__1" (match_operand:BWD 2 "" ""))) (set (match_operand:BWD 0 "register_operand" "=&r") (match_dup 1)) - (clobber (match_scratch:SI 3 "=&r"))] + (clobber (match_scratch:SI 3 "=&r")) + (clobber (reg:CC CRIS_CC0_REGNUM))] "mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS" { /* Can't be too sure; better ICE if this happens. */ @@ -226,7 +227,8 @@ (define_insn "cris_atomic_compare_and_swap_1" [(match_dup 2) (match_dup 3) (match_operand:BWD 4 "register_operand" "r")] - CRIS_UNSPEC_ATOMIC_SWAP_MEM))] + CRIS_UNSPEC_ATOMIC_SWAP_MEM)) + (clobber (reg:CC CRIS_CC0_REGNUM))] "mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS" { if (cris_cpu_version == 10) From patchwork Wed Jan 22 06:12:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 1226995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-517974-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=axis.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=GOL/p67m; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 482Znq6y90z9sRR for ; Wed, 22 Jan 2020 17:12:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=jOrA0KvNH/i72YdS ZyyQs0kzb5ITQtWTAnXXCg/6sLpO9Xf5ngVjcaaoF7J69fyZfVeL4Rdtlo1KofHZ RhyOOv6ywycKe2IeBylAEP2DRyCDCcTSYyV5AEqdWkshU+C+3sqWWioCocVjSB/p PiDTAgq9v3UWNqEd9xgJ/5fhCWo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=Lc62d/h8f2t0We4PLc2E8P fcBW0=; b=GOL/p67mhb1IG+wQqzD5hwLL1/bEtyhRKTzh+7/Eiak+2SEH7zOByy ZVjO1f+JSjma9P7/1cfAWbuMaUNCru86SzxdJAg2pmRe8xt5AFwapvdsnegt9JMD w4TvI6+M00aV+INrzGe0upCvSxK5NizUWdQ9N47M9OxM2uDMdMdUs= Received: (qmail 75614 invoked by alias); 22 Jan 2020 06:12:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75592 invoked by uid 89); 22 Jan 2020 06:12:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: smtp2.axis.com Received: from smtp2.axis.com (HELO smtp2.axis.com) (195.60.68.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:12:37 +0000 IronPort-SDR: eKfxZDBYWrkU5xJiLdE5eHFoPKAUMWFd3ATooXSTzkXNzI9P2DrmgeKqqfd294Qcv5ookRLpwO 63fgwvqBrA8wNrRW6KW+z9NY9bJd0vT/wQ3E2p4cnSg9Lu+9k4mpIyF4uVWeGEVC9Ldhgv/Jhq R/EG4ulTzvtcPemkKmsE37E4Gi3oCUYJcoh4d8U/FIMH0gjNKf32bFKkrwlpidUsfvomGf5v9V VVqDKLdRBonEsc+RUFfYGCKQKJUD02un3VLy/yIrJVn0WZUpCgnbCMNywYekMG6exJ8rEZH1VB v6A= Date: Wed, 22 Jan 2020 07:12:35 +0100 Message-ID: <202001220612.00M6CZdf018324@ignucius.se.axis.com> From: Hans-Peter Nilsson To: Subject: [cris-decc0 9/9] testsuite: cris: xfail parts of gcc.target/cris/sync-2i.c, sync-2s.c MIME-Version: 1.0 X-IsSubscribed: yes PR target/93372 * gcc.target/cris/sync-2s.c, gcc.target/cris/sync-2i.c: XFAIL. Unfortunately, some assembly-code-matches have to be xfailed until the port is improved to use other than straight compare-insns. --- gcc/testsuite/gcc.target/cris/sync-2i.c | 5 +++-- gcc/testsuite/gcc.target/cris/sync-2s.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/cris/sync-2i.c b/gcc/testsuite/gcc.target/cris/sync-2i.c index e43aa5356f5..f69675cd9de 100644 --- a/gcc/testsuite/gcc.target/cris/sync-2i.c +++ b/gcc/testsuite/gcc.target/cris/sync-2i.c @@ -3,7 +3,8 @@ /* { dg-options "-O2 -Dop -Dtype=int" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ -/* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," } } */ -/* { dg-final { scan-assembler-not "\tand" } } */ +/* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */ +/* The xfails are due to pr93372 (regression-tracker for cris cc0 transition). */ #include "sync-1.c" diff --git a/gcc/testsuite/gcc.target/cris/sync-2s.c b/gcc/testsuite/gcc.target/cris/sync-2s.c index 9be7dc6bcb5..f31d3210dd8 100644 --- a/gcc/testsuite/gcc.target/cris/sync-2s.c +++ b/gcc/testsuite/gcc.target/cris/sync-2s.c @@ -3,7 +3,8 @@ /* { dg-options "-O2 -Dop -Dtype=short" } */ /* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */ /* { dg-final { scan-assembler "\tbreak 8" } } */ -/* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," } } */ -/* { dg-final { scan-assembler-not "\tand" } } */ +/* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */ +/* The xfails are due to pr93372 (regression-tracker for cris cc0 transition). */ #include "sync-1.c"