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Mon, 27 Nov 2017 15:20:29 +0000 From: Wilco Dijkstra To: GCC Patches CC: James Greenhalgh , nd Subject: [PATCH][AArch64] Fix ICE due to store_pair_lanes Date: Mon, 27 Nov 2017 15:20:29 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB6PR08MB2664; 6:+rDxT7lAPQHyavqJVJVD+0s8r/mfhXV+aM10zplWFdhIYoXQHbUVAK4Vu8p3gFY6eJax+2j0CHrgqyUplYizJ8tPeXNRtKKInPeSAaeKRAzDAAaAZtpQbEhORmzivjtsgVj+M071ay7OJcKoZ2qyl4HVv+e8CEyznMCaN0k1uKzH/E5CHWNxWLSN7eqwJqe7fUyl++1LbvovsQjzYN2JKQOzkprXpMGz1dxdCBSyDv/G1YGlcbN7auT24FzRvkXfTZn/CIaAuEAsw3F6KlU02yBjVoTPCPqZIG72t1RXT7u2ZEMa+5gLAatXQYR5foJH0F7aUYEohVZNwtVTzuSYf5YrdqVXioVAnYnUmDbBdkg=; 5:de+lirP5yQRsksiSWg7GhllvZStZ1pP9Ce9I6Tv6hmmC8zhb6iGZ/luF9jbCuZ6zmu8qrNF4B9jDDg2ceuXAmsQyLqGch0DqI6T4SlXUdVTxxNkcmgq+RhCA0n6vIJzLmR3BAcMeeP/qZFo+Am7nyRURYix6D3Xr5d0ei7+2FTk=; 24:prnqYnOiceO1qkxrgTRLtEszImMarZziO0oun6xjUsFBpxAXEkXH5ePNXbf1YU5ZpT3lK42jaYzHtre8lpURsD57UCPhoMn8xik6Pk0a2Rs=; 7:Yy9qFdkDJkzHI8WhY5qvr7DoCNjUoU6lj5UvueiIJXDwEYs7BzvKd5n4CvkoMhK3I61muVcJ6f19wiPWb6Hqyn3k+0zPyLwcA0kroXT8nQCwgwqk1PHvtPRkLZz65e3PC85Kj0FiXahUCYgBjG5dLPSKY2k5MwBb9U+qTtfx8h0/64/BKfuoBh4aRWeY2sVhn5AK4/oPea5zPust0CgsFcfC09gAxwAg3U/DBvXzYdPR+vDp7HXl+s1C0hQGd1V6 x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 7a93ce4b-a7d2-4f05-3afe-08d535aa6505 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(48565401081)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(5600026)(4604075)(2017052603199); SRVR:DB6PR08MB2664; x-ms-traffictypediagnostic: DB6PR08MB2664: nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040450)(2401047)(8121501046)(5005006)(3231022)(3002001)(93006095)(93001095)(10201501046)(6055026)(6041248)(20161123564025)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123560025)(20161123558100)(6072148)(201708071742011); SRVR:DB6PR08MB2664; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:DB6PR08MB2664; x-forefront-prvs: 0504F29D72 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(376002)(346002)(39860400002)(366004)(199003)(377424004)(189002)(54534003)(189998001)(81156014)(81166006)(5660300001)(8676002)(3660700001)(4326008)(54356999)(8936002)(2900100001)(3846002)(6116002)(102836003)(50986999)(7736002)(3280700002)(74316002)(305945005)(105586002)(5250100002)(55016002)(25786009)(6506006)(478600001)(4001150100001)(97736004)(72206003)(101416001)(6436002)(6916009)(99286004)(2906002)(54906003)(68736007)(53936002)(316002)(575784001)(86362001)(14454004)(7696005)(33656002)(9686003)(106356001)(66066001); DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR08MB2664; H:DB6PR0801MB2053.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a93ce4b-a7d2-4f05-3afe-08d535aa6505 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Nov 2017 15:20:29.7253 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR08MB2664 The recently added store_pair_lanes causes ICEs in output_operand. This is due to aarch64_classify_address treating it like a 128-bit STR rather than a STP. The valid immediate offsets don't fully overlap, causing it to return false. Eg. offset 264 is a valid 8-byte STP offset but not a valid 16-byte STR offset since it isn't a multiple of 16. The original instruction isn't passed in the printing code, so the context is unclear. The solution is to add a new operand formatting specifier which is used for LDP/STP instructions like this. This, like the Uml constraint that applies to store_pair_lanes, uses PARALLEL when calling aarch64_classify_address so that it knows it is an STP. Also add the 'z' specifier for future use by load/store pair instructions. Passes regress, OK for commit? ChangeLog: 2017-11-27 Wilco Dijkstra * config/aarch64/aarch64.c (aarch64_print_operand): Add new cases for printing LDP/STP memory addresses. (aarch64_print_address_internal): Renamed from aarch64_print_operand_address, added parameter, add Pmode check. (aarch64_print_ldpstp_address): New function for LDP/STP addresses. (aarch64_print_operand_address): Indirect to aarch64_print_address_internal. * config/aarch64/aarch64-simd.md (store_pair_lanes): Use new 'y' operand output specifier. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index cddd935d96589c52519334bd1b8c24e80ea475f3..b7dfbfaa1b00df113329e4b35397e2b6ce234786 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3047,8 +3047,8 @@ (define_insn "store_pair_lanes" (match_operand:VDC 2 "register_operand" "w, r")))] "TARGET_SIMD" "@ - stp\\t%d1, %d2, %0 - stp\\t%x1, %x2, %0" + stp\\t%d1, %d2, %y0 + stp\\t%x1, %x2, %y0" [(set_attr "type" "neon_stp, store_16")] ) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 60a8555b16296f07c68059bc54db803aeef0f369..e601f573bde4fae9a6e32af79ee987190895e088 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -150,6 +150,7 @@ static bool aarch64_builtin_support_vector_misalignment (machine_mode mode, bool is_packed); static machine_mode aarch64_simd_container_mode (scalar_mode mode, unsigned width); +static void aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx x); /* Major revision number of the ARM Architecture implemented by the target. */ unsigned aarch64_architecture_version; @@ -5448,7 +5449,11 @@ static const int aarch64_nzcv_codes[] = 'L': Output constant address specified by X with a relocation offset if appropriate. 'G': Prints address of X, specifying a PC relative - relocation mode if appropriate. */ + relocation mode if appropriate. + 'y': Output address of LDP or STP - this is used for + some LDP/STPs which don't use a PARALLEL in their + pattern (so the mode needs to be adjusted). + 'z': Output address of a typical LDP or STP. */ static void aarch64_print_operand (FILE *f, rtx x, int code) @@ -5650,8 +5655,6 @@ aarch64_print_operand (FILE *f, rtx x, int code) case MEM: output_address (GET_MODE (x), XEXP (x, 0)); - /* Check all memory references are Pmode - even with ILP32. */ - gcc_assert (GET_MODE (XEXP (x, 0)) == Pmode); break; case CONST: @@ -5815,18 +5818,48 @@ aarch64_print_operand (FILE *f, rtx x, int code) } break; + case 'y': + case 'z': + { + machine_mode mode = GET_MODE (x); + + if (GET_CODE (x) != MEM) + { + output_operand_lossage ("invalid operand for '%%%c'", code); + return; + } + + if (code == 'y') + { + /* LDP/STP which uses a single double-width memory operand. + Adjust the mode to appear like a typical LDP/STP. + Currently this is supported for 16-byte accesses only. */ + gcc_assert (GET_MODE_SIZE (mode) == 16); + mode = DFmode; + } + + aarch64_print_ldpstp_address (f, mode, XEXP (x, 0)); + } + break; + default: output_operand_lossage ("invalid operand prefix '%%%c'", code); return; } } +/* Print address 'x' of a memory access with mode 'mode'. + 'op' is the context required by aarch64_classify_address. It can either be + MEM for a normal memory access or PARALLEL for LDP/STP. */ static void -aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x) +aarch64_print_address_internal (FILE *f, machine_mode mode, rtx x, RTX_CODE op) { struct aarch64_address_info addr; - if (aarch64_classify_address (&addr, x, mode, MEM, true)) + /* Check all addresses are Pmode - including ILP32. */ + gcc_assert (GET_MODE (x) == Pmode); + + if (aarch64_classify_address (&addr, x, mode, op, true)) switch (addr.type) { case ADDRESS_REG_IMM: @@ -5909,6 +5942,20 @@ aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x) output_addr_const (f, x); } +/* Print address 'x' of a LDP/STP with mode 'mode'. */ +static void +aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx x) +{ + aarch64_print_address_internal (f, mode, x, PARALLEL); +} + +/* Print address 'x' of a memory access with mode 'mode'. */ +static void +aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x) +{ + aarch64_print_address_internal (f, mode, x, MEM); +} + bool aarch64_label_mentioned_p (rtx x) {