From patchwork Wed Jan 8 15:33:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1219760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47tCw501nsz9sRh for ; Thu, 9 Jan 2020 02:34:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47tCw43ftVzDqMG for ; Thu, 9 Jan 2020 02:34:12 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47tCvs2vgmzDqHj for ; Thu, 9 Jan 2020 02:34:00 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 008FMlpS130080 for ; Wed, 8 Jan 2020 10:33:56 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xdd60at8p-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 08 Jan 2020 10:33:56 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 8 Jan 2020 15:33:52 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 008FX3Bb50004476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 Jan 2020 15:33:03 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9BC1711C04C; Wed, 8 Jan 2020 15:33:50 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6F06B11C04A; Wed, 8 Jan 2020 15:33:50 +0000 (GMT) Received: from pic2.home (unknown [9.145.47.190]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 8 Jan 2020 15:33:50 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com, clombard@linux.ibm.com Date: Wed, 8 Jan 2020 16:33:50 +0100 X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20010815-0020-0000-0000-0000039EF4E6 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20010815-0021-0000-0000-000021F65514 Message-Id: <20200108153350.4724-1-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-08_04:2020-01-08, 2020-01-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxlogscore=903 priorityscore=1501 suspectscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001080128 Subject: [Skiboot] [PATCH v2] npu2-opencapi: don't fence on masked XSL errors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" An upcoming change in the initfile is going to modify the default action and fence behavior of some of the NPU FIR2 bits. We're already overriding the settings of most of those. The one exception is for bits 41 and 42, which are XSL errors impacting 2 links that we mask (instead we rely on the subsequent OTL error, which is per link). The new initfile will fence-on-error for bits 41 and 42. And even if the FIRs are masked, the NPU logic could fence the links, which is not what we want. So this patch makes sure we don't fence on the FIRs we want to ignore. It has no effect on existing firmware. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan --- Changelog: v2: add comment and use macro for the xsl bits we ignore (Andrew) hw/npu2-opencapi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index ed6650f4..07e81d23 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1649,7 +1649,7 @@ static int enable_interrupts(struct npu2 *p) * the systems, since we can just fence the brick and keep * the system alive. * - the exception to the above is 2 FIRs for XSL errors - * resulting of bad AFU behavior, for which we don't want to + * resulting from bad AFU behavior, for which we don't want to * checkstop but can't configure to send an error interrupt * either, as the XSL errors are reported on 2 links (the * XSL is shared between 2 links). Instead, we mask @@ -1661,7 +1661,8 @@ static int enable_interrupts(struct npu2 *p) */ xsl_fault = PPC_BIT(0) | PPC_BIT(1) | PPC_BIT(2) | PPC_BIT(3); xstop_override = 0x0FFFEFC00F91B000; - xsl_mask = PPC_BIT(41) | PPC_BIT(42); + xsl_mask = NPU2_CHECKSTOP_REG2_XSL_XLAT_REQ_WHILE_SPAP_INVALID | + NPU2_CHECKSTOP_REG2_XSL_INVALID_PEE; xscom_read(p->chip_id, p->xscom_base + NPU2_MISC_FIR2_MASK, ®); reg |= xsl_fault | xstop_override | xsl_mask; @@ -1677,10 +1678,16 @@ static int enable_interrupts(struct npu2 *p) * Make sure the brick is fenced on those errors. * Fencing is incompatible with freezing, but there's no * freeze defined for FIR2, so we don't have to worry about it + * + * For the 2 XSL bits we ignore, we need to make sure they + * don't fence the link, as the NPU logic could allow it even + * when masked. */ reg = npu2_scom_read(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, NPU2_MISC_DA_LEN_8B); reg |= xstop_override; + reg &= ~NPU2_CHECKSTOP_REG2_XSL_XLAT_REQ_WHILE_SPAP_INVALID; + reg &= ~NPU2_CHECKSTOP_REG2_XSL_INVALID_PEE; npu2_scom_write(p->chip_id, p->xscom_base, NPU2_MISC_FENCE_ENABLE2, NPU2_MISC_DA_LEN_8B, reg);