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Signed-off-by: Anand Moon --- Changes from previous v2: Fix the clk phase macro to support PHASE_180 drop the wrong CLK_CORE_PHASE_MASK macro. v1: use the mainline kernel tuning for clk tuning. Fixed the commmit messages. Patch v1: https://patchwork.ozlabs.org/patch/1201208/ Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) After these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) Test on Odroid N2 and Odroid C2 with eMMC and microSD cards --- arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++++++-------- drivers/mmc/meson_gx_mmc.c | 9 +++++---- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index e3a72c8b66..ee20c009e2 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -7,6 +7,7 @@ #define __SD_EMMC_H__ #include +#include #define SDIO_PORT_A 0 #define SDIO_PORT_B 1 @@ -19,14 +20,11 @@ #define CLK_MAX_DIV 63 #define CLK_SRC_24M (0 << 6) #define CLK_SRC_DIV2 (1 << 6) -#define CLK_CO_PHASE_000 (0 << 8) -#define CLK_CO_PHASE_090 (1 << 8) -#define CLK_CO_PHASE_180 (2 << 8) -#define CLK_CO_PHASE_270 (3 << 8) -#define CLK_TX_PHASE_000 (0 << 10) -#define CLK_TX_PHASE_090 (1 << 10) -#define CLK_TX_PHASE_180 (2 << 10) -#define CLK_TX_PHASE_270 (3 << 10) + +#define CLK_PHASE_180 2 +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12) + #define CLK_ALWAYS_ON BIT(24) #define MESON_SD_EMMC_CFG 0x44 diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 86c1a7164a..ad697d3a5e 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) clk_div = DIV_ROUND_UP(clk, mmc->clock); /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; - - /* 180 phase tx clock */ - meson_mmc_clk |= CLK_TX_PHASE_000; + meson_mmc_clk |= CLK_PHASE_180; + /* 000 phase rx clock */ + meson_mmc_clk |= CLK_RX_PHASE_MASK; + /* 000 phase tx clock */ + meson_mmc_clk |= CLK_TX_PHASE_MASK; /* clock settings */ meson_mmc_clk |= clk_src; From patchwork Thu Dec 26 11:33:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 1215471 X-Patchwork-Delegate: narmstrong@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong --- include/configs/meson64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 736081277d..50707a3197 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -8,7 +8,7 @@ #define __MESON64_CONFIG_H /* Generic Interrupt Controller Definitions */ -#if defined(CONFIG_MESON_AXG) +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) #define GICD_BASE 0xffc01000 #define GICC_BASE 0xffc02000 #else /* MESON GXL and GXBB */ From patchwork Thu Dec 26 11:33:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 1215472 X-Patchwork-Delegate: narmstrong@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Thu, 26 Dec 2019 03:34:09 -0800 (PST) Received: from localhost.localdomain ([45.112.0.38]) by smtp.gmail.com with ESMTPSA id e188sm37000247pfe.113.2019.12.26.03.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Dec 2019 03:34:08 -0800 (PST) From: Anand Moon To: Neil Armstrong , Peng Fan , Jerome Brunet , u-boot-amlogic@groups.io, u-boot@lists.denx.de Subject: [PATCHv3 3/3] board: amlogic: select PWRSEQ for all amlogic platform Date: Thu, 26 Dec 2019 11:33:53 +0000 Message-Id: <20191226113353.1757-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191226113353.1757-1-linux.amoon@gmail.com> References: <20191226113353.1757-1-linux.amoon@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc") introduce CONFIG_PWESEQ for power sequence for eMMC module on amlogic platform, so enable this to all amlogic boards. Signed-off-by: Anand Moon Reviewed-by: Neil Armstrong --- arch/arm/mach-meson/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index e29e4c0acc..513a33dae2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -8,6 +8,7 @@ config MESON64_COMMON select DM_SERIAL select SYSCON select REGMAP + select PWRSEQ select BOARD_LATE_INIT imply CMD_DM