From patchwork Thu Nov 28 13:56:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1202072 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rLc5SLqx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47NzhM4kbsz9sP6 for ; Fri, 29 Nov 2019 00:56:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 55CE8C22096; Thu, 28 Nov 2019 13:56:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8C7E2C21ECA; Thu, 28 Nov 2019 13:56:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3910EC21ECA; Thu, 28 Nov 2019 13:56:25 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id BACE8C21C29 for ; Thu, 28 Nov 2019 13:56:24 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id b11so11014963wmj.4 for ; Thu, 28 Nov 2019 05:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=SN9pB3z94RHxINt2PC8GaDi0SH6gmnXypADz4US4ZW0=; b=rLc5SLqxn3oIWX4blmReKszMXxiVhLtLGUwboDCIUZ5Pdw/8htUMX+u/YQx8KzCjn7 rg+VVUs/z81ySgGrMMMSWWUYd6w2+ydwIjPmnU5xBwi9TuVpp5jf+4Dkj59nP7L17aSa dbttgu4NG3Xu8G0xTdMBK+aMiR5ZmPAW4Ye5evE+ufa0dsHWZvoc9/O2LMiPqqWY12a8 cPhhVeWMxwJD2YD1CBFQ0VkrADM0SEgbFgXKK/Z5s6di58f2hxUUnhFUkP6HpHFzsKmS iLj6k1V5HXPbXe37OlRO5Ro2hmiDZQIdmziUUX6lON6lv7nzF40JX04dXWM/WPpXASHQ rnJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SN9pB3z94RHxINt2PC8GaDi0SH6gmnXypADz4US4ZW0=; b=heTDi5KV5seQUhhLWtN1BY8XeRLmQwDIYiIPOOeYEYQ/N19lAojyuW7upxo1FV5kHN zejD2EKOCKKjKvv1/MBMGfucqGdCAOTLlpZBOgi2A7BwUBY+FEV2vT+te0FurMHe9LH6 DRv4Reo2R8vY1Q7rDx+dz3u5o0dxWYbe6De5MeyQqqF/dvDpwujewfA5knft84cMGD+0 0v/N9gsmKQ2EJrYEsu/emppgX7RTHT3vpUSNklOt6/8sndZ45OAXgNBcTMaXJBGLGIjU AorEyAsBzt8GidvsNCkmJi57uTcdpMtsWICR6ZEx33GCl0hoik58Y92/YUanRXraGh5l nhuQ== X-Gm-Message-State: APjAAAURB2es4w5rFClwhNZ4Hyi/CIovbda8qYULinIJIUpJnwXuO/TA IBOfqT6jJMu/IdiqFfIoXcueI/UV9fo= X-Google-Smtp-Source: APXvYqyN8j5R8+dlLUvr0/EKFBt2eZMEQh22UyYva4qBkH9O/jDoIZW2BPk7npITQhxo1eg1IiSQzA== X-Received: by 2002:a1c:7419:: with SMTP id p25mr9987332wmc.111.1574949383929; Thu, 28 Nov 2019 05:56:23 -0800 (PST) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id m15sm23453702wrq.97.2019.11.28.05.56.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Nov 2019 05:56:23 -0800 (PST) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Thu, 28 Nov 2019 15:56:19 +0200 Message-Id: <20191128135621.12719-1-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 Cc: "NXP i.MX U-Boot Team" , Marcel Ziswiler , Igor Opaniuk , Max Krummenacher Subject: [U-Boot] [PATCH v2 1/3] mach-imx: bootaux: print stack pointer and reset vector X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk 1. Change information printed about loaded M4 binary, print the stack pointer and reset vector addressed. 2. Add sanity check for the address provided as param. Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx_bootaux.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 3d9422d5a2..ee786f7d06 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -20,6 +20,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) stack = *(u32 *)boot_private_data; pc = *(u32 *)(boot_private_data + 4); + printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", + stack, pc); + /* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); @@ -80,7 +83,8 @@ static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); - printf("## Starting auxiliary core at 0x%08lX ...\n", addr); + if (!addr) + return CMD_RET_FAILURE; ret = arch_auxiliary_core_up(0, addr); if (ret) From patchwork Thu Nov 28 13:56:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1202073 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cqB4OZcH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47Nzhv1hTgz9sP6 for ; Fri, 29 Nov 2019 00:57:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E2E5CC22063; Thu, 28 Nov 2019 13:56:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3F067C220C4; Thu, 28 Nov 2019 13:56:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 67A31C21ECA; Thu, 28 Nov 2019 13:56:26 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id 16D4FC21C29 for ; Thu, 28 Nov 2019 13:56:26 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id g206so11077647wme.1 for ; Thu, 28 Nov 2019 05:56:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6SVkeGGqZ44hwvlLnDNlfxLlcOTlgdFslSmmjFeG7zY=; b=cqB4OZcHvk2dDQg428HmqcDHPpc63pherbg7DF46MEnftS3P5deCQG4oOsL6gDshzT mVsUR9792Bxg6Co9obFIjEnNIejBuIATElaaE/HFQGaH/SSfD8L8ejPM4BCj7iKG4NIv yDQKjuQ+Q6l8vGjLyCCJ4x84LDkHfmnfhCiNs/+xRpK5eJM8g98KU0yeUsx5yJohC8dA eIXglOEe5Bsunu5zrVEzuWv3didMwAzjwOA6PRKf4q9NXBZrSSJJjkh3Mwyh08sdyV6o z2DXq1S7MwuVmrNKHaEp6uyZPB1WaHpihw//mk1WlipenYdKGXYgXF+UTvRnl/k9Y+h+ 7LuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6SVkeGGqZ44hwvlLnDNlfxLlcOTlgdFslSmmjFeG7zY=; b=VBuDj4yfSmEx0Mx1NCSGDdwrSSy/AzixCBz8n3b3sTjKS6oulvprGYXYnCaJKTGAf5 9HMw56fv0rfLtsrKiP7OCFg9uObiMrRTLXUOCklioiOk27yOQrV7Tov9b7BxrwJhMvGv gJjbla5ZqUmnlFVQ1jr98unZHZC+3sOdU8FDLNvsLhmqqkRKr6GyT0KjnknQlKTRwPXe tmWJsHLaQdYYmMhnr834Ub9xppRF+AVonfLmyO9E1VxquC1bQqGNU7ffqyh53thN19Qb t06o3L6dxtqTKHSOTrgXEcCggCqyqJh1OZPfIfnPDr793FfgzaAITWxI2+EkOtWh3dGf nPLQ== X-Gm-Message-State: APjAAAVYICVCBmyKEkS4foAb+4mx+9i5Mp1rjZwSLDJwDm/uQOevp0P3 FPZAX0A6o2RNEDqAGNIZWeqsR5yzusA= X-Google-Smtp-Source: APXvYqwVuCbJ0CLv+E9bNkGl7dLeC86qaahdGTyAQdDNwAaycbGr/6lReCu89ciOhkLw26+yd3aJLQ== X-Received: by 2002:a1c:3d87:: with SMTP id k129mr10215229wma.26.1574949385359; Thu, 28 Nov 2019 05:56:25 -0800 (PST) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id w12sm10510061wmi.17.2019.11.28.05.56.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Nov 2019 05:56:24 -0800 (PST) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Thu, 28 Nov 2019 15:56:20 +0200 Message-Id: <20191128135621.12719-2-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191128135621.12719-1-igor.opaniuk@gmail.com> References: <20191128135621.12719-1-igor.opaniuk@gmail.com> Cc: "NXP i.MX U-Boot Team" , Marcel Ziswiler , Igor Opaniuk , Max Krummenacher Subject: [U-Boot] [PATCH v2 2/3] mach-imx: bootaux: add dcache flushing before enabling M4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk This patch fixes the issue with broken bootaux command, when M4 binary is loaded and data cache isn't flushed before M4 core is enabled. Reproducing: > tftpboot ${loadaddr} ${board_name}/hello_world.bin > cp.b ${loadaddr} 0x7F8000 $filesize > bootaux 0x7F8000 Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx_bootaux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index ee786f7d06..c750cee60c 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -27,6 +27,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); + flush_dcache_all(); + /* Enable M4 */ #ifdef CONFIG_IMX8M call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0); From patchwork Thu Nov 28 13:56:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1202074 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VkfOEmZM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47NzjF0scxz9sPK for ; Fri, 29 Nov 2019 00:57:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B01D7C21C29; Thu, 28 Nov 2019 13:56:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CF5DEC220E6; Thu, 28 Nov 2019 13:56:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E6649C22068; Thu, 28 Nov 2019 13:56:28 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id 9273AC21ED5 for ; Thu, 28 Nov 2019 13:56:27 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id a15so31236891wrf.9 for ; Thu, 28 Nov 2019 05:56:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RtCtkaCRzpAnK564UZ2YqIwgrJz0tUXfrv7i2DIvVFQ=; b=VkfOEmZMFq+bukESIfA2rXhBtDpkNzxezQPnhCYFsrm1YMUsceHtWg29xfcr3reyza uGQbQMiCIkiZEuzyfsT4VfiB/C0lIRG91u4qTexQA6IY3ffeNDwNW7avBpKO6AEKyQjq RBnWAnJyNxl+THfscSvYCmf7LG9mIkgFQm2BubQA1CKkVYxBvUeo4jds2cg4PypA8EVN 5w+v/LXaQhYBUS/uZh6CKRivhrNz9M6Xg7zDioUheDhSYGezsQ6q4AjYA+YPPHUJWBbK YOIwX8sIs40V944StEcQc/LLHmXORU7NIhVX5bAEJ7QJT9xiIbgamj9bz8kndJUQxd11 D9uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RtCtkaCRzpAnK564UZ2YqIwgrJz0tUXfrv7i2DIvVFQ=; b=PxIsKpNyoG9LczT0npBvPkwPrKTHSNUOMOqMDqxqWMIU/OuYAXMsvHNRi+fnjuW6Im B/8y4GuyJJAUgTQVsff8OREZV3kKUFbSmikLIxt9S6mLhTDskPa6/d4mwZn5frCS1bEX u1UszXWUk36vNGOGtJuVJZtMuD/5pYxEIt9BKaopzw4ntvwY47iAJzAVWC2WaXmCb38d L10Rri/GGh8DqIeK380H9jeizNO119VFARRGLDD8VLgdWeYqbftYt712RVqP9sce/4dx +BeKA0SleE8QtNj5vYO8VKMvu1K6f3p7uEYj2uPWHeGqgaIWJ8ueRrKfuCXJR3VAxZgB NmxQ== X-Gm-Message-State: APjAAAUih5ec0+XDw3cu4do3byoLBxQQI7z2hmbJLwu5iiw7eJOIfe3L hpu2L+NGsaEPCd8bX9etmTcdwtgNEWg= X-Google-Smtp-Source: APXvYqzZTbt7XEFfb2tjIVqo0HC12kBGsF4h6mqpk3wOHGiBABRfDxP/IdBeUcdqE0Oc4QX+mejp9w== X-Received: by 2002:adf:c50a:: with SMTP id q10mr8565316wrf.374.1574949386839; Thu, 28 Nov 2019 05:56:26 -0800 (PST) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id w11sm25171347wra.83.2019.11.28.05.56.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Nov 2019 05:56:26 -0800 (PST) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Thu, 28 Nov 2019 15:56:21 +0200 Message-Id: <20191128135621.12719-3-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191128135621.12719-1-igor.opaniuk@gmail.com> References: <20191128135621.12719-1-igor.opaniuk@gmail.com> Cc: "NXP i.MX U-Boot Team" , Stefan Agner , Marcel Ziswiler , Igor Opaniuk , Otavio Salvador , Max Krummenacher Subject: [U-Boot] [PATCH v2 3/3] mach-imx: bootaux: elf firmware support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c Signed-off-by: Igor Opaniuk Signed-off-by: Stefan Agner Reviewed-by: Oleksandr Suvorov --- arch/arm/include/asm/mach-imx/sys_proto.h | 7 ++ arch/arm/mach-imx/imx_bootaux.c | 84 +++++++++++++++++++++-- arch/arm/mach-imx/mx7/soc.c | 28 ++++++++ 3 files changed, 115 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 1e627c8fc3..ed5d9a1667 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -104,6 +104,13 @@ void gpr_init(void); #endif /* CONFIG_MX6 */ +/* address translation table */ +struct rproc_att { + u32 da; /* device address (From Cortex M4 view) */ + u32 sa; /* system bus address */ + u32 size; /* size of reg range */ +}; + u32 get_nr_cpus(void); u32 get_cpu_rev(void); u32 get_cpu_speed_grade_hz(void); diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index c750cee60c..871169e771 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -7,18 +7,94 @@ #include #include #include +#include #include #include -int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader, assumes the image is valid, returns the + * entry point address. + */ +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} + +int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; - if (!boot_private_data) + if (!addr) return -EINVAL; - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); + if (valid_elf_image(addr)) { + stack = 0x0; + pc = load_elf_image_phdr(addr); + if (!pc) + return CMD_RET_FAILURE; + + } else { + /* + * Assume binary file with vector table at the beginning. + * Cortex-M4 vector tables start with the stack pointer (SP) + * and reset vector (initial PC). + */ + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + } printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", stack, pc); diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 35160f4b37..4aafeed188 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -193,6 +193,34 @@ static void init_cpu_basic(void) #endif } +#ifdef CONFIG_IMX_BOOTAUX +/* + * Table of mappings of physical mem regions in both + * Cortex-A7 and Cortex-M4 address spaces. + * + * For additional details check sections 2.1.2 and 2.1.3 in + * i.MX7Dual Applications Processor Reference Manual + * + */ +const struct rproc_att hostmap[] = { + /* aux core , host core, size */ + { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */ + { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */ + { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */ + { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */ + { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */ + { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ + { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ + { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { /* sentinel */ } +}; +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* enable all periherial can be accessed in nosec mode */ static void init_csu(void)