From patchwork Mon Nov 18 11:00:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="axyw3Cad"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmG50HDQz9sPW for ; Mon, 18 Nov 2019 22:00:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726686AbfKRLAn (ORCPT ); Mon, 18 Nov 2019 06:00:43 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36343 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726563AbfKRLAm (ORCPT ); Mon, 18 Nov 2019 06:00:42 -0500 Received: by mail-wr1-f65.google.com with SMTP id r10so18902478wrx.3; Mon, 18 Nov 2019 03:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/r/rbSHnQ681j6w5Fd1xT+tCG0CKj+LRyHPCBVvmrlM=; b=axyw3CadnYKZZ/gPWsjDxs4XIRVAbwQA2BIPtCkbInP+P5tLbFpCU451G7RuR37Z9l ngNfWM+B2QlQT6ZFR4BjTiP5kgxgdwN3Fy2FBXubHDp3BVEgFsTV9E2yFVLgS3Dy5tY2 mtozqqdqgWFfS7FhuwMK5zdEC7a13CXKFPr7KmRQ861zPsj4CmXlqCyT3+6sEkGiDGuM ZLS9Qcw35kxi4bErUZqf9Rl8lHF9jcdCQcO/mPP/rMfVUq3cQ/OhJ6GrlWCsqC0TQx5e +4THiAdRNt35MiDPE2SrPRjTHjJgbwI5HHkIEb9vrQ94w/xIk7hpEwWe5eObrAXytAD/ PNRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/r/rbSHnQ681j6w5Fd1xT+tCG0CKj+LRyHPCBVvmrlM=; b=RbKH0MHrUsDpkvEz0/yl1AX/8sPXMU2hAYoOK7pBu/Rs9xUr4Yh9XrNZbjxl9HmksN VV99EbN7myQ4ZN8sivMRNrQYdoOckbpGkCw3WPH/wBJ3y11ZLvQbrCp49hkYMquwjudG m09Dzd8EX+LhFpArlstknZBpFREue96TOI5h+2/x9Q6RTSAlUjwk1BeHtpPgDOSZK6+F +RdlaUPY/LHUOCoWbHp9Nh366rgFm0sjy9TgtPojnaFf0+rJGsdu/w6K4oydleLnoK2i wFuYEbE2wvt8PzSyd+7TYVzhcj02mts29MMvtxiZFsnV2BpATQJ6dkDUuV1L3Pyc9Vc6 W/JA== X-Gm-Message-State: APjAAAXvGG4HIBrqGnYoQv7lsA8wJUmh/LmLtZK+ndPSb8ZHviBd3m7k Z3mvf9l/2Eu/uKP0b1qHTjM= X-Google-Smtp-Source: APXvYqxEFAX5cEn1tc0TWYXeLTvWC45ER2bxKy0vHBbmoO46RYGcBJIFgShG/Z/M5rcmO7fKz2Repg== X-Received: by 2002:adf:f005:: with SMTP id j5mr28478666wro.295.1574074840489; Mon, 18 Nov 2019 03:00:40 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:40 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , Rob Herring , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 1/8] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Mon, 18 Nov 2019 12:00:27 +0100 Message-Id: <20191118110034.19444-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Reviewed-by: Rob Herring Signed-off-by: Clément Péron --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..1bae446febbb 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,51 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + items: + - description: Module Clock + - description: Bus Clock + + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clock-names: true + + resets: maxItems: 1 + if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + + else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +92,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Mon Nov 18 11:00:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rvyNyMqc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmGn6KsRz9sPW for ; Mon, 18 Nov 2019 22:01:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727139AbfKRLBR (ORCPT ); Mon, 18 Nov 2019 06:01:17 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:38352 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726822AbfKRLAo (ORCPT ); Mon, 18 Nov 2019 06:00:44 -0500 Received: by mail-wr1-f65.google.com with SMTP id i12so18897809wro.5; Mon, 18 Nov 2019 03:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=rvyNyMqc1D+jPRurNAmZ1sgzsaQbzJ6wBBEgsy5D62mpDk+XyXG1TxGfzXo+McCZcK +NcIA9co9Xqvh9g01D673oDyHFpJH79a0edKgNXuqb3wExDS+/BUX2arhQ4IKS9sm3oI QYR1xDwpYxJ5EabIT7IGZibDN1zGNcEi9R/Jc+bFsSuSRFlA1ZCVpXFVOyNLAjou90JX JJlXlJd3biqLgGfo6CzTzaXpw3qZfAm7TlyjVglBdd93dZaTnCIPQ9hljWAM3YUbmHFH 2MTNDC/4JxaDfN0yA/p2GYPjIrktq56S2KV7+CsxGYI0tPHdgYqFM2GNmSZ487AkFbAg fK4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=WxlJBPi60IvpPZNmUzLnAx+ig/ab/DxjMzmEVjZgZ9y5SCakgildK+mCk9t2ecItLU /3mYoZNQQLY4pCI+AYDg0EEKsnWxCNUVMgsWKeE/v/AVSnhJmy+bYmVXdzlGP/Q/LdEB TsB1ENEcqlcnkMpzQ7wcFp1TRiXhGg8xLrWQhKbdw02sSTqYCiyRDAuON9A5x0vk1ysS TaRw4LSS3L4o9NWSAqMPcnkSMvkynR4NXNiRIZ/+wUnBZYEvFnP6mXNx/GQdRXYV0hlh fW/YTnJeH+XgUvxDBlIsodYV46w5fF3g0bXr+C/G15cuIhvwmhAciXMuGu1h32wTRy5X MO/g== X-Gm-Message-State: APjAAAWdzQ7MtPQhfh3nWMyMHSHciC6MSVgFG0/f3oCNLDUvcmtR7yMF DKvjL0dtsp9yGTwaKggMjbJqhLe4MGIaeA== X-Google-Smtp-Source: APXvYqx75gEPB0FteaYS2yHGOP2I2/utQyuuZOScnt6LFmIebZFYgGAW1ROUtA2x2X9B7RfWT43kyg== X-Received: by 2002:a5d:558e:: with SMTP id i14mr28728525wrv.140.1574074841156; Mon, 18 Nov 2019 03:00:41 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:40 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 2/8] pwm: sun4i: Add an optional probe for reset line Date: Mon, 18 Nov 2019 12:00:28 +0100 Message-Id: <20191118110034.19444-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Reviewed-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 581d23287333..c17935805690 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get reset failed %pe\n", + pwm->rst); + return PTR_ERR(pwm->rst); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Mon Nov 18 11:00:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QFDuz+IW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmG657Pnz9sPW for ; Mon, 18 Nov 2019 22:00:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726911AbfKRLAp (ORCPT ); Mon, 18 Nov 2019 06:00:45 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36355 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726562AbfKRLAo (ORCPT ); Mon, 18 Nov 2019 06:00:44 -0500 Received: by mail-wr1-f67.google.com with SMTP id r10so18902619wrx.3; Mon, 18 Nov 2019 03:00:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+uPwPfx0oQerpYTv3rMNbZ1we4qpdrwsuG2bGFowiTE=; b=QFDuz+IW+HnUgegZRGK3iKMMqIgXz0PnyggLLboNAo23LCWY2Gj5hyXBR8JHU8sDEW 2nFd8+IW1Nzpj3BTX/Ttt6LotZtoOk7OE4hTSRRql/uwPopINBAR0Tprett8ddJKHgBh 3vHJuPOfA60KLKupuWrAF4vdz5IxsfObywmNmB/3ySzo/X0LP3uLOzkowkzFN32lsHlR REVQ60uYcjw5vMMLLNNKA0ylvY5KVclB/BVwP7Cy1QT+kzWy6ZVtQ5JRHn0Ejlq0DYkw ASV1ziUmM3K+C7WVSn+VR1BbebvHWGO6sPbiG+O1OHWtjqLpRtt6spd1TTCBAALQ3Ai9 qufQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+uPwPfx0oQerpYTv3rMNbZ1we4qpdrwsuG2bGFowiTE=; b=DSdCtbvaDQdpi3UXaK89QKkjoKU5jEgE+l5CiudaEeAbGka+6fEp1GNWtY9sM+JPm0 5TWJOCsQ/uCEjaPGAsWryucSZuDRXFprWx7e4DQuAYMkksPL/MFKmJSpsfY0EcYkTSsq 9kDVB6JNyh4pV8OFwWAtinNsiSa9UXHwaMxVgqkpoOgNzguzWZRudZWWFovnk8Y5nO+s lq58VRX96blDbKRHMS1M3uWcaKmUiBNdEVnPYeahNg0zEs7Mgrv1sa6+JEH8CByUOcWX 9dR8ALSf97qKteUyfgUVt/0JJ/5MaWZPbJAa1tHBDl+ufhXDrIdPOX6XF+8/RizKW2Ur CdMw== X-Gm-Message-State: APjAAAXRsn6Y8w21lJSHZZ36oXfmUVW/Zc+Rx5lvepN7tMzdUwZQcn50 sZCJOrNjR3JVePp62nIx2n4= X-Google-Smtp-Source: APXvYqyaEaWN5edD71vuH2Nr7q1utFJujX5hmEgB41Q5ofpd4MyhhKPr56RU/npbmympYwagPqL5hA== X-Received: by 2002:adf:f20d:: with SMTP id p13mr27767215wro.325.1574074841802; Mon, 18 Nov 2019 03:00:41 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:41 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 3/8] pwm: sun4i: Prefer "mod" clock to unnamed Date: Mon, 18 Nov 2019 12:00:29 +0100 Message-Id: <20191118110034.19444-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org New device tree bindings called the source clock of the module "mod" when several clocks are defined. Try to get a clock called "mod" if nothing is found try to get an unnamed clock. Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index c17935805690..6d97fef4ed43 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->base)) return PTR_ERR(pwm->base); - pwm->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) + /* + * All hardware variants need a source clock that is divided and + * then feeds the counter that defines the output wave form. In the + * device tree this clock is either unnamed or called "mod". + * Some variants (e.g. H6) need another clock to access the + * hardware registers; this is called "bus". + * So we request "mod" first (and ignore the corner case that a + * parent provides a "mod" clock while the right one would be the + * unnamed one of the PWM device) and if this is not found we fall + * back to the first clock of the PWM. + */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get mod clock failed %pe\n", + pwm->clk); return PTR_ERR(pwm->clk); + } + + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get unnamed clock failed %pe\n", + pwm->clk); + return PTR_ERR(pwm->clk); + } + } pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { From patchwork Mon Nov 18 11:00:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AxdIa2+7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmGg3KSDz9sRf for ; Mon, 18 Nov 2019 22:01:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727116AbfKRLBL (ORCPT ); Mon, 18 Nov 2019 06:01:11 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:34143 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726855AbfKRLAp (ORCPT ); Mon, 18 Nov 2019 06:00:45 -0500 Received: by mail-wr1-f65.google.com with SMTP id e6so18921862wrw.1; Mon, 18 Nov 2019 03:00:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jsifq8PTX0er46e43pUZkmCyPNqnaTwpRAxn8YySges=; b=AxdIa2+7XYravskLqghTUZppTTZptO8qgtCJ8FPixAp6+EU5OJstpE/ZAIfKD8JE/b jzg/hdoKslHHCtuW/rCVmM6KvSWifU2sfbvRHsgBkUJDSu4if41mbXAjD5KQidpE1Mvj Aa8ccEJos7u0q49ldpl3NK8RMDOJinitwm3d2U+xFQJK+m3bnQZw0vQLkaHs8RKospPy UK15nVIlImEynkAN/Ed2fsDxDcwXFoQ7RzN9LB8cQlzkBd8NCSszqCN6pnG8aTLXOInT RGTqi5s7R2srOuPNE52k+qro/45QT4GuU3ZUySevKB18V+NdHaR6h8G77hcA7g32sZ5/ q4jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jsifq8PTX0er46e43pUZkmCyPNqnaTwpRAxn8YySges=; b=GrXp3nZR1d87VRdywkIJiJ0tW2V5kJmJ2rKg+/YZZdXsqBuTm3MfoUNx61JmmDudbQ zIP1kmKkRytQ85owN4QgrN676Uv0Ja/+aM9kW69Wgk8uSu2NyTYcSvLWhcSXLrbJV5M7 w3h5YtXgQy2d9MX76oJ+wiuZt4Yyfus2C/4DFjzXTXM9ZHp09kPQjSHCWvs3QgecUrc8 WwPW3SGqtbrDtBZk8Iv7pBfVTLTwDH90xUB+Eih27o17iAKTQcvxXhncEaippwOCm5MF mwcjpTGhBWRKgkpWWock3R7alYwWF7ZHsx8ecqUy0dRC7ITjaQaIMgZhoGTW5kXcWjOb iC3Q== X-Gm-Message-State: APjAAAUzcWElVZ8xCavaC+Us5qmMebCVO5Gj3lfo5H1N7HY9t0V8izN2 UihUKRFBeJoYNXp0YkerECw= X-Google-Smtp-Source: APXvYqwUHWq7ibM4Sw/PPC1hM1P4uE5Ho0apvC2XIkz8SHsKzaAKYdlTw3hx8tCnK33bDFYGGvWLcw== X-Received: by 2002:a05:6000:150:: with SMTP id r16mr28384394wrx.313.1574074842479; Mon, 18 Nov 2019 03:00:42 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:42 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 4/8] pwm: sun4i: Add an optional probe for bus clock Date: Mon, 18 Nov 2019 12:00:30 +0100 Message-Id: <20191118110034.19444-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6d97fef4ed43..ce83d479ba0e 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) } } + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get bus clock failed %pe\n", + pwm->bus_clk); + return PTR_ERR(pwm->bus_clk); + } + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) @@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* + * We're keeping the bus clock on for the sake of simplicity. + * Actually it only needs to be on for hardware register accesses. + */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -426,6 +445,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -440,6 +461,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Mon Nov 18 11:00:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BKtOOwd5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmG90ss7z9sRK for ; Mon, 18 Nov 2019 22:00:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726976AbfKRLAr (ORCPT ); Mon, 18 Nov 2019 06:00:47 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:56204 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726890AbfKRLAq (ORCPT ); Mon, 18 Nov 2019 06:00:46 -0500 Received: by mail-wm1-f65.google.com with SMTP id b11so16865381wmb.5; Mon, 18 Nov 2019 03:00:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ftjDb5WxJHIC5enFSHC7KF6MbGREBXU1Fw5+H0zCqjU=; b=BKtOOwd5PFHpTXzaPGzsZSf6SzBqmft5c18vACqhNtn/BHhEADlsLGxJ5N56hvL6p9 bLaRpRRXGy5LxDdCMU3xmnrZI8jkxT7OPlj4ilSE8E1bowv+CIccJnPu23ZNpURHsyBC Vt4LvCjtviRaKcoJ/eRHNwC8DMQyH9pRWQU+pPszStqnXdGHnftDnmD5bbNQ80ia6T/a 1DZgijT0XVq9ES9JxoVRBA/sjv4iMtCFHXp9U78AIch3gOdGa7mAZPCqSP7WyZf25vua 9P9VxXsY3TepgNEraX9yEtAFcSdwjkKUucl6PX/fP/TywTgKKR0/2kqrwI4NsOq2dq/s vLTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ftjDb5WxJHIC5enFSHC7KF6MbGREBXU1Fw5+H0zCqjU=; b=S8j1OEJJDSQ+mKXmfW74H62z+hKB77rL+QgUDlK94pVDNL2Q1PlZ9gjLx+sV/xtJex 6aZ+o8WYquZ2bY9t36y3eeT197Gk3G57uadgb8lmhEqO8mL0DndQeR/3BKaRXr6mBg3f LfhGN5EZLJNUwWqdgNVlRDX8pcrpvhfxGDY536Oph9Rnvi6D3M3dwmEkCu1lm+KBPtta mGKmAOelnZDrWsYRVbQ15401jRFwJreoS7O4uugvgAQt7CEu45u6bNj/ZkY7WQk62/8A 5LX0DI9UT3mvaGDv3/CmqgAbSngN/ia3M64hvV7gryzq6PFMRSRxAFAlqXmqWEZo2QmY akXA== X-Gm-Message-State: APjAAAXv4Tbad1+knM+AzLWnAlwp6LEdpEtsaygTm9zUt29pxg7xWRfN Vww5zWW2iOrRjiftFmibzzU= X-Google-Smtp-Source: APXvYqzDePjFRVwVWistNfGwK2aOzOLZlJczcRyWzcuhDl+0BxWaExUGTIEwquoySANeymwTWiUPPw== X-Received: by 2002:a1c:9c54:: with SMTP id f81mr28729101wme.89.1574074843262; Mon, 18 Nov 2019 03:00:43 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:42 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 5/8] pwm: sun4i: Add support to output source clock directly Date: Mon, 18 Nov 2019 12:00:31 +0100 Message-Id: <20191118110034.19444-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++------------- 1 file changed, 64 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index ce83d479ba0e..a1d8851b18f0 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, const struct pwm_state *state, - u32 *dty, u32 *prd, unsigned int *prsclr) + u32 *dty, u32 *prd, unsigned int *prsclr, + bool *bypass) { u64 clk_rate, div = 0; unsigned int pval, prescaler = 0; clk_rate = clk_get_rate(sun4i_pwm->clk); + *bypass = state->enabled && + (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + + /* Skip calculation of other parameters if we bypass them */ + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) + return 0; + if (sun4i_pwm->data->has_prescaler_bypass) { /* First, test without any prescaler when available */ prescaler = PWM_PRESCAL_MASK; @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, period, duty, val; int ret; - unsigned int delay_us; + unsigned int delay_us, prescaler; unsigned long now; + bool bypass; pwm_get_state(pwm, &cstate); @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - if ((cstate.period != state->period) || - (cstate.duty_cycle != state->duty_cycle)) { - u32 period, duty, val; - unsigned int prescaler; + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, + &bypass); + if (ret) { + dev_err(chip->dev, "period exceeds the maximum value\n"); + spin_unlock(&sun4i_pwm->ctrl_lock); + if (!cstate.enabled) + clk_disable_unprepare(sun4i_pwm->clk); + return ret; + } - ret = sun4i_pwm_calculate(sun4i_pwm, state, - &duty, &period, &prescaler); - if (ret) { - dev_err(chip->dev, "period exceeds the maximum value\n"); - spin_unlock(&sun4i_pwm->ctrl_lock); - if (!cstate.enabled) - clk_disable_unprepare(sun4i_pwm->clk); - return ret; + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) { + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + /* We can skip apply of other parameters */ + goto bypass_mode; + } else { + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); } + } - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { - /* Prescaler changed, the clock has to be gated */ - ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - - ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); - ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } + if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { + /* Prescaler changed, the clock has to be gated */ + ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - val = (duty & PWM_DTY_MASK) | PWM_PRD(period); - sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); - sun4i_pwm->next_period[pwm->hwpwm] = jiffies + - usecs_to_jiffies(cstate.period / 1000 + 1); - sun4i_pwm->needs_delay[pwm->hwpwm] = true; + ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); + ctrl |= BIT_CH(prescaler, pwm->hwpwm); } + val = (duty & PWM_DTY_MASK) | PWM_PRD(period); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); + sun4i_pwm->next_period[pwm->hwpwm] = jiffies + + usecs_to_jiffies(cstate.period / 1000 + 1); + sun4i_pwm->needs_delay[pwm->hwpwm] = true; + if (state->polarity != PWM_POLARITY_NORMAL) ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); else ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -264,6 +299,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Mon Nov 18 11:00:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lqFiFGfE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmGb5bwRz9sRK for ; Mon, 18 Nov 2019 22:01:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726962AbfKRLAq (ORCPT ); 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[82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:43 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 6/8] pwm: sun4i: Add support for H6 PWM Date: Mon, 18 Nov 2019 12:00:32 +0100 Message-Id: <20191118110034.19444-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Acked-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index a1d8851b18f0..640f6349e36f 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -358,6 +358,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -374,6 +380,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Mon Nov 18 11:00:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Wr086HtE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmGZ4HDyz9sRf for ; Mon, 18 Nov 2019 22:01:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727016AbfKRLBF (ORCPT ); Mon, 18 Nov 2019 06:01:05 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40091 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726927AbfKRLAr (ORCPT ); Mon, 18 Nov 2019 06:00:47 -0500 Received: by mail-wm1-f66.google.com with SMTP id f3so18227816wmc.5; Mon, 18 Nov 2019 03:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=Wr086HtETOZcOmc4iZyEckCSVl84N673n+TidoSKWx/tsWUykTFSEw0lVTE7A7/cHq kA7CelwmTaEk9vXiH9I1UTDGMbeEpKPDtbkQoE6O6NZRUvxhWYWhqBOclnS3PO9m07eB zx8MqwgyY4bVZQu56j63cjjRkWfFs5kT8tb7UDkSRRZvSVmKcF5l8cCzOEs6uSXoVg11 iqD6LL1eN8v2B8nwluCKWahNwl4Ub1aQ243SZJsjjw7ABqgyOELMD5fpBUcHNYD0UR8r cXwfS9aqlqMINWywAgBUHeQAvgYHEgqt8YeMXd6eYuRiZFB7IjVtuzawScSxmdHCAtKw xQgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=CtPdsPTAeTdTKOKEMFr/UtRlsPKWgVT1ohIApWI4nZFCQrME89b58YEOTb49KqukQF jNu5Sa0cPP4Z/Qh70rwNx0rAFQ7bnOxRji9pLRk+9N52/88HhRT+ppzwnXaD2/QtHdY4 jwr1DkQdR/lnLnO5TWmuhIq2VJHlJ3dzBfddWA0AI2GzTeiQJCvZk//erBJU/SxMvo/k ZKrikg5bxbIZgtNxhNj4q4Ula5SWI9cFQNhIq5qMd0FN/NXQr4787OHSwLrFoH92ZSNu TNOjL5jpfqACxC/IvhDtGHUtb0QQwTIGBhUhMh5bE6IOxd/xEz5AwS7I2dlDkyhrojIL UmrA== X-Gm-Message-State: APjAAAUPnqJe7bOL79Krs+wIjfBQDcKBS+vf+hoP6yXrJd2LBk0T9+Tg bJUVtjGQV0dQwqveleigS8s= X-Google-Smtp-Source: APXvYqwJPN1Zn8wdFBpSu4h4FnkR4VySti7UEN2KiwGGp1NrFrPsGy/qRfs1nyJMt6qg4QbJ2U7YXg== X-Received: by 2002:a1c:1fcc:: with SMTP id f195mr28211273wmf.137.1574074844581; Mon, 18 Nov 2019 03:00:44 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:44 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 7/8] arm64: dts: allwinner: h6: Add PWM node Date: Mon, 18 Nov 2019 12:00:33 +0100 Message-Id: <20191118110034.19444-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 29824081b43b..6d4bde488f15 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -245,6 +245,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Mon Nov 18 11:00:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196669 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oHTBVWCz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GmGS3dPDz9sRM for ; Mon, 18 Nov 2019 22:01:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbfKRLAr (ORCPT ); Mon, 18 Nov 2019 06:00:47 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:33921 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726951AbfKRLAr (ORCPT ); Mon, 18 Nov 2019 06:00:47 -0500 Received: by mail-wm1-f68.google.com with SMTP id j18so15645286wmk.1; Mon, 18 Nov 2019 03:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=oHTBVWCzKbEEX8ADBqtS0nC4h3CNYn1XfnE4upjcrU9jd9WOlvNbtYTmD+5cn8y61a AtXhSXsQe2jqj9xCOUPD47GxZa2WNeUOQP0F/BexCFOxpgS0Cibok9YMUFQCHHSMbJru x54QTghn8OTid42B41o6KQZkwK9dqeYDz3fYthk6Bt5dqfpcZ5sW/n3J51nJd1mZbLha yshq5NVf/JpBrh8AaZV1sImpXOO7tj68GC2YnSc88Hi4ceBwsC0Na5L8yBAWQvEnswbn 04sLIfQBYErlUi+bgzg+zfbsE0TSsFdFxMynRVwZlGfBPu7MBD8X5XDO1Grehx2HWHbG jSlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=Sm88K1hQKn8ONaLAzHqPG+01ZvS2rQKSrZMPfcZfkIEIj2h6qsXj2nHnbFQWIKGLFS +POMW7e2WNanaR/5si8ut5TB1BKZRWr7Z/M8xlzoIrhdXTIY/qxcrRkJhErD6GIhYgH0 6m3rysfv/m7UedBaEky5IND7Vai1rBexDJRxqTA0FXiYkLdNu+202w0xRE5mL3DtHKi+ cY/F5GlRglYXVFQFQVTZFD87CyAgF3XUMyrr3SxQn9UtSUxPR13kydaXK0cN6SK97FZ2 5qiOpmb4nVlUvN7fl0js/7X9tM+9Jgw4VltVNYWxE1YxpSRAlbcBG7qEQYJgReDmaiB0 X/5A== X-Gm-Message-State: APjAAAVUdu77Oncear8Gq74+nVvt/5NiQKMCzodU3Bad82mrlBNTLHx/ cNpGTRdlxb62/CNaLMFmdC8= X-Google-Smtp-Source: APXvYqylsRp4Nj3fkxX+SPKT7MsCCNLSmcFaIEujk7WAbZj4htC5DEVRLFeS7TNDCdftzyqTPoROuw== X-Received: by 2002:a1c:7c06:: with SMTP id x6mr30073630wmc.34.1574074845202; Mon, 18 Nov 2019 03:00:45 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id f67sm19873313wme.16.2019.11.18.03.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 03:00:44 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v6 8/8] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Mon, 18 Nov 2019 12:00:34 +0100 Message-Id: <20191118110034.19444-9-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118110034.19444-1-peron.clem@gmail.com> References: <20191118110034.19444-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index f335f7482a73..cf684bc7374d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -136,6 +136,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";