From patchwork Mon Nov 18 10:59:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196660 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="EJ2uav3+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47GmG02WY0z9sPT for ; Mon, 18 Nov 2019 22:00:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0732DC21EF0; Mon, 18 Nov 2019 10:59:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 80710C21EA7; Mon, 18 Nov 2019 10:59:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C894DC21E74; Mon, 18 Nov 2019 10:59:06 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 71043C21D56 for ; Mon, 18 Nov 2019 10:59:04 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xAIAx11J081989; Mon, 18 Nov 2019 04:59:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574074741; bh=w2AfVWwBLMrYVxqxp2fHaOw0xG8FxqCXjV/3rhtZ8SY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EJ2uav3+GGv4Ouh+PXcQN38remHRCFUduG5bKc0bf4yIf8kEBpVUflhtnFXWVcDtp wI8wo2Rj1VTpefYkIe1Pc3cooaiuLBm9cJDcRCHGZD0AL/QL7bfewDKE2rEWb7Zf3+ UYBEvhJT0k13dVwuPFcfPSLYT8mgeVeCPfITHir8= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xAIAx1Z5036663 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Nov 2019 04:59:01 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 18 Nov 2019 04:59:00 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 18 Nov 2019 04:59:00 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xAIAwsJm119513; Mon, 18 Nov 2019 04:58:58 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:05 +0530 Message-ID: <20191118105910.14472-2-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 1/6] dma: Introduce dma_get_cfg() interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Sometimes, there would be a need to exchange data between DMA provider and DMA client which are very specific to DMA driver of the SoC/platform and are not generic enough to be put into struct dma. Therefore, introduce dma_get_cfg() interface to get DMA provider specific data from client device. Clients can use unique configuration ID flags to get different configuration data from DMA driver. Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- drivers/dma/dma-uclass.c | 12 ++++++++++++ include/dma-uclass.h | 11 +++++++++++ include/dma.h | 11 +++++++++++ 3 files changed, 34 insertions(+) diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 9c961cf1e2c7..2321fb513ba3 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -186,6 +186,18 @@ int dma_send(struct dma *dma, void *src, size_t len, void *metadata) return ops->send(dma, src, len, metadata); } + +int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->get_cfg) + return -ENOSYS; + + return ops->get_cfg(dma, cfg_id, cfg_data); +} #endif /* CONFIG_DMA_CHANNELS */ int dma_get_device(u32 transfer_type, struct udevice **devp) diff --git a/include/dma-uclass.h b/include/dma-uclass.h index 31b43fb4b98e..a1d9d26ac56f 100644 --- a/include/dma-uclass.h +++ b/include/dma-uclass.h @@ -108,6 +108,17 @@ struct dma_ops { * @return zero on success, or -ve error code. */ int (*send)(struct dma *dma, void *src, size_t len, void *metadata); + /** + * get_cfg() - Get DMA channel configuration for client's use + * + * @dma: The DMA Channel to manipulate + * @cfg_id: DMA provider specific ID to identify what + * configuration data client needs + * @data: Pointer to store pointer to DMA driver specific + * configuration data for the given cfg_id (output param) + * @return zero on success, or -ve error code. + */ + int (*get_cfg)(struct dma *dma, u32 cfg_id, void **data); #endif /* CONFIG_DMA_CHANNELS */ /** * transfer() - Issue a DMA transfer. The implementation must diff --git a/include/dma.h b/include/dma.h index 32885571f7d4..426617b34edf 100644 --- a/include/dma.h +++ b/include/dma.h @@ -290,6 +290,17 @@ int dma_receive(struct dma *dma, void **dst, void *metadata); * @return zero on success, or -ve error code. */ int dma_send(struct dma *dma, void *src, size_t len, void *metadata); +/** + * dma_get_cfg() - Get DMA channel configuration for client's use + * + * @dma: The DMA Channel to manipulate + * @cfg_id: DMA provider specific ID to identify what + * configuration data client needs + * @cfg_data: Pointer to store pointer to DMA driver specific + * configuration data for the given cfg_id (output param) + * @return zero on success, or -ve error code. + */ +int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data); #endif /* CONFIG_DMA_CHANNELS */ #if CONFIG_IS_ENABLED(DMA) From patchwork Mon Nov 18 10:59:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196661 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Z55HJ0a9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47GmG24frFz9sPT for ; Mon, 18 Nov 2019 22:00:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 56F99C21F02; Mon, 18 Nov 2019 10:59:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 626C1C21EE5; Mon, 18 Nov 2019 10:59:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4B583C21EEF; Mon, 18 Nov 2019 10:59:08 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id 3FF4EC21EA6 for ; Mon, 18 Nov 2019 10:59:06 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xAIAx4SY069731; Mon, 18 Nov 2019 04:59:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574074744; bh=ncacCoItGULXaXZuTXkf1Tsj1aslQHPA4KSntYoUNTg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Z55HJ0a9EMLslbAjWGey/0axyH0QL/Wa1MUZ42CeOdOhRZTTdIUWQxLHtpvWvoUbw RFdfKd+S8mbxlcIe5BVB5ec+8++5e5akAdqJhHSBXNAA3hZEhD7REswgv3js4Fxq3X pZt7KDWxnAeycYliZMXEU76N1p83TzYDcCmIZV00= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xAIAx3Db005769 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 18 Nov 2019 04:59:04 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 18 Nov 2019 04:59:03 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 18 Nov 2019 04:59:03 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xAIAwsJn119513; Mon, 18 Nov 2019 04:59:00 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:06 +0530 Message-ID: <20191118105910.14472-3-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 2/6] dma: ti: k3-udma: Implement dma_get_cfg() interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement dma_get_cfg() interface to pass flow id information for DMA clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and UDMA (DMA provider) support "flows" within a given RX DMA channel. This allows different network packets to be segregated while using same RX DMA channel. In order for basic ethernet to work, CPSW slave must be aware of the flow ID allocated for the RX channel by the DMA driver. This interface allows CPSW to query flow ID from DMA provider and configure it in CPSW HW. Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- drivers/dma/ti/k3-udma.c | 28 ++++++++++++++++++++++++++++ include/linux/soc/ti/ti-udma.h | 19 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 7336bad99412..3d24d8a7ff12 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -108,6 +108,8 @@ struct udma_chan { struct udma_rchan *rchan; struct udma_rflow *rflow; + struct ti_udma_drv_chan_cfg_data cfg_data; + u32 bcnt; /* number of bytes completed since the start of the channel */ bool pkt_mode; /* TR or packet */ @@ -1530,6 +1532,11 @@ static int udma_request(struct dma *dma) uc->desc_rx_cur = 0; uc->num_rx_bufs = 0; + if (uc->dir == DMA_DEV_TO_MEM) { + uc->cfg_data.flow_id_base = uc->rflow->id; + uc->cfg_data.flow_id_cnt = 1; + } + return 0; } @@ -1804,6 +1811,26 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) return 0; } +static int udma_get_cfg(struct dma *dma, u32 id, void **data) +{ + struct udma_dev *ud = dev_get_priv(dma->dev); + struct udma_chan *uc; + + if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) { + dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id); + return -EINVAL; + } + + switch (id) { + case TI_UDMA_CHAN_PRIV_INFO: + uc = &ud->channels[dma->id]; + *data = &uc->cfg_data; + return 0; + } + + return -EINVAL; +} + static const struct dma_ops udma_ops = { .transfer = udma_transfer, .of_xlate = udma_of_xlate, @@ -1814,6 +1841,7 @@ static const struct dma_ops udma_ops = { .send = udma_send, .receive = udma_receive, .prepare_rcv_buf = udma_prepare_rcv_buf, + .get_cfg = udma_get_cfg, }; static const struct udevice_id udma_ids[] = { diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h index e9d4226c48d9..04e354fb2d69 100644 --- a/include/linux/soc/ti/ti-udma.h +++ b/include/linux/soc/ti/ti-udma.h @@ -21,4 +21,23 @@ struct ti_udma_drv_packet_data { u32 dest_tag; }; +/** + * struct ti_udma_drv_chan_cfg_data - TI UDMA per channel specific + * configuration data + * + * @flow_id_base: Start index of flow ID allocated to this channel + * @flow_id_cnt: Number of flows allocated for this channel starting at + * flow_id_base + * + * TI UDMA channel specific data returned as part of dma_get_cfg() call + * from the DMA client driver. + */ +struct ti_udma_drv_chan_cfg_data { + u32 flow_id_base; + u32 flow_id_cnt; +}; + +/* TI UDMA specific flag IDs for dma_get_cfg() call */ +#define TI_UDMA_CHAN_PRIV_INFO 0 + #endif /* __TI_UDMA_H */ From patchwork Mon Nov 18 10:59:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196681 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="UdL8Ezlp"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47GmJ169Kcz9sR8 for ; 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Mon, 18 Nov 2019 04:59:03 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:07 +0530 Message-ID: <20191118105910.14472-4-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 3/6] net: ti: am65-cpsw-nuss: Rework RX flow ID handling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Get flow ID information for RX DMA channel using dma_get_cfg() interface instead of reading from DT. This is required in order to avoid DT update whenever there is change in the range of flow ID allocated to the host. Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- drivers/net/ti/am65-cpsw-nuss.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 06b06639506a..2e14f4be862f 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -99,7 +99,6 @@ struct am65_cpsw_common { u32 port_num; struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS]; - u32 rflow_id_base; struct mii_dev *bus; u32 bus_freq; @@ -276,6 +275,7 @@ static int am65_cpsw_start(struct udevice *dev) struct am65_cpsw_common *common = priv->cpsw_common; struct am65_cpsw_port *port = &common->ports[priv->port_id]; struct am65_cpsw_port *port0 = &common->ports[0]; + struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; int ret, i; ret = power_domain_on(&common->pwrdmn); @@ -341,7 +341,8 @@ static int am65_cpsw_start(struct udevice *dev) writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG); /* set base flow_id */ - writel(common->rflow_id_base, + dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data); + writel(dma_rx_cfg_data->flow_id_base, port0->port_base + AM65_CPSW_P0_FLOW_ID_REG); /* Reset and enable the ALE */ @@ -669,11 +670,6 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) AM65_CPSW_CPSW_NU_ALE_BASE; cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE; - cpsw_common->rflow_id_base = 0; - cpsw_common->rflow_id_base = - dev_read_u32_default(dev, "ti,rx-flow-id-base", - cpsw_common->rflow_id_base); - ports_np = dev_read_subnode(dev, "ports"); if (!ofnode_valid(ports_np)) { ret = -ENOENT; @@ -761,12 +757,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (ret) goto out; - dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u rflow_id_base:%u mdio_freq:%u\n", + dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n", readl(cpsw_common->ss_base), readl(cpsw_common->cpsw_base), readl(cpsw_common->ale_base), cpsw_common->port_num, - cpsw_common->rflow_id_base, cpsw_common->bus_freq); out: From patchwork Mon Nov 18 10:59:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196659 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="HfBYhKb0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47GmFx689Tz9sPT for ; Mon, 18 Nov 2019 22:00:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 85FA0C21EF0; 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Mon, 18 Nov 2019 04:59:06 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:08 +0530 Message-ID: <20191118105910.14472-5-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 4/6] net: ti: am65-cpsw-nuss: Add new compatible for J721e X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add new compatible to handle J721e SoC Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- drivers/net/ti/am65-cpsw-nuss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 2e14f4be862f..b606ff0ade2a 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -772,6 +772,7 @@ out: static const struct udevice_id am65_cpsw_nuss_ids[] = { { .compatible = "ti,am654-cpsw-nuss" }, + { .compatible = "ti,j721e-cpsw-nuss" }, { } }; From patchwork Mon Nov 18 10:59:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196677 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Pv50prqD"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 47GmHL64hSz9sPT for ; Mon, 18 Nov 2019 22:01:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8A998C21F18; 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Mon, 18 Nov 2019 04:59:09 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:09 +0530 Message-ID: <20191118105910.14472-6-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 5/6] arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking up on J721e EVM. Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- .../k3-j721e-common-proc-board-u-boot.dtsi | 268 ++++++++++++++++++ 1 file changed, 268 insertions(+) diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 541da22c4889..c4f2dd6b4fb2 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -3,15 +3,97 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include +#include + / { chosen { stdout-path = "serial2:115200n8"; tick-timer = &timer1; }; + + aliases { + ethernet0 = &cpsw_port1; + }; }; &cbass_main{ u-boot,dm-spl; + + cbass_main_navss: interconnect0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + dma-ranges; + ranges; + + ti,sci-dev-id = <199>; + u-boot,dm-spl; + + main_navss_intr: interrupt-controller1 { + compatible = "ti,sci-intr"; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dst-id = <14>; + ti,sci-rm-range-girq = <0>, <2>; + }; + + main_udmass_inta: interrupt-controller@33d00000 { + compatible = "ti,sci-inta"; + reg = <0x0 0x33d00000 0x0 0x100000>; + interrupt-controller; + interrupt-parent = <&main_navss_intr>; + #interrupt-cells = <3>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <209>; + ti,sci-rm-range-vint = <0xa>; + ti,sci-rm-range-global-event = <0xd>; + }; + + main_ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <1024>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <211>; + interrupt-parent = <&main_udmass_inta>; + u-boot,dm-spl; + }; + + main_udmap: udmap@31150000 { + compatible = "ti,j721e-navss-main-udmap"; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + #dma-cells = <3>; + + ti,ringacc = <&main_ringacc>; + ti,psil-base = <0x1000>; + + interrupt-parent = <&main_udmass_inta>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <212>; + + ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ + <0x0f>, /* TX_HCHAN */ + <0x10>; /* TX_UHCHAN */ + ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ + <0x0b>, /* RX_HCHAN */ + <0x0c>; /* RX_UHCHAN */ + ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ + u-boot,dm-spl; + }; + }; }; &cbass_mcu_wakeup { @@ -24,6 +106,138 @@ clock-frequency = <25000000>; u-boot,dm-spl; }; + + mcu_conf: scm_conf@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_sel: cpsw-phy-sel@4040 { + compatible = "ti,am654-cpsw-phy-sel"; + reg = <0x4040 0x4>; + reg-names = "gmii-sel"; + }; + }; + + mcu_cpsw: ethernet@046000000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges; + dma-coherent; + clocks = <&k3_clks 18 22>; + clock-names = "fck"; + power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; + ti,psil-base = <0x7000>; + cpsw-phy-sel = <&phy_sel>; + + interrupt-parent = <&main_udmass_inta>; + + dmas = <&main_udmap &mcu_cpsw 0 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 1 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 2 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 3 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 4 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 5 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 6 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 7 UDMA_DIR_TX>, + <&main_udmap &mcu_cpsw 0 UDMA_DIR_RX>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + host: host@0 { + reg = <0>; + ti,label = "host"; + }; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + ti,label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + }; + }; + + davinci_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; + + cpts { + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + + ti,psil-config0 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config1 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config2 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config3 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config4 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config5 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config6 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + + ti,psil-config7 { + linux,udma-mode = ; + statictr-type = ; + ti,needs-epib; + ti,psd-size = <16>; + }; + }; }; &secure_proxy_main { @@ -52,6 +266,29 @@ &wkup_pmx0 { u-boot,dm-spl; + mcu_cpsw_pins_default: mcu_cpsw_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu_mdio1_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; }; &main_pmx0 { @@ -73,3 +310,34 @@ &main_sdhci1 { u-boot,dm-spl; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */ + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&mcu_cpsw { + reg = <0x0 0x46000000 0x0 0x200000>, + <0x0 0x40f00200 0x0 0x2>; + reg-names = "cpsw_nuss", "mac_efuse"; + + cpsw-phy-sel@40f04040 { + compatible = "ti,am654-cpsw-phy-sel"; + reg= <0x0 0x40f04040 0x0 0x4>; + reg-names = "gmii-sel"; + }; +}; From patchwork Mon Nov 18 10:59:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1196680 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 18 Nov 2019 04:59:15 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 18 Nov 2019 04:59:15 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 18 Nov 2019 04:59:15 -0600 Received: from a0132425.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xAIAwsJr119513; Mon, 18 Nov 2019 04:59:12 -0600 From: Vignesh Raghavendra To: Lokesh Vutla , Tom Rini Date: Mon, 18 Nov 2019 16:29:10 +0530 Message-ID: <20191118105910.14472-7-vigneshr@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118105910.14472-1-vigneshr@ti.com> References: <20191118105910.14472-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de, Peter Ujfalusi , Joe Hershberger Subject: [U-Boot] [PATCH 6/6] configs: j721e_evm_a72_defconfig: Enable DMA and Ethernet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable configs related to DMA and Ethernet so as to support networking at U-Boot prompt Signed-off-by: Vignesh Raghavendra Acked-by: Joe Hershberger --- configs/j721e_evm_a72_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index f9396e612b02..748179e82317 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -59,6 +60,8 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y @@ -77,6 +80,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -91,6 +98,7 @@ CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y