From patchwork Mon Nov 18 09:37:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196612 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P8pFwrxq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQN4MgHz9sR8 for ; Mon, 18 Nov 2019 20:37:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726728AbfKRJhr (ORCPT ); Mon, 18 Nov 2019 04:37:47 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:35831 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726626AbfKRJhq (ORCPT ); Mon, 18 Nov 2019 04:37:46 -0500 Received: by mail-wr1-f67.google.com with SMTP id s5so18575397wrw.2; Mon, 18 Nov 2019 01:37:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/r/rbSHnQ681j6w5Fd1xT+tCG0CKj+LRyHPCBVvmrlM=; b=P8pFwrxqnL/iAlT+wWn4oq38pZqZta2yNEuAHyDIb1ZjDOQxlMQy8X/ezmV554mXtA 7qPCzxvNVf63u+CueuV8DHvfhXqfNHSXywFqjdaI02d5OWMyXLZBmMI7ioIbkNSqfKiA jl4L7QVsnzzQYak2nL9YfSwksJm31ddlGXeUXnzCfibnyTcIbfvXPu0kI7UuO+GTDb6Z 80LAMvSPP0J/6PVpJ6B6+jjuuVjVwK1q03/AnGi0S5d0sDPaqjUGsT28CXb5KKsH1Cya x52cOGS8VUBM65zquq9U8OOYBY13eZj6J8b/IKk7JdUy3oC06ksEDFc74Fgb8QPklqWa ZLQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/r/rbSHnQ681j6w5Fd1xT+tCG0CKj+LRyHPCBVvmrlM=; b=LHkdzBHaZGYkfHuJm6NGjSSP2P1GqKff39ru7F6krJKLnzIxUXWhL6lNED0jzXKwlo 2Tx12ZBjQrjyff1fNWnTPgvkbKguDuFyw+LREl3skW8nRd+gdHCkDSZ5ozSi28sspTF1 6rBEk8Nn96cCe4h+Uup0Cyaq8YeiY/4yFxAB4/b53Jd4ES6UCd5eHAjr3RrqJmNYUVjn lM66lv8YmNbVPsTBa5OArwGDD/6S0yP74rMZ2gHoP0XkT1+vuj7DMwSnlKDmfgSVqKjW 6O2wZ+GsdtnsAsl539F1kFmL774FIrU7WBxYcnmWmJW0uGhSU2zyxpDd+GGvNiwESI2Q K07A== X-Gm-Message-State: APjAAAWIfqSKrxMuzFzArr9mqGH/JkGe9o5QIxdQqfDL7oxZ3Im/uslQ 9f0pFc56piYerLtX3AUVB00= X-Google-Smtp-Source: APXvYqzrptzyinv4zHsSKlk4uBZG+NdIuGybLeML+SvcHF0FPHiczOcqXhndK5SV0r9Z2ybhkDjMLw== X-Received: by 2002:a5d:68c3:: with SMTP id p3mr31067514wrw.82.1574069862972; Mon, 18 Nov 2019 01:37:42 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:42 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , Rob Herring , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 1/8] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Mon, 18 Nov 2019 10:37:20 +0100 Message-Id: <20191118093727.21899-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Reviewed-by: Rob Herring Signed-off-by: Clément Péron --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..1bae446febbb 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,51 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + items: + - description: Module Clock + - description: Bus Clock + + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clock-names: true + + resets: maxItems: 1 + if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + + else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +92,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Mon Nov 18 09:37:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196619 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pDq8S9eB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQv3nFJz9sRh for ; Mon, 18 Nov 2019 20:38:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726717AbfKRJhq (ORCPT ); Mon, 18 Nov 2019 04:37:46 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:46119 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726579AbfKRJhq (ORCPT ); Mon, 18 Nov 2019 04:37:46 -0500 Received: by mail-wr1-f65.google.com with SMTP id b3so18548277wrs.13; Mon, 18 Nov 2019 01:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=pDq8S9eBLG5YpdtCLceYlK8zJHKySSMJ4gNa4obO5RzmF65RlwU73LgN2+V4Akd/r8 9nt+gRe5Lyaf5Zd85j/GTuEWkunkx8qc/Ppg40CeYy0cLTS9YNVDCBEPuzJ7XuyEGrCJ R3hNBjDFh+Npn16HM/wTRfCR+MctwUgZOeLT+OWYuxlKivqnO5CHZvnqjna3UEL3Mg2V 01+51+jKT2PN8x4dsQfCMCTqQBMFJuD6xT/7qUiK64KxeMGeyUuPaXD3IvQnPhXMxLQM pZ9lOuez7rvmJiubMR/HPxaZSo7Os6ftlqaOZ9vsV6FtgOpNQqTGKGPywa4EQev/u/6s q6Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nFDrmtiB5h/Zr80zbuCGUX75SrtWuuQxETq8orGACdo=; b=GxQAE9c5e5BEanB7dy7vUvoGWmPXtj1nCu95Fvh/Iwhbe2rRQm6csDGLw3XmxH1L3i T+2Jp918ha58FXyDE65YId2WOmLCgRBHjeGrOtttV8qxeAO3Hvo5YT2/euShIhShV/fr GjhIFWAp7RDxlJIUMTJ5NV3zWOpQ+7+3NEoZqE3qIfd6vleHg8CxeZ/Vqp4YkbTJeCeo i6gpJjusC1RK0DXOppiEHbXSNZe04RxRsPcSetW8I4SYAHC/TPlk2iWYB1bwnLb58bbu WFiv+bDqB5a+kI7VGaxXVQHF5Mnj6kodVuUumxmowPtyhwDfuBTHlWKyfOP85Vn+yoai yPOw== X-Gm-Message-State: APjAAAU7k8drbMjrJvjvJQ9hLRFM2/ndSMtlJJSRxShZPxzSsYrWtYW0 FQTxOAyTSziK+pgOmBIZPtg= X-Google-Smtp-Source: APXvYqxrEmLi5UBnckJcDzEtZ/GOtx6jGsQIN4D2M+GIJGDkkHT82C2NdqHccLyS9r8AyPBugiVUwg== X-Received: by 2002:a5d:6585:: with SMTP id q5mr25423114wru.158.1574069863961; Mon, 18 Nov 2019 01:37:43 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:43 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 2/8] pwm: sun4i: Add an optional probe for reset line Date: Mon, 18 Nov 2019 10:37:21 +0100 Message-Id: <20191118093727.21899-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Reviewed-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 581d23287333..c17935805690 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get reset failed %pe\n", + pwm->rst); + return PTR_ERR(pwm->rst); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Mon Nov 18 09:37:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AAwSAzRJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQw0sqBz9sRm for ; Mon, 18 Nov 2019 20:38:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727031AbfKRJiO (ORCPT ); Mon, 18 Nov 2019 04:38:14 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:34496 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726461AbfKRJhr (ORCPT ); Mon, 18 Nov 2019 04:37:47 -0500 Received: by mail-wr1-f68.google.com with SMTP id e6so18584423wrw.1; Mon, 18 Nov 2019 01:37:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3oSzYYj438eAKcP5hk6lqHYItTlWnnUzKNHsPAjkdJc=; b=AAwSAzRJnxMXxjJhclwhlpl/mYNzB5ilqx+RifNxbzYksBz8LgaY8HM1HjolEFjUlL htMUYi1b7/J9koh5JDoM5lang7KZDLwjE6LCARKrKo2iUv6DaNBf4lTaUQGBHu4hWz7X 5OHJlfP7Un+y6PgbkQ2SXfWbqW3hi7zz7xofwBFSxwRm6iYI23xFe3yjWbG3F6TLwiuR gdE7MYjSUXMpmX0782a7Kv8EzXZ/nArwW7O8qPZBz1ge4yY27txHV/SCApwR89XgItGo KdfQTO0P4EOkM8udo8IuJ90uquKhx1zz25e4/iCrXyT7XdDJoUkD8E5S10WNQHl0FOAt NbdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3oSzYYj438eAKcP5hk6lqHYItTlWnnUzKNHsPAjkdJc=; b=nJ3hGiLxrsmnklzROxvIkRTpLuHKJqlfd2wX5n+RjiAwuDJnuYGg1ywRKP9ch3AYZd BqJnxSAxJVnK0G+bjiCXBy2mg1YyicCoJS0kXoJ6dktzzEIozrnon+dvfTFU0apczGaO A2p00V5Cw4weHpRI0qleQ1DvFvo4461e8nrw4GXPFJtePPrlRtDswoxEbsV/Cb0Z/LyU 97VjZGbi3qs8EOKrTyGGZDLapG2MxpYq9wcaG0UEKosz8qA8lkNZfZNKOJj8DxkoD8QZ ffyIS2+RljDVdrhccvJ1K7WnSbO+ozYECSpBkfBAcqbVRwBwxaplRqUFVR2I4iq7nVZR +nug== X-Gm-Message-State: APjAAAXRrLPSXFQcCkKc9VtMeoRjFAphO47Q7NF9BsGj25GYpPsZvnbn 5wRrLQH689Y1ouewcO7x+h4= X-Google-Smtp-Source: APXvYqzDOwuq0A8F4oYn60+HJq1SW+kqllssigTTUg8uT9nBRUvhHeMoTlhVG7xt0+yV2c7Jg6TXXw== X-Received: by 2002:adf:fd91:: with SMTP id d17mr28262822wrr.214.1574069864966; Mon, 18 Nov 2019 01:37:44 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:44 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 3/8] pwm: sun4i: Prefer "mod" clock to unnamed Date: Mon, 18 Nov 2019 10:37:22 +0100 Message-Id: <20191118093727.21899-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org New device tree bindings called the source clock of the module "mod" when several clocks are defined. Try to get a clock called "mod" if nothing is found try to get an unnamed clock. Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index c17935805690..bbb1ed194c0e 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->base)) return PTR_ERR(pwm->base); - pwm->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) + /* + * All hardware variants need a source clock that is divided and + * then feeds the counter that defines the output wave form. In the + * device tree this clock is either unnamed or called "mod". + * Some variants (e.g. H6) need another clock to access the + * hardware registers; this is called "bus". + * So we request "mod" first (and ignore the corner case that a + * parent provides a "mod" clock while the right one would be the + * unnamed one of the PWM device) and if this is not found we fall + * back to the first clock of the PWM. + */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get clock failed %pe\n", + pwm->clk); return PTR_ERR(pwm->clk); + } + + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get clock failed %pe\n", + pwm->clk); + return PTR_ERR(pwm->clk); + } + } pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { From patchwork Mon Nov 18 09:37:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P8eEcz0r"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQt3J8hz9sR8 for ; Mon, 18 Nov 2019 20:38:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727000AbfKRJiJ (ORCPT ); Mon, 18 Nov 2019 04:38:09 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:38720 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726716AbfKRJhr (ORCPT ); Mon, 18 Nov 2019 04:37:47 -0500 Received: by mail-wr1-f65.google.com with SMTP id i12so18561894wro.5; Mon, 18 Nov 2019 01:37:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HiEB14HdJo07lXE127L0D4zLI4SiB6r7sIlA8IG1R+w=; b=P8eEcz0rpMwHCPRfIcNF7thKCA2HcPHqC95B0QFpDk663hyYC/nXYlpRG2l0mANVq8 vmDXNF3g4M5+cNxIy1taw8q3s9r2d5QAmFcHAjQ7kBNpjqjaUKL7DXIDBUOrLd80TdT2 C+lAUnZCi5tKfFCNtcrSYboJJDA596WPmEiuF09l1lT5+pCLs2tqAoFfiBjnr9xaEjcp 8X6hDjMU/t+C/xxdCapOxprOWxjoOK0It7gzOyMEOneDBqTlfCnqFaaCGIeM5OKFPM+M GyBstZgzR8aenHjLxpjqmPnubVKgiF1l2f9LaaHUoE+rnucKwLNk2P6tyHyZ+2lPJGdJ eEZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HiEB14HdJo07lXE127L0D4zLI4SiB6r7sIlA8IG1R+w=; b=ra87QaueYkqvkH9hFzojfgPi6U49xC53TzflEidViH80lk9Z7F4bBZEBYdIUzQJap6 L8eg9p7+bFKo3DQn1w1bxac48tsnwPB36uzZJGNJrHtAav6IGPc3pvDYun1Z/QByz2GV mheS7Tsas71JKCEfq8DAW9+Iku9RfGEaQfgHn8RrEeVu2yBMbPFrNb/+17omibpqnb9l qBMY8K03/uLIUs5LdtQwYhXPfce8z+c0qGmvYCN6HEPmnMm/ECtw/W56lqkuVvNTZ9FM Jlk8ejFTI5N4fMqTsyfW981Q9XIfHut2R7bmT1kTtelviWolq33bOffcfemo4Et8mdWd 2t/w== X-Gm-Message-State: APjAAAV0SGsBcBl3m1taVv5idL5/mHOw0l+Av7G8AspeOSAp9NGieGhK BrGD5yoakTMxfm+082RS+jzBQNvfQJJF0g== X-Google-Smtp-Source: APXvYqwTngUkIiY9ZbT6/ObAG2RnFts4cd7nnJ9PwnrchZyQajMB6mNe0CMJioRCBqdlAR8I5rEy9g== X-Received: by 2002:adf:db4b:: with SMTP id f11mr1434099wrj.239.1574069866054; Mon, 18 Nov 2019 01:37:46 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:45 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 4/8] pwm: sun4i: Add an optional probe for bus clock Date: Mon, 18 Nov 2019 10:37:23 +0100 Message-Id: <20191118093727.21899-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it and a fallback for previous bindings without name on module clock. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index bbb1ed194c0e..93f4d44e9fa8 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) } } + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get bus_clock failed %pe\n", + pwm->bus_clk); + return PTR_ERR(pwm->bus_clk); + } + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) @@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* + * We're keeping the bus clock on for the sake of simplicity. + * Actually it only needs to be on for hardware register accesses. + */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -426,6 +445,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -440,6 +461,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Mon Nov 18 09:37:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Az5+tvsw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQd6wMtz9sR8 for ; Mon, 18 Nov 2019 20:38:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbfKRJhw (ORCPT ); Mon, 18 Nov 2019 04:37:52 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:38721 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726740AbfKRJhu (ORCPT ); Mon, 18 Nov 2019 04:37:50 -0500 Received: by mail-wr1-f65.google.com with SMTP id i12so18561955wro.5; Mon, 18 Nov 2019 01:37:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W5bXqrIjuWnRPljMAMXu9KqQKUGPcEz+PkaSRuI1ExA=; b=Az5+tvswXbvmz0HeEAtt2I2L3bhgy+u1mRpAd/GTF55zJWIkj4blVtjePK93mA4FKV vYv8Xjf0ZT7CfkevgldTJQ42mnRhDLpePzrpvLIe8xvXOgSynLWThLrTYhVQkTvaLQ6A eHG9bIEPHlKWVpOIxTCTRLGjw3RdV/wG1U4hBh3O9K/uw6AWDfL9ZgZI1pW9+ivUoB/b 8R0AZFGbFR1+no3ZDLdr2oJ97Ln2jpeXK62jO/a5CHWkFQMzALcOIHVODDp6zNnOb3m/ u5j+m0ossmM+c9heb6swprZskVDMzi5B/8K9vXdUYmy17osLjkgXKbLhdvkxVRUvRaiR ohQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W5bXqrIjuWnRPljMAMXu9KqQKUGPcEz+PkaSRuI1ExA=; b=huV6rvp0tp8CkkB/rz6S/ntUJRoM326CEQcUINpoVbCJYx1JPtb+FZmWI4WBS3abEw Icizg3fjjys1OJxmPbJtXBbpI3P36muT7erLZeb6PgR7KfTMZAo52BGYxA7P1mglirGa 9Epj+ghA4SXCwPrg3YVl1wp2+Wz43mcRGL68gPRSmkh/3DC5v9e7wZ9ijQWnbvFG6g8u qaF4Ej70UN60IvUOO3/OSzlqsAPHaQ3qDaIvExoK6vb+JPZWB1pMFMY8Yss2M/x7w2Pt CnvnxyLIJLHp1QGG0kwXzXObhrTSpD3WKC5Uobt3j/QqwrC5XsTsMc0XDAJHb3wDGC/H 1MlA== X-Gm-Message-State: APjAAAU08+cSDq3/DBLsn8a0UYt3BEXoBVeetiKDm3AGbCWlXJlFYCmc Uro3f0UrdBq7hlRv1CQexu0= X-Google-Smtp-Source: APXvYqxwdhYMF82bItahGWRsWafBgu/DOH+ZN5cArMrkQvd3gVfhaSL84Pb234f0SxbwfO13R5r23g== X-Received: by 2002:adf:f607:: with SMTP id t7mr28746843wrp.390.1574069866687; Mon, 18 Nov 2019 01:37:46 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:46 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 5/8] pwm: sun4i: Add support to output source clock directly Date: Mon, 18 Nov 2019 10:37:24 +0100 Message-Id: <20191118093727.21899-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++------------- 1 file changed, 64 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 93f4d44e9fa8..b64250b7e2be 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, const struct pwm_state *state, - u32 *dty, u32 *prd, unsigned int *prsclr) + u32 *dty, u32 *prd, unsigned int *prsclr, + bool *bypass) { u64 clk_rate, div = 0; unsigned int pval, prescaler = 0; clk_rate = clk_get_rate(sun4i_pwm->clk); + *bypass = state->enabled && + (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + + /* Skip calculation of other parameters if we bypass them */ + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) + return 0; + if (sun4i_pwm->data->has_prescaler_bypass) { /* First, test without any prescaler when available */ prescaler = PWM_PRESCAL_MASK; @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, period, duty, val; int ret; - unsigned int delay_us; + unsigned int delay_us, prescaler; unsigned long now; + bool bypass; pwm_get_state(pwm, &cstate); @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - if ((cstate.period != state->period) || - (cstate.duty_cycle != state->duty_cycle)) { - u32 period, duty, val; - unsigned int prescaler; + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, + &bypass); + if (ret) { + dev_err(chip->dev, "period exceeds the maximum value\n"); + spin_unlock(&sun4i_pwm->ctrl_lock); + if (!cstate.enabled) + clk_disable_unprepare(sun4i_pwm->clk); + return ret; + } - ret = sun4i_pwm_calculate(sun4i_pwm, state, - &duty, &period, &prescaler); - if (ret) { - dev_err(chip->dev, "period exceeds the maximum value\n"); - spin_unlock(&sun4i_pwm->ctrl_lock); - if (!cstate.enabled) - clk_disable_unprepare(sun4i_pwm->clk); - return ret; + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) { + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + /* We can skip apply of other parameters */ + goto bypass_mode; + } else { + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); } + } - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { - /* Prescaler changed, the clock has to be gated */ - ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - - ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); - ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } + if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { + /* Prescaler changed, the clock has to be gated */ + ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - val = (duty & PWM_DTY_MASK) | PWM_PRD(period); - sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); - sun4i_pwm->next_period[pwm->hwpwm] = jiffies + - usecs_to_jiffies(cstate.period / 1000 + 1); - sun4i_pwm->needs_delay[pwm->hwpwm] = true; + ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); + ctrl |= BIT_CH(prescaler, pwm->hwpwm); } + val = (duty & PWM_DTY_MASK) | PWM_PRD(period); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); + sun4i_pwm->next_period[pwm->hwpwm] = jiffies + + usecs_to_jiffies(cstate.period / 1000 + 1); + sun4i_pwm->needs_delay[pwm->hwpwm] = true; + if (state->polarity != PWM_POLARITY_NORMAL) ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); else ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -264,6 +299,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Mon Nov 18 09:37:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196613 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qIiuY4DC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQV5Rtlz9sRY for ; Mon, 18 Nov 2019 20:37:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbfKRJhw (ORCPT ); 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[82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:46 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 6/8] pwm: sun4i: Add support for H6 PWM Date: Mon, 18 Nov 2019 10:37:25 +0100 Message-Id: <20191118093727.21899-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Acked-by: Uwe Kleine-König Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index b64250b7e2be..8d6699659db7 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -358,6 +358,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -374,6 +380,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Mon Nov 18 09:37:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pEnL5y/J"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQm0q0mz9sRf for ; Mon, 18 Nov 2019 20:38:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726953AbfKRJiB (ORCPT ); Mon, 18 Nov 2019 04:38:01 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:43107 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726795AbfKRJhu (ORCPT ); Mon, 18 Nov 2019 04:37:50 -0500 Received: by mail-wr1-f65.google.com with SMTP id n1so18524582wra.10; Mon, 18 Nov 2019 01:37:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=pEnL5y/JfRfOj2VPs0MQ3Dm3cpqhOVzzq3YSk4naex2AEYy/SLeY89R3sGnuctZItW BxhOnaPxdCNgbUsWYzgKqs5uERI7uJONWQf8gCeZisSfvEp5Fro370miD//0aoHX0xOf BGOvV8yRCtX8pxFbShH5ClZ2zACLzMspCc4WOq95oKRaQZY4u1uAbWlqdeQ9JzFuaUJg S+mn15qg9dQrTvcYtm3wnEZyu29s+b8FN+UZOD5DfVFQ9JhNSPmnpJq6hDcgo1afGQV/ RSYi95GxiUyNXVc1hlSe6w49Q5GF6DrnL++1l2W0mqLKqV5mzJej2HNcphKzTTzWCREh CqjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q0mPzKXAC37oXp0wVkV8/ys9/u7aTcSnLuWMUuY5ccw=; b=bIab1tacR1WG4uMqyEl6Hy3Ixj9JyCD+quCZDcRTdOyTW69y2KMuffYXxq6nxJpTEl piOLevePDof/VqUi7Bx5XGaymXs1HM7tcrxVRO3ExL3DPA/bude4mdHGwVDWI9cbFfaS YFVwGPNcGGLKnJdI01xqNtVmCKIeuhsSwpQo3JYS3v79mP6lCGORgz/+fIfeZbc4YcNe p67nTGWnDjd56Y7nCaViJxTsmDcUxPWlVJ2aNf8vE5Fk1GE8hmSQBDsphuD3VYkxO3ax 23zsHMyYHGv8tu5etx4ZeyHhDRb3k1RM/hGpyH3e2TYx9CrLhsAwwBV8JbB2xn/4XiUI iQLA== X-Gm-Message-State: APjAAAVlWA2kr9WmcisUfl5VjR6CMeBtH2H3Txb/IHYb7CRhyWnFaBuv w7U2zsRiGeGR1s4XaWQmrcoTruSEcSlWgA== X-Google-Smtp-Source: APXvYqxuDV4SIDq7LKd+hcWzsyqT+zaAXEO9EyFr4PnVgO9NKkGUDD24RwUvGUU9Rstz0wduFfOpBg== X-Received: by 2002:a5d:49c4:: with SMTP id t4mr29606700wrs.226.1574069868491; Mon, 18 Nov 2019 01:37:48 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:47 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 7/8] arm64: dts: allwinner: h6: Add PWM node Date: Mon, 18 Nov 2019 10:37:26 +0100 Message-Id: <20191118093727.21899-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 29824081b43b..6d4bde488f15 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -245,6 +245,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Mon Nov 18 09:37:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1196616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tLOox4gX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47GkQn2Rx6z9sRM for ; Mon, 18 Nov 2019 20:38:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726874AbfKRJiB (ORCPT ); Mon, 18 Nov 2019 04:38:01 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:34821 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726626AbfKRJhv (ORCPT ); Mon, 18 Nov 2019 04:37:51 -0500 Received: by mail-wr1-f65.google.com with SMTP id s5so18575817wrw.2; Mon, 18 Nov 2019 01:37:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=tLOox4gXBgeuMcVf6MPAAv697SJ+irwwdmKmBr5Y/n1W/KDxkadEcy+ffgp4gbfPu2 YZV8mDzXoU/DHJ4YvPNk6Gx8xVQUmQM+rWgm8jV3IXROjViFIosyi2eLKzbPRW4PsS3p w54uwjSjthL3gl9VJ3VhNtAYWBieiOu9+kVg6q3m/yVXyE1y5OY9eCfPv7+ckJEiJIAq 3bYg3t107yXwdeHQdxi5D7FPBk/kxLgrhUYhnR+GJEYplDIVEeSm6GpMp2u9nO5bK99X H2eZa0YyOymjzaVKyI355x9IQR2srhgyyc0MldA0FBfy5LN5srnSclLFv+FCrhfjOTCh sZ5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iGqUalssFt90BW+qC26cPJ2ocimtOg3RIH0RE3W1sS4=; b=dwjBxqU5sIuKzFvxSrCEzCkwCrqDUgWzWyrpzNz47zVs8CeN3AQhsm0jftHjl6uC/I XVbxVjQzuHtaZjOQn/TrT0jgKZweb7JpivHPX9aEs7RMDY3ffbFXd9NOtnirUehHbc8L //N+SR0rpkFia1KenZDC5v3UrnGUrMzGUwaDT627ITU23wUkfcKkHNT1D95wYgpI+Tly sWyoKHgMzv0ov8hD+//piJQI3vGe2yTWLdq/4DgcRoWuG0fI6FXHW9fQaCmvHQnPn5ts mti0fNCI62Kna4g6FY0+Tn0nglkaPaVBLvlhvroZ+LmPAUNTfwDDnL2QRbdoU7up2wQv GNCA== X-Gm-Message-State: APjAAAXyXXyKkZPy185pV4NHXC6irZAiuUryrU9ZJ4xiBWePadaUxRIj 97Y/wo2qLrWp3j2RJN+zzeM= X-Google-Smtp-Source: APXvYqwJTC4TGwM9hvlm2LKX+ev9HQJG633L3So58N0alxBGkAmetvFIYpwsUfKCX1Z+oAukbL2Qkg== X-Received: by 2002:a5d:4b08:: with SMTP id v8mr26653916wrq.338.1574069869088; Mon, 18 Nov 2019 01:37:49 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id w10sm19006687wmd.26.2019.11.18.01.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 01:37:48 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?b?w7ZuaWc=?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v5 8/8] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Mon, 18 Nov 2019 10:37:27 +0100 Message-Id: <20191118093727.21899-9-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191118093727.21899-1-peron.clem@gmail.com> References: <20191118093727.21899-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index f335f7482a73..cf684bc7374d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -136,6 +136,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";