From patchwork Wed Nov 6 12:10:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QQ25978z9sNx for ; Wed, 6 Nov 2019 23:12:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IwH8jwEA"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477QQ14wpLzF5sQ for ; Wed, 6 Nov 2019 23:12:09 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::543; helo=mail-pg1-x543.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IwH8jwEA"; dkim-atps=neutral Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QP45z7gzF5rw for ; Wed, 6 Nov 2019 23:11:20 +1100 (AEDT) Received: by mail-pg1-x543.google.com with SMTP id q22so9395606pgk.2 for ; Wed, 06 Nov 2019 04:11:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABHnyc9cGiUchiY4LlVwkTd97Le2d9Q8dXvPTCHUoFc=; b=IwH8jwEAAhsOumWJ/hAKZvfpXwkrujzavFQ2Y1AJclNgV3Qmh7nEkhVYiKAJmnMCPv o6Vu6XHusPU1fLnHSE663DbMhTYp99E6S8jR/2D8oW9PRClA1kA9+K59+49WjhDtZrN2 Ef84sFQTYRLk0pJhgV0celfje8ocPXmh1fOIuztex4y4em7UiwTQ3b6rfoX/09R7GUtg GNdEp19hnoQk9ZXoR2LHvSTeYldTMtIPQKFzfFtVuHdmaUNJb6EUr/M9MxgfTw91Xscu Q7k2ID31/t3HVI/jNphxQnc6exBr42Xb66zXF+/plYHBQdYI12PFxstE7PSBaFLKVLPi t+jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABHnyc9cGiUchiY4LlVwkTd97Le2d9Q8dXvPTCHUoFc=; b=md8EeUvKf0RuqlyUqIV6X/Ma4GYIeNa40+LyyYS6gVtii2Wwagh3Bse/ESsR8xT/u3 7hacT07BOIWn/eSLsj4thbLhAZn1ikCYfVaHXYx+5D9z4o8Fqkpw/OOLb/62rAwSphrZ ZHL0S3fIqcDE71/BUSigP4E+jzWiUvp8lsFpnHjI7klzU0Heg/fHMYjFORWTk24O/o7U oT1KNdaGLjDYlpGkdMU+gAviq/GFVNfqnHxI48GBy+Xkc/vUCQdW/tl+m1mSonRjH+Ld 9Ai0AFZiB66LlvzFL2iDhbvHD0g3mX5GOvaLvaQyGd3nQkmRfxrooXBKogoGiV+Sd8Df Sx5g== X-Gm-Message-State: APjAAAXHeexYk7uve0+nizMjXFGdkOHGWwtm3NdgPUh2LySEwhf4PYTu DNRC4MTmpqq2C+bMHjEJM101rJ7y X-Google-Smtp-Source: APXvYqwCFvWTXwhu9puNQdf5lSwdBySprDXjiPUHqnOFmXxaChTnLjhlAVYwGglP4xp324bXFh512A== X-Received: by 2002:a63:7158:: with SMTP id b24mr2498785pgn.153.1573042277831; Wed, 06 Nov 2019 04:11:17 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:17 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:19 +1000 Message-Id: <20191106121047.14389-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 01/29] asm/cvc_entry.S: r2 save fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The TOC save area for the current stack frame should be used to save r2, not the caller's frame. Acked-by: Stewart Smith Signed-off-by: Nicholas Piggin --- asm/cvc_entry.S | 9 +++++++-- include/stack.h | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/asm/cvc_entry.S b/asm/cvc_entry.S index 1296e88fe..3e8b3fdad 100644 --- a/asm/cvc_entry.S +++ b/asm/cvc_entry.S @@ -24,6 +24,11 @@ #.include "kernel/ppcconsts.S" +# Updated hostboot location is src/securerom/rom_entry.S. +# This also has a fix for TOC save frame pointer. + +#include + .section .text .global __cvc_verify_v1 @@ -33,10 +38,10 @@ __cvc_verify_v1: __cvc_sha512_v1: call_rom_entry: - std %r2, 40(%r1) mflr %r0 std %r0, 16(%r1) stdu %r1, -128(%r1) + std %r2, STACK_TOC_OFFSET(%r1) li %r2, 0 mtctr %r3 mr %r3, %r4 @@ -45,8 +50,8 @@ call_rom_entry: mr %r6, %r7 mr %r7, %r8 bctrl + ld %r2, STACK_TOC_OFFSET(%r1) addi %r1, %r1, 128 - ld %r2, 40(%r1) ld %r0, 16(%r1) mtlr %r0 blr diff --git a/include/stack.h b/include/stack.h index 3ad52d64c..09d22adb6 100644 --- a/include/stack.h +++ b/include/stack.h @@ -11,6 +11,8 @@ #define STACK_ENTRY_RESET 0x0100 /* System reset */ #define STACK_ENTRY_SOFTPATCH 0x1500 /* Soft patch (denorm emulation) */ +#define STACK_TOC_OFFSET 40 + /* Safety/ABI gap at top of stack */ #define STACK_TOP_GAP 0x100 From patchwork Wed Nov 6 12:10:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QQd1RS1z9sNx for ; Wed, 6 Nov 2019 23:12:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QCyCcYXS"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477QQd072jzF5w9 for ; Wed, 6 Nov 2019 23:12:41 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::42d; helo=mail-pf1-x42d.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QCyCcYXS"; dkim-atps=neutral Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QP73pMkzF5rs for ; Wed, 6 Nov 2019 23:11:23 +1100 (AEDT) Received: by mail-pf1-x42d.google.com with SMTP id d13so18733363pfq.2 for ; Wed, 06 Nov 2019 04:11:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KCojVVM987ttqjr2R1DjqYbLWh6UW1lFIFw5/enC6eY=; b=QCyCcYXSK9gQifQV7JV1tQ5J0QxdwRH0UA+GFjrI+LBTT6n+6Yu1jpgt8xSfsAP7WX GyHy4+5fz5RdP91EFlhP6s9isbmN71LaifrcTHbLXTmanoTSK/uh7ei0MokTfAf8ICGR xAgeQnKXWCVxYXCTAIucwqwXYjorv8o0yrdKGRfn2vCn+zTpUN8z5ZGj8hFsJrnjmKlf OFgTMwXgrBOADFP1hGQ/z8UbORrSlq4KavUMNEoDLbRQRCs+m5Yx1EwXOvLJRWvN4zvH t4qzI//AQmgYY+C1fbc3T6KnCMFqhHK4Asv2Mjxt9fysaMi7HhqrGipMhw2UNz+DkiXy sj7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KCojVVM987ttqjr2R1DjqYbLWh6UW1lFIFw5/enC6eY=; b=WHnVDF5vCQeTJZNtkbYOFaIryWVhjkJbJwUAktkNXNsuEOtrKMPWNFfOo48W1lgkwQ GnuUqxnvz0Km5Q7LALdMS1UaeqsVDW5muWxIS68e8OzzTURSnZOh/3R5eF1Gctu7IugC LAKutqqxDq7+ZnowCnhsD4IYzays+YYwxgWPHNpgV5Rq2KKWrURW5FF9NPgF0NUpji0W vMdSmlmAjEyzlcoroCe00Q9hVWp6LPYdmZQlNcijzoeOzgeU2I2dKpXH6sPPzqzRWpQo YKqPKo7r87vamjprIz2L6FV0MFq4Y4Xf5WSUXIJEuO1rJfTsWFRy0yzXjg+CH6oY0BVj P/rA== X-Gm-Message-State: APjAAAXsff3iAZuI4he4o60UrRZt6AhrEGMkkj4uEqA0TamATj6gM1Kh 0pnyShIb+frGjjAysEdAZ/vkpKJEXEM= X-Google-Smtp-Source: APXvYqx6wUqoWcrW4lb6ySQjOM0JLjl5MNoZY8c3w3zJMn2eA5ADs7Duyl0JD4QsBA1DkhKHHqv17A== X-Received: by 2002:a63:4d0d:: with SMTP id a13mr2449530pgb.451.1573042280573; Wed, 06 Nov 2019 04:11:20 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:20 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:20 +1000 Message-Id: <20191106121047.14389-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 02/29] Remove dead POWER7 code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. And change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. Acked-by: Stewart Smith Signed-off-by: Nicholas Piggin --- asm/head.S | 10 ------- hdata/paca.c | 80 ---------------------------------------------------- 2 files changed, 90 deletions(-) diff --git a/asm/head.S b/asm/head.S index 58f9aea97..426b5d5c1 100644 --- a/asm/head.S +++ b/asm/head.S @@ -857,16 +857,6 @@ hv_lid_load_table: .long 0 - /* The FSP seems to ignore our primary/secondary entry - * points and instead copy that bit down to 0x180 and - * patch the first instruction to get our expected - * boot CPU number. We ignore that patching for now and - * got to the same entry we use for pHyp and FDT HB. - */ -opal_boot_trampoline: - li %r27,-1 - ba boot_entry - __head - /* * * OPAL entry point from operating system diff --git a/hdata/paca.c b/hdata/paca.c index 28025b0cd..3e8d89856 100644 --- a/hdata/paca.c +++ b/hdata/paca.c @@ -12,8 +12,6 @@ #include "hdata.h" -#define PACA_MAX_THREADS 4 - static unsigned int paca_index(const struct HDIF_common_hdr *paca) { void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); @@ -121,77 +119,6 @@ static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num) arr[i] = new; } -static void add_xics_icps(void) -{ - struct dt_node *cpu; - unsigned int i; - u64 reg[PACA_MAX_THREADS * 2]; - struct dt_node *icp; - - dt_for_each_node(dt_root, cpu) { - u32 irange[2], size, pir; - const struct dt_property *intsrv; - const struct HDIF_common_hdr *paca; - u64 ibase; - unsigned int num_threads; - bool found = false; - - if (!dt_has_node_property(cpu, "device_type", "cpu")) - continue; - - intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); - if (!intsrv) - continue; - - pir = dt_prop_get_u32(cpu, "ibm,pir"); - - /* Get ibase address */ - paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); - for_each_paca(paca) { - const struct sppaca_cpu_id *id; - id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size); - - if (!CHECK_SPPTR(id)) - continue; - - if (pir != be32_to_cpu(id->pir)) - continue; - ibase = cleanup_addr(be64_to_cpu(id->ibase)); - found = true; - break; - } - if (!found) - return; - - num_threads = intsrv->len / sizeof(u32); - assert(num_threads <= PACA_MAX_THREADS); - - icp = dt_new_addr(dt_root, "interrupt-controller", ibase); - if (!icp) - continue; - - dt_add_property_strings(icp, "compatible", - "IBM,ppc-xicp", - "IBM,power7-xicp"); - - irange[0] = dt_property_get_cell(intsrv, 0); /* Index */ - irange[1] = num_threads; /* num servers */ - dt_add_property(icp, "ibm,interrupt-server-ranges", - irange, sizeof(irange)); - dt_add_property(icp, "interrupt-controller", NULL, 0); - dt_add_property_cells(icp, "#address-cells", 0); - dt_add_property_string(icp, "device_type", - "PowerPC-External-Interrupt-Presentation"); - for (i = 0; i < num_threads*2; i += 2) { - reg[i] = ibase; - /* One page is enough for a handful of regs. */ - reg[i+1] = 4096; - ibase += reg[i+1]; - } - dt_add_property(icp, "reg", reg, sizeof(reg)); - } -} - static bool __paca_parse(void) { const struct HDIF_common_hdr *paca; @@ -311,13 +238,6 @@ static bool __paca_parse(void) free(new_prop); } - /* - * P7 and P8 use the XICS interrupt controller which has a per-core - * interrupt controller node. - */ - if (proc_gen <= proc_gen_p8) - add_xics_icps(); - return true; } From patchwork Wed Nov 6 12:10:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QRG45HSz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:23 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:21 +1000 Message-Id: <20191106121047.14389-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 03/29] capp: fix endian conversion X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Donnellan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Acked-by: Stewart Smith Reviewed-by: Andrew Donnellan Signed-off-by: Nicholas Piggin --- hw/capp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/capp.c b/hw/capp.c index 709e6db14..269deb637 100644 --- a/hw/capp.c +++ b/hw/capp.c @@ -168,7 +168,7 @@ int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id, /* 'CAPPULID' in ASCII */ if ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944UL) || - (be64_to_cpu(ucode->version != 1))) { + (be64_to_cpu(ucode->version) != 1)) { PHBERR(opal_id, chip_id, index, "CAPP: ucode header invalid\n"); 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:25 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:22 +1000 Message-Id: <20191106121047.14389-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 04/29] cpu: use dt accessor device tree access X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/cpu.c | 2 +- core/device.c | 1 + core/fdt.c | 4 ++-- core/interrupts.c | 4 ++-- core/pci.c | 28 +++++++++++++--------------- hdata/fsp.c | 7 ++++--- hdata/iohub.c | 20 ++++++++++---------- hw/fsp/fsp-sysparam.c | 4 ++-- hw/fsp/fsp.c | 2 +- hw/imc.c | 4 ++-- hw/lpc.c | 6 +++--- hw/psi.c | 8 ++++---- hw/vas.c | 6 ++---- 13 files changed, 47 insertions(+), 49 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index d0e4cdc1c..b3433aef5 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1214,7 +1214,7 @@ void init_all_cpus(void) t = &cpu_stacks[pir + thread].cpu; init_cpu_thread(t, state, pir + thread); t->trace = boot_cpu->trace; - t->server_no = ((const u32 *)p->prop)[thread]; + t->server_no = dt_property_get_cell(p, thread); t->is_secondary = true; t->primary = pt; t->node = cpu; diff --git a/core/device.c b/core/device.c index ce0171b67..0118d485f 100644 --- a/core/device.c +++ b/core/device.c @@ -1110,6 +1110,7 @@ void dt_adjust_subtree_phandle(struct dt_node *dev, continue; phandle = dt_prop_get_u32(node, *name); phandle += import_phandle; + phandle = cpu_to_be32(phandle); memcpy((char *)&prop->prop, &phandle, prop->len); } } diff --git a/core/fdt.c b/core/fdt.c index d3c6d9fa1..e093e8b54 100644 --- a/core/fdt.c +++ b/core/fdt.c @@ -146,8 +146,8 @@ static void create_dtb_reservemap(void *fdt, const struct dt_node *root) ranges = (const void *)prop->prop; for (i = 0; i < prop->len / (sizeof(uint64_t) * 2); i++) { - base = *(ranges++); - size = *(ranges++); + base = be64_to_cpu(*(ranges++)); + size = be64_to_cpu(*(ranges++)); save_err(fdt_add_reservemap_entry(fdt, base, size)); } } diff --git a/core/interrupts.c b/core/interrupts.c index b0c1da198..10baa15f6 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -231,8 +231,8 @@ void add_opal_interrupts(void) names[tns++] = 0; i = count++; irqs = realloc(irqs, 8 * count); - irqs[i*2] = isn; - irqs[i*2+1] = iflags; + irqs[i*2] = cpu_to_be32(isn); + irqs[i*2+1] = cpu_to_be32(iflags); } } unlock(&irq_lock); diff --git a/core/pci.c b/core/pci.c index 9ee70f4fd..6c5c83bea 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1334,7 +1334,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np, { uint32_t *map, *p; int dev, irq, esize, edevcount; - size_t map_size, isize; + size_t map_size; /* Some emulated setups don't use standard interrupts * representation @@ -1342,9 +1342,6 @@ void pci_std_swizzle_irq_map(struct dt_node *np, if (lstate->int_size == 0) return; - /* Size in bytes of a target interrupt */ - isize = lstate->int_size * sizeof(uint32_t); - /* Calculate the size of a map entry: * * 3 cells : PCI Address @@ -1384,22 +1381,23 @@ void pci_std_swizzle_irq_map(struct dt_node *np, for (dev = 0; dev < edevcount; dev++) { for (irq = 0; irq < 4; irq++) { /* Calculate pin */ + size_t i; uint32_t new_irq = (irq + dev + swizzle) % 4; /* PCI address portion */ - *(p++) = dev << (8 + 3); + *(p++) = cpu_to_be32(dev << (8 + 3)); *(p++) = 0; *(p++) = 0; /* PCI interrupt portion */ - *(p++) = irq + 1; + *(p++) = cpu_to_be32(irq + 1); /* Parent phandle */ - *(p++) = lstate->int_parent[new_irq]; + *(p++) = cpu_to_be32(lstate->int_parent[new_irq]); /* Parent desc */ - memcpy(p, lstate->int_val[new_irq], isize); - p += lstate->int_size; + for (i = 0; i < lstate->int_size; i++) + *(p++) = cpu_to_be32(lstate->int_val[new_irq][i]); } } @@ -1549,16 +1547,16 @@ static void __noinline pci_add_one_device_node(struct phb *phb, char name[MAX_NAME]; char compat[MAX_NAME]; uint32_t rev_class, vdid; - uint32_t reg[5]; + __be32 reg[5]; uint8_t intpin; bool is_pcie; - const uint32_t ranges_direct[] = { + const __be32 ranges_direct[] = { /* 64-bit direct mapping. We know the bridges * don't cover the entire address space so * use 0xf00... as a good compromise. */ - 0x02000000, 0x0, 0x0, - 0x02000000, 0x0, 0x0, - 0xf0000000, 0x0}; + cpu_to_be32(0x02000000), 0x0, 0x0, + cpu_to_be32(0x02000000), 0x0, 0x0, + cpu_to_be32(0xf0000000), 0x0}; pci_cfg_read32(phb, pd->bdfn, 0, &vdid); pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class); @@ -1635,7 +1633,7 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * entry in the "reg" property. That's enough for Linux and we might * even want to make this legit in future ePAPR */ - reg[0] = pd->bdfn << 8; + reg[0] = cpu_to_be32(pd->bdfn << 8); reg[1] = reg[2] = reg[3] = reg[4] = 0; dt_add_property(np, "reg", reg, sizeof(reg)); diff --git a/hdata/fsp.c b/hdata/fsp.c index 5923f1feb..fe36eef18 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -206,7 +206,7 @@ static void fsp_create_links(const void *spss, int index, chip = fsp_create_link(iopath, i, index); lp = lcount++; links = realloc(links, 4 * lcount); - links[lp] = chip; + links[lp] = cpu_to_be32(chip); } if (links) dt_add_property(fsp_node, "ibm,psi-links", links, lcount * 4); @@ -268,7 +268,7 @@ static void add_uart(const struct spss_iopath *iopath, struct dt_node *lpc) be32_to_cpu(iopath->lpc.uart_baud)); } -static void add_chip_id_to_sensors(struct dt_node *sensor_node, __be32 slca_index) +static void add_chip_id_to_sensors(struct dt_node *sensor_node, uint32_t slca_index) { unsigned int i; const void *hdif; @@ -347,7 +347,8 @@ static void add_ipmi_sensors(struct dt_node *bmc_node) dt_add_property_cells(sensor_node, "ipmi-sensor-type", ipmi_sensors->data[i].type); - add_chip_id_to_sensors(sensor_node, ipmi_sensors->data[i].slca_index); + add_chip_id_to_sensors(sensor_node, + be32_to_cpu(ipmi_sensors->data[i].slca_index)); } } diff --git a/hdata/iohub.c b/hdata/iohub.c index 6921d95ce..2af040a2f 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -109,12 +109,12 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, /* "reg" property contains in order the PE, PCI and SPCI XSCOM * addresses */ - reg[0] = pe_xscom; - reg[1] = 0x20; - reg[2] = pci_xscom; - reg[3] = 0x05; - reg[4] = spci_xscom; - reg[5] = 0x15; + reg[0] = cpu_to_be32(pe_xscom); + reg[1] = cpu_to_be32(0x20); + reg[2] = cpu_to_be32(pci_xscom); + reg[3] = cpu_to_be32(0x05); + reg[4] = cpu_to_be32(spci_xscom); + reg[5] = cpu_to_be32(0x15); dt_add_property(pbcq, "reg", reg, sizeof(reg)); /* A couple more things ... */ @@ -214,10 +214,10 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, return NULL; /* "reg" property contains (in order) the PE and PCI XSCOM addresses */ - reg[0] = pe_xscom; - reg[1] = 0x100; - reg[2] = pci_xscom; - reg[3] = 0x200; + reg[0] = cpu_to_be32(pe_xscom); + reg[1] = cpu_to_be32(0x100); + reg[2] = cpu_to_be32(pci_xscom); + reg[3] = cpu_to_be32(0x200); dt_add_property(pbcq, "reg", reg, sizeof(reg)); /* The hubs themselves go under the stacks */ diff --git a/hw/fsp/fsp-sysparam.c b/hw/fsp/fsp-sysparam.c index 09005ef87..0e1e8181f 100644 --- a/hw/fsp/fsp-sysparam.c +++ b/hw/fsp/fsp-sysparam.c @@ -469,8 +469,8 @@ static void add_opal_sysparam_node(void) strcpy(s, sysparam_attrs[i].name); s = s + strlen(sysparam_attrs[i].name) + 1; - ids[i] = sysparam_attrs[i].id; - lens[i] = sysparam_attrs[i].length; + ids[i] = cpu_to_be32(sysparam_attrs[i].id); + lens[i] = cpu_to_be32(sysparam_attrs[i].length); perms[i] = sysparam_attrs[i].perm; } diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 6fa6534f9..7193c6f4c 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -1915,7 +1915,7 @@ static void fsp_init_links(struct dt_node *fsp_node) u64 reg; u32 link; - link = ((const u32 *)linksprop->prop)[i]; + link = be32_to_cpu(((const __be32 *)linksprop->prop)[i]); fiop = &fsp->iopath[i]; fiop->psi = psi_find_link(link); if (fiop->psi == NULL) { diff --git a/hw/imc.c b/hw/imc.c index ca06f3c36..16b060d39 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -458,8 +458,8 @@ static void imc_dt_update_nest_node(struct dt_node *dev) base_addr = malloc(sizeof(uint64_t) * nr_chip); chipids = malloc(sizeof(uint32_t) * nr_chip); for_each_chip(chip) { - base_addr[i] = chip->homer_base; - chipids[i] = chip->id; + base_addr[i] = cpu_to_be64(chip->homer_base); + chipids[i] = cpu_to_be32(chip->id); i++; } diff --git a/hw/lpc.c b/hw/lpc.c index 354d2b4f0..3411f036f 100644 --- a/hw/lpc.c +++ b/hw/lpc.c @@ -884,9 +884,9 @@ static void lpc_create_int_map(struct lpcm *lpc, struct dt_node *psi_node) continue; *(pmap++) = 0; *(pmap++) = 0; - *(pmap++) = i; - *(pmap++) = psi_node->phandle; - *(pmap++) = lpc->sirq_routes[i] + P9_PSI_IRQ_LPC_SIRQ0; + *(pmap++) = cpu_to_be32(i); + *(pmap++) = cpu_to_be32(psi_node->phandle); + *(pmap++) = cpu_to_be32(lpc->sirq_routes[i] + P9_PSI_IRQ_LPC_SIRQ0); } if (pmap == map) return; diff --git a/hw/psi.c b/hw/psi.c index bc170bbcf..3b497a092 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -786,10 +786,10 @@ static void psi_create_p9_int_map(struct psi *psi, struct dt_node *np) int i; for (i = 0; i < P9_PSI_NUM_IRQS; i++) { - map[i][0] = i; - map[i][1] = get_ics_phandle(); - map[i][2] = psi->interrupt + i; - map[i][3] = 1; + map[i][0] = cpu_to_be32(i); + map[i][1] = cpu_to_be32(get_ics_phandle()); + map[i][2] = cpu_to_be32(psi->interrupt + i); + map[i][3] = cpu_to_be32(1); } dt_add_property(np, "interrupt-map", map, sizeof(map)); dt_add_property_cells(np, "#address-cells", 0); diff --git a/hw/vas.c b/hw/vas.c index 212da0ec1..82a07904c 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -375,7 +375,6 @@ static struct vas *alloc_vas(uint32_t chip_id, uint32_t vas_id, uint64_t base) static void create_mm_dt_node(struct proc_chip *chip) { - int gcid; struct dt_node *dn; struct vas *vas; uint64_t hvwc_start, hvwc_len; @@ -384,7 +383,6 @@ static void create_mm_dt_node(struct proc_chip *chip) uint64_t pbf_start, pbf_nbits; vas = chip->vas; - gcid = chip->id; get_hvwc_mmio_bar(chip->id, &hvwc_start, &hvwc_len); get_uwc_mmio_bar(chip->id, &uwc_start, &uwc_len); get_paste_bar(chip->id, &pbar_start, &pbar_len); @@ -400,8 +398,8 @@ static void create_mm_dt_node(struct proc_chip *chip) pbar_start, pbar_len, pbf_start, pbf_nbits); - dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id)); - dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid)); + dt_add_property_cells(dn, "ibm,vas-id", vas->vas_id); + dt_add_property_cells(dn, "ibm,chip-id", chip->id); } /* From patchwork Wed Nov 6 12:10:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QSR1VNsz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:28 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:23 +1000 Message-Id: <20191106121047.14389-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 05/29] opal-api: add endian conversions to most opal calls X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds missing endian conversions to most calls, sufficient at least to handle calls from a kernel booting on mambo. Subsystems requiring more extensive changes (e.g., xive) will be done with individual changes. Signed-off-by: Nicholas Piggin --- core/console.c | 19 +++++--- core/interrupts.c | 8 +++- core/ipmi-opal.c | 6 +-- core/pci-opal.c | 98 +++++++++++++++++++++++++++++++---------- core/powercap.c | 14 ++++-- core/psr.c | 14 ++++-- core/sensor.c | 60 ++++++++++++++++--------- hw/fake-rtc.c | 11 +++-- hw/fsp/fsp-console.c | 26 ++++++----- hw/fsp/fsp-rtc.c | 25 ++++++----- hw/ipmi/ipmi-rtc.c | 11 +++-- hw/lpc-rtc.c | 11 +++-- hw/lpc-uart.c | 16 +++---- hw/npu2-opencapi.c | 12 +++-- hw/xscom.c | 19 +++++++- include/console.h | 6 +-- platforms/mambo/mambo.c | 9 +++- 17 files changed, 252 insertions(+), 113 deletions(-) diff --git a/core/console.c b/core/console.c index 139ba4a97..ac88f0c71 100644 --- a/core/console.c +++ b/core/console.c @@ -351,22 +351,25 @@ void memcons_add_properties(void) * complicated since they can come from the in-memory console (BML) or from the * internal skiboot console driver. */ -static int64_t dummy_console_write(int64_t term_number, int64_t *length, +static int64_t dummy_console_write(int64_t term_number, __be64 *length, const uint8_t *buffer) { + uint64_t l; + if (term_number != 0) return OPAL_PARAMETER; if (!opal_addr_valid(length) || !opal_addr_valid(buffer)) return OPAL_PARAMETER; - write(0, buffer, *length); + l = be64_to_cpu(*length); + write(0, buffer, l); return OPAL_SUCCESS; } static int64_t dummy_console_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *length) { if (term_number != 0) return OPAL_PARAMETER; @@ -375,21 +378,25 @@ static int64_t dummy_console_write_buffer_space(int64_t term_number, return OPAL_PARAMETER; if (length) - *length = INMEM_CON_OUT_LEN; + *length = cpu_to_be64(INMEM_CON_OUT_LEN); return OPAL_SUCCESS; } -static int64_t dummy_console_read(int64_t term_number, int64_t *length, +static int64_t dummy_console_read(int64_t term_number, __be64 *length, uint8_t *buffer) { + uint64_t l; + if (term_number != 0) return OPAL_PARAMETER; if (!opal_addr_valid(length) || !opal_addr_valid(buffer)) return OPAL_PARAMETER; - *length = read(0, buffer, *length); + l = be64_to_cpu(*length); + l = read(0, buffer, l); + *length = cpu_to_be64(l); opal_update_pending_evt(OPAL_EVENT_CONSOLE_INPUT, 0); return OPAL_SUCCESS; diff --git a/core/interrupts.c b/core/interrupts.c index 10baa15f6..d4a2c3124 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -439,9 +439,11 @@ static int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority) } opal_call(OPAL_SET_XIVE, opal_set_xive, 3); -static int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority) +static int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority) { struct irq_source *is = irq_find_source(isn); + uint16_t s; + int64_t ret; if (!opal_addr_valid(server)) return OPAL_PARAMETER; @@ -449,7 +451,9 @@ static int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority) if (!is || !is->ops->get_xive) return OPAL_PARAMETER; - return is->ops->get_xive(is, isn, server, priority); + ret = is->ops->get_xive(is, isn, &s, priority); + *server = cpu_to_be16(s); + return ret; } opal_call(OPAL_GET_XIVE, opal_get_xive, 3); diff --git a/core/ipmi-opal.c b/core/ipmi-opal.c index 796508ca0..d36962d36 100644 --- a/core/ipmi-opal.c +++ b/core/ipmi-opal.c @@ -57,7 +57,7 @@ static int64_t opal_ipmi_send(uint64_t interface, } static int64_t opal_ipmi_recv(uint64_t interface, - struct opal_ipmi_msg *opal_ipmi_msg, uint64_t *msg_len) + struct opal_ipmi_msg *opal_ipmi_msg, __be64 *msg_len) { struct ipmi_msg *msg; int64_t rc; @@ -82,7 +82,7 @@ static int64_t opal_ipmi_recv(uint64_t interface, goto out_del_msg; } - if (*msg_len - sizeof(struct opal_ipmi_msg) < msg->resp_size + 1) { + if (be64_to_cpu(*msg_len) - sizeof(struct opal_ipmi_msg) < msg->resp_size + 1) { rc = OPAL_RESOURCE; goto out_del_msg; } @@ -101,7 +101,7 @@ static int64_t opal_ipmi_recv(uint64_t interface, msg->cmd, msg->netfn >> 2, msg->resp_size); /* Add one as the completion code is returned in the message data */ - *msg_len = msg->resp_size + sizeof(struct opal_ipmi_msg) + 1; + *msg_len = cpu_to_be64(msg->resp_size + sizeof(struct opal_ipmi_msg) + 1); ipmi_free_msg(msg); return OPAL_SUCCESS; diff --git a/core/pci-opal.c b/core/pci-opal.c index 828ce8a97..25c701e6f 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -58,9 +58,38 @@ OPAL_PCICFG_ACCESS_WRITE(write_byte, write8, uint8_t) OPAL_PCICFG_ACCESS_WRITE(write_half_word, write16, uint16_t) OPAL_PCICFG_ACCESS_WRITE(write_word, write32, uint32_t) +static int64_t opal_pci_config_read_half_word_be(uint64_t phb_id, + uint64_t bus_dev_func, + uint64_t offset, + __be16 *__data) +{ + uint16_t data; + int64_t rc; + + rc = opal_pci_config_read_half_word(phb_id, bus_dev_func, offset, &data); + *__data = cpu_to_be16(data); + + return rc; +} + +static int64_t opal_pci_config_read_word_be(uint64_t phb_id, + uint64_t bus_dev_func, + uint64_t offset, + __be32 *__data) +{ + uint32_t data; + int64_t rc; + + rc = opal_pci_config_read_word(phb_id, bus_dev_func, offset, &data); + *__data = cpu_to_be32(data); + + return rc; +} + + opal_call(OPAL_PCI_CONFIG_READ_BYTE, opal_pci_config_read_byte, 4); -opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, opal_pci_config_read_half_word, 4); -opal_call(OPAL_PCI_CONFIG_READ_WORD, opal_pci_config_read_word, 4); +opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, opal_pci_config_read_half_word_be, 4); +opal_call(OPAL_PCI_CONFIG_READ_WORD, opal_pci_config_read_word_be, 4); opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, opal_pci_config_write_byte, 4); opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, opal_pci_config_write_half_word, 4); opal_call(OPAL_PCI_CONFIG_WRITE_WORD, opal_pci_config_write_word, 4); @@ -87,14 +116,15 @@ void opal_pci_eeh_clear_evt(uint64_t phb_id) static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, uint8_t *freeze_state, - uint16_t *pci_error_type, - uint64_t *phb_status) + __be16 *__pci_error_type, + __be64 *__phb_status) { struct phb *phb = pci_get_phb(phb_id); + uint16_t pci_error_type; int64_t rc; - if (!opal_addr_valid(freeze_state) || !opal_addr_valid(pci_error_type) - || !opal_addr_valid(phb_status)) + if (!opal_addr_valid(freeze_state) || !opal_addr_valid(__pci_error_type) + || !opal_addr_valid(__phb_status)) return OPAL_PARAMETER; if (!phb) @@ -103,12 +133,13 @@ static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, return OPAL_UNSUPPORTED; phb_lock(phb); - if (phb_status) + if (__phb_status) prlog(PR_ERR, "PHB#%04llx: %s: deprecated PHB status\n", phb_id, __func__); rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state, - pci_error_type, NULL); + &pci_error_type, NULL); + *__pci_error_type = cpu_to_be16(pci_error_type); phb_unlock(phb); return rc; @@ -371,12 +402,14 @@ opal_call(OPAL_PCI_SET_XIVE_PE, opal_pci_set_xive_pe, 3); static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, uint8_t msi_range, - uint32_t *msi_address, uint32_t *message_data) + __be32 *__msi_address, __be32 *__message_data) { struct phb *phb = pci_get_phb(phb_id); + uint32_t msi_address; + uint32_t message_data; int64_t rc; - if (!opal_addr_valid(msi_address) || !opal_addr_valid(message_data)) + if (!opal_addr_valid(__msi_address) || !opal_addr_valid(__message_data)) return OPAL_PARAMETER; if (!phb) @@ -385,21 +418,26 @@ static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, return OPAL_UNSUPPORTED; phb_lock(phb); rc = phb->ops->get_msi_32(phb, mve_number, xive_num, msi_range, - msi_address, message_data); + &msi_address, &message_data); phb_unlock(phb); + *__msi_address = cpu_to_be32(msi_address); + *__message_data = cpu_to_be32(message_data); + return rc; } opal_call(OPAL_GET_MSI_32, opal_get_msi_32, 6); static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, uint8_t msi_range, - uint64_t *msi_address, uint32_t *message_data) + __be64 *__msi_address, __be32 *__message_data) { struct phb *phb = pci_get_phb(phb_id); + uint64_t msi_address; + uint32_t message_data; int64_t rc; - if (!opal_addr_valid(msi_address) || !opal_addr_valid(message_data)) + if (!opal_addr_valid(__msi_address) || !opal_addr_valid(__message_data)) return OPAL_PARAMETER; if (!phb) @@ -408,9 +446,12 @@ static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, return OPAL_UNSUPPORTED; phb_lock(phb); rc = phb->ops->get_msi_64(phb, mve_number, xive_num, msi_range, - msi_address, message_data); + &msi_address, &message_data); phb_unlock(phb); + *__msi_address = cpu_to_be64(msi_address); + *__message_data = cpu_to_be32(message_data); + return rc; } opal_call(OPAL_GET_MSI_64, opal_get_msi_64, 6); @@ -918,14 +959,17 @@ static int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, } opal_call(OPAL_PCI_GET_PHB_DIAG_DATA2, opal_pci_get_phb_diag_data2, 3); -static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, - uint16_t *pci_error_type, uint16_t *severity) +static int64_t opal_pci_next_error(uint64_t phb_id, __be64 *__first_frozen_pe, + __be16 *__pci_error_type, __be16 *__severity) { struct phb *phb = pci_get_phb(phb_id); + uint64_t first_frozen_pe; + uint16_t pci_error_type; + uint16_t severity; int64_t rc; - if (!opal_addr_valid(first_frozen_pe) || - !opal_addr_valid(pci_error_type) || !opal_addr_valid(severity)) + if (!opal_addr_valid(__first_frozen_pe) || + !opal_addr_valid(__pci_error_type) || !opal_addr_valid(__severity)) return OPAL_PARAMETER; if (!phb) @@ -935,10 +979,14 @@ static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, phb_lock(phb); opal_pci_eeh_clear_evt(phb_id); - rc = phb->ops->next_error(phb, first_frozen_pe, pci_error_type, - severity); + rc = phb->ops->next_error(phb, &first_frozen_pe, &pci_error_type, + &severity); phb_unlock(phb); + *__first_frozen_pe = cpu_to_be64(first_frozen_pe); + *__pci_error_type = cpu_to_be16(pci_error_type); + *__severity = cpu_to_be16(severity); + return rc; } opal_call(OPAL_PCI_NEXT_ERROR, opal_pci_next_error, 4); @@ -999,11 +1047,12 @@ static int64_t opal_pci_set_p2p(uint64_t phbid_init, uint64_t phbid_target, } opal_call(OPAL_PCI_SET_P2P, opal_pci_set_p2p, 4); -static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) +static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, __be64 *__addr) { struct phb *phb = pci_get_phb(phb_id); + uint64_t addr; - if (!opal_addr_valid(addr)) + if (!opal_addr_valid(__addr)) return OPAL_PARAMETER; if (!phb) @@ -1012,8 +1061,11 @@ static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) return OPAL_UNSUPPORTED; phb_lock(phb); - phb->ops->get_tunnel_bar(phb, addr); + phb->ops->get_tunnel_bar(phb, &addr); phb_unlock(phb); + + *__addr = cpu_to_be64(addr); + return OPAL_SUCCESS; } opal_call(OPAL_PCI_GET_PBCQ_TUNNEL_BAR, opal_pci_get_pbcq_tunnel_bar, 2); diff --git a/core/powercap.c b/core/powercap.c index b9d172b54..de2a79095 100644 --- a/core/powercap.c +++ b/core/powercap.c @@ -7,13 +7,19 @@ #include -static int opal_get_powercap(u32 handle, int token __unused, u32 *pcap) +static int opal_get_powercap(u32 handle, int token __unused, __be32 *__pcap) { - if (!pcap || !opal_addr_valid(pcap)) + if (!__pcap || !opal_addr_valid(__pcap)) return OPAL_PARAMETER; - if (powercap_get_class(handle) == POWERCAP_CLASS_OCC) - return occ_get_powercap(handle, pcap); + if (powercap_get_class(handle) == POWERCAP_CLASS_OCC) { + u32 pcap; + int rc; + + rc = occ_get_powercap(handle, &pcap); + *__pcap = cpu_to_be32(pcap); + return rc; + } return OPAL_UNSUPPORTED; }; diff --git a/core/psr.c b/core/psr.c index 4cd3768ae..6698df8d2 100644 --- a/core/psr.c +++ b/core/psr.c @@ -10,13 +10,19 @@ #include static int opal_get_power_shift_ratio(u32 handle, int token __unused, - u32 *ratio) + __be32 *__ratio) { - if (!ratio || !opal_addr_valid(ratio)) + if (!__ratio || !opal_addr_valid(__ratio)) return OPAL_PARAMETER; - if (psr_get_class(handle) == PSR_CLASS_OCC) - return occ_get_psr(handle, ratio); + if (psr_get_class(handle) == PSR_CLASS_OCC) { + u32 ratio; + int rc; + + rc = occ_get_psr(handle, &ratio); + *__ratio = cpu_to_be32(ratio); + return rc; + } return OPAL_UNSUPPORTED; }; diff --git a/core/sensor.c b/core/sensor.c index a804f968a..d3b15aa16 100644 --- a/core/sensor.c +++ b/core/sensor.c @@ -20,12 +20,12 @@ static LIST_HEAD(async_read_list); struct sensor_async_read { struct list_node link; - u64 *sensor_data64; - u32 *sensor_data32; + u64 *val; + __be32 *opal_data; int token; }; -static int add_to_async_read_list(int token, u32 *data32, u64 *data64) +static int add_to_async_read_list(int token, __be32 *opal_data, u64 *val) { struct sensor_async_read *req; @@ -34,8 +34,8 @@ static int add_to_async_read_list(int token, u32 *data32, u64 *data64) return OPAL_NO_MEM; req->token = token; - req->sensor_data64 = data64; - req->sensor_data32 = data32; + req->val = val; + req->opal_data = opal_data; lock(&async_read_list_lock); list_add_tail(&async_read_list, &req->link); @@ -59,50 +59,70 @@ void check_sensor_read(int token) if (!req) goto out; - *req->sensor_data32 = *req->sensor_data64; - free(req->sensor_data64); + *req->opal_data = cpu_to_be32((u32)*req->val); + free(req->val); list_del(&req->link); free(req); out: unlock(&async_read_list_lock); } -static s64 opal_sensor_read_u64(u32 sensor_hndl, int token, u64 *sensor_data) +static s64 sensor_read(u32 sensor_hndl, int token, u64 *data) { + s64 rc; + switch (sensor_get_family(sensor_hndl)) { case SENSOR_DTS: - return dts_sensor_read(sensor_hndl, token, sensor_data); + rc = dts_sensor_read(sensor_hndl, token, data); + return rc; + case SENSOR_OCC: - return occ_sensor_read(sensor_hndl, sensor_data); + rc = occ_sensor_read(sensor_hndl, data); + return rc; + default: break; } - if (platform.sensor_read) - return platform.sensor_read(sensor_hndl, token, sensor_data); + if (platform.sensor_read) { + rc = platform.sensor_read(sensor_hndl, token, data); + return rc; + } return OPAL_UNSUPPORTED; } +static s64 opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *__data) +{ + u64 data; + s64 rc; + + rc = sensor_read(sensor_hndl, token, &data); + if (rc == OPAL_SUCCESS) + *__data = cpu_to_be64(data); + + return rc; +} + static int64_t opal_sensor_read(uint32_t sensor_hndl, int token, - uint32_t *sensor_data) + __be32 *__data) { u64 *val; - s64 ret; + s64 rc; val = zalloc(sizeof(*val)); if (!val) return OPAL_NO_MEM; - ret = opal_sensor_read_u64(sensor_hndl, token, val); - if (!ret) { - *sensor_data = *val; + rc = sensor_read(sensor_hndl, token, val); + if (rc == OPAL_SUCCESS) { + *__data = cpu_to_be32((u32)*val); free(val); - } else if (ret == OPAL_ASYNC_COMPLETION) { - ret = add_to_async_read_list(token, sensor_data, val); + } else if (rc == OPAL_ASYNC_COMPLETION) { + rc = add_to_async_read_list(token, __data, val); } - return ret; + return rc; } static int opal_sensor_group_clear(u32 group_hndl, int token) diff --git a/hw/fake-rtc.c b/hw/fake-rtc.c index 328be97d9..fd2882d68 100644 --- a/hw/fake-rtc.c +++ b/hw/fake-rtc.c @@ -34,13 +34,15 @@ static int64_t fake_rtc_write(uint32_t ymd, uint64_t hmsm) return OPAL_SUCCESS; } -static int64_t fake_rtc_read(uint32_t *ymd, uint64_t *hmsm) +static int64_t fake_rtc_read(__be32 *__ymd, __be64 *__hmsm) { time_t sec; struct tm tm_calculated; + uint32_t ymd; + uint64_t hmsm; - if (!ymd || !hmsm) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; /* Compute the emulated clock value */ @@ -48,10 +50,13 @@ static int64_t fake_rtc_read(uint32_t *ymd, uint64_t *hmsm) sec = tb_to_secs(mftb() - tb_synctime) + mktime(&tm_offset); gmtime_r(&sec, &tm_calculated); - tm_to_datetime(&tm_calculated, ymd, hmsm); + tm_to_datetime(&tm_calculated, &ymd, &hmsm); unlock(&emulation_lock); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); + return OPAL_SUCCESS; } diff --git a/hw/fsp/fsp-console.c b/hw/fsp/fsp-console.c index 42fb98806..837eab5fd 100644 --- a/hw/fsp/fsp-console.c +++ b/hw/fsp/fsp-console.c @@ -579,7 +579,7 @@ void fsp_console_preinit(void) } -static int64_t fsp_console_write(int64_t term_number, int64_t *length, +static int64_t fsp_console_write(int64_t term_number, __be64 *__length, const uint8_t *buffer) { struct fsp_serial *fs; @@ -596,7 +596,7 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, return OPAL_CLOSED; } /* Clamp to a reasonable size */ - requested = *length; + requested = be64_to_cpu(*__length); if (requested > 0x1000) requested = 0x1000; written = fsp_write_vserial(fs, buffer, requested); @@ -618,7 +618,7 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, buffer[6], buffer[6], buffer[7], buffer[7]); #endif /* OPAL_DEBUG_CONSOLE_IO */ - *length = written; + *__length = cpu_to_be64(written); unlock(&fsp_con_lock); if (written) @@ -628,11 +628,12 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, } static int64_t fsp_console_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *__length) { static bool elog_generated = false; struct fsp_serial *fs; struct fsp_serbuf_hdr *sb; + int64_t length; if (term_number < 0 || term_number >= MAX_SERIAL) return OPAL_PARAMETER; @@ -645,15 +646,16 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, return OPAL_CLOSED; } sb = fs->out_buf; - *length = (sb->next_out + SER_BUF_DATA_SIZE - sb->next_in - 1) + length = (sb->next_out + SER_BUF_DATA_SIZE - sb->next_in - 1) % SER_BUF_DATA_SIZE; unlock(&fsp_con_lock); /* Console buffer has enough space to write incoming data */ - if (*length != fs->out_buf_prev_len) { - fs->out_buf_prev_len = *length; + if (length != fs->out_buf_prev_len) { + fs->out_buf_prev_len = length; fs->out_buf_timeout = 0; + *__length = cpu_to_be64(length); return OPAL_SUCCESS; } @@ -667,8 +669,10 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, secs_to_tb(SER_BUFFER_OUT_TIMEOUT); } - if (tb_compare(mftb(), fs->out_buf_timeout) != TB_AAFTERB) + if (tb_compare(mftb(), fs->out_buf_timeout) != TB_AAFTERB) { + *__length = cpu_to_be64(length); return OPAL_SUCCESS; + } /* * FSP is still active but not reading console data. Hence @@ -686,13 +690,13 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, return OPAL_RESOURCE; } -static int64_t fsp_console_read(int64_t term_number, int64_t *length, +static int64_t fsp_console_read(int64_t term_number, __be64 *__length, uint8_t *buffer) { struct fsp_serial *fs; struct fsp_serbuf_hdr *sb; bool pending = false; - uint32_t old_nin, n, i, chunk, req = *length; + uint32_t old_nin, n, i, chunk, req = be64_to_cpu(*__length); int rc = OPAL_SUCCESS; if (term_number < 0 || term_number >= MAX_SERIAL) @@ -716,7 +720,7 @@ static int64_t fsp_console_read(int64_t term_number, int64_t *length, pending = true; n = req; } - *length = n; + *__length = cpu_to_be64(n); chunk = SER_BUF_DATA_SIZE - sb->next_out; if (chunk > n) diff --git a/hw/fsp/fsp-rtc.c b/hw/fsp/fsp-rtc.c index 53838f87c..e68836e66 100644 --- a/hw/fsp/fsp-rtc.c +++ b/hw/fsp/fsp-rtc.c @@ -249,12 +249,13 @@ static int64_t fsp_rtc_send_read_request(void) return OPAL_BUSY_EVENT; } -static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, - uint64_t *hour_minute_second_millisecond) +static int64_t fsp_opal_rtc_read(__be32 *__ymd, __be64 *__hmsm) { int64_t rc; + uint32_t ymd; + uint64_t hmsm; - if (!year_month_day || !hour_minute_second_millisecond) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; lock(&rtc_lock); @@ -267,8 +268,7 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, /* During R/R of FSP, read cached TOD */ if (fsp_in_rr()) { if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -290,11 +290,9 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, opal_rtc_eval_events(true); if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); prlog(PR_TRACE,"FSP-RTC Cached datetime: %x %llx\n", - *year_month_day, - *hour_minute_second_millisecond); + ymd, hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -306,8 +304,7 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, prlog(PR_TRACE, "RTC read timed out\n"); if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -319,6 +316,12 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, } out: unlock(&rtc_lock); + + if (rc == OPAL_SUCCESS) { + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); + } + return rc; } diff --git a/hw/ipmi/ipmi-rtc.c b/hw/ipmi/ipmi-rtc.c index deb4addcb..ad98f21c6 100644 --- a/hw/ipmi/ipmi-rtc.c +++ b/hw/ipmi/ipmi-rtc.c @@ -62,12 +62,13 @@ static int64_t ipmi_set_sel_time(uint32_t _tv) return ipmi_queue_msg(msg); } -static int64_t ipmi_opal_rtc_read(uint32_t *y_m_d, - uint64_t *h_m_s_m) +static int64_t ipmi_opal_rtc_read(__be32 *__ymd, __be64 *__hmsm) { int ret = 0; + uint32_t ymd; + uint64_t hmsm; - if (!y_m_d || !h_m_s_m) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; switch(time_status) { @@ -83,7 +84,9 @@ static int64_t ipmi_opal_rtc_read(uint32_t *y_m_d, break; case updated: - rtc_cache_get_datetime(y_m_d, h_m_s_m); + rtc_cache_get_datetime(&ymd, &hmsm); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); time_status = idle; ret = OPAL_SUCCESS; break; diff --git a/hw/lpc-rtc.c b/hw/lpc-rtc.c index f560c8c9f..ba15941fb 100644 --- a/hw/lpc-rtc.c +++ b/hw/lpc-rtc.c @@ -139,14 +139,15 @@ static void lpc_init_hw(void) unlock(&rtc_lock); } -static int64_t lpc_opal_rtc_read(uint32_t *y_m_d, - uint64_t *h_m_s_m) +static int64_t lpc_opal_rtc_read(__be32 *__ymd, __be64 *__hmsm) { uint8_t val; int64_t rc = OPAL_SUCCESS; struct tm tm; + uint32_t ymd; + uint64_t hmsm; - if (!y_m_d || !h_m_s_m) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; /* Return busy if updating. This is somewhat racy, but will @@ -172,7 +173,9 @@ static int64_t lpc_opal_rtc_read(uint32_t *y_m_d, rtc_cache_update(&tm); /* Convert to OPAL time */ - tm_to_datetime(&tm, y_m_d, h_m_s_m); + tm_to_datetime(&tm, &ymd, &hmsm); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); } return rc; diff --git a/hw/lpc-uart.c b/hw/lpc-uart.c index feca229b6..b37e04201 100644 --- a/hw/lpc-uart.c +++ b/hw/lpc-uart.c @@ -255,10 +255,10 @@ static uint32_t uart_tx_buf_space(void) (out_buf_prod + OUT_BUF_SIZE - out_buf_cons) % OUT_BUF_SIZE; } -static int64_t uart_opal_write(int64_t term_number, int64_t *length, +static int64_t uart_opal_write(int64_t term_number, __be64 *__length, const uint8_t *buffer) { - size_t written = 0, len = *length; + size_t written = 0, len = be64_to_cpu(*__length); if (term_number != 0) return OPAL_PARAMETER; @@ -277,19 +277,19 @@ static int64_t uart_opal_write(int64_t term_number, int64_t *length, unlock(&uart_lock); - *length = written; + *__length = cpu_to_be64(written); return OPAL_SUCCESS; } static int64_t uart_opal_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *__length) { if (term_number != 0) return OPAL_PARAMETER; lock(&uart_lock); - *length = uart_tx_buf_space(); + *__length = cpu_to_be64(uart_tx_buf_space()); unlock(&uart_lock); return OPAL_SUCCESS; @@ -326,10 +326,10 @@ static void uart_adjust_opal_event(void) } /* This is called with the console lock held */ -static int64_t uart_opal_read(int64_t term_number, int64_t *length, +static int64_t uart_opal_read(int64_t term_number, __be64 *__length, uint8_t *buffer) { - size_t req_count = *length, read_cnt = 0; + size_t req_count = be64_to_cpu(*__length), read_cnt = 0; uint8_t lsr = 0; if (term_number != 0) @@ -373,7 +373,7 @@ static int64_t uart_opal_read(int64_t term_number, int64_t *length, /* Adjust the OPAL event */ uart_adjust_opal_event(); - *length = read_cnt; + *__length = cpu_to_be64(read_cnt); return OPAL_SUCCESS; } diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index fc9e50c3f..902462a29 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -2251,10 +2251,12 @@ out: } static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, - uint64_t size, uint64_t *bar) + uint64_t size, __be64 *__bar) { struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; + uint64_t bar; + int64_t rc; if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) @@ -2264,10 +2266,14 @@ static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, if (!dev) return OPAL_PARAMETER; - if (!opal_addr_valid(bar)) + if (!opal_addr_valid(__bar)) return OPAL_PARAMETER; - return alloc_mem_bar(dev, size, bar); + rc = alloc_mem_bar(dev, size, &bar); + if (rc == OPAL_SUCCESS) + *__bar = cpu_to_be64(bar); + + return rc; } opal_call(OPAL_NPU_MEM_ALLOC, opal_npu_mem_alloc, 4); diff --git a/hw/xscom.c b/hw/xscom.c index 9b28422d2..38ec72199 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -639,7 +639,17 @@ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_loc return rc; } -opal_call(OPAL_XSCOM_READ, xscom_read, 3); +static int64_t opal_xscom_read(uint32_t partid, uint64_t pcb_addr, __be64 *__val) +{ + uint64_t val; + int64_t rc; + + rc = xscom_read(partid, pcb_addr, &val); + *__val = cpu_to_be64(val); + + return rc; +} +opal_call(OPAL_XSCOM_READ, opal_xscom_read, 3); int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_lock) { @@ -683,7 +693,12 @@ int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_loc unlock(&xscom_lock); return rc; } -opal_call(OPAL_XSCOM_WRITE, xscom_write, 3); + +static int64_t opal_xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) +{ + return xscom_write(partid, pcb_addr, val); +} +opal_call(OPAL_XSCOM_WRITE, opal_xscom_write, 3); /* * Perform a xscom read-modify-write. diff --git a/include/console.h b/include/console.h index 26602b7ac..230b825b0 100644 --- a/include/console.h +++ b/include/console.h @@ -47,13 +47,13 @@ struct opal_con_ops { */ void (*init)(void); - int64_t (*write)(int64_t term, int64_t *len, const uint8_t *buf); - int64_t (*read)(int64_t term, int64_t *len, uint8_t *buf); + int64_t (*write)(int64_t term, __be64 *__len, const uint8_t *buf); + int64_t (*read)(int64_t term, __be64 *__len, uint8_t *buf); /* * returns the amount of space available in the console write buffer */ - int64_t (*space)(int64_t term_number, int64_t *length); + int64_t (*space)(int64_t term_number, __be64 *__length); /* * Forces the write buffer to be flushed by the driver diff --git a/platforms/mambo/mambo.c b/platforms/mambo/mambo.c index e523cd3eb..aa1bf8305 100644 --- a/platforms/mambo/mambo.c +++ b/platforms/mambo/mambo.c @@ -173,11 +173,13 @@ static void bogus_disk_flash_init(void) } } -static int64_t mambo_rtc_read(uint32_t *ymd, uint64_t *hmsm) +static int64_t mambo_rtc_read(__be32 *ymd, __be64 *hmsm) { int64_t mambo_time; struct tm t; time_t mt; + uint32_t __ymd; + uint64_t __hmsm; if (!ymd || !hmsm) return OPAL_PARAMETER; @@ -185,7 +187,10 @@ static int64_t mambo_rtc_read(uint32_t *ymd, uint64_t *hmsm) mambo_time = callthru0(SIM_GET_TIME_CODE); mt = mambo_time >> 32; gmtime_r(&mt, &t); - tm_to_datetime(&t, ymd, hmsm); + tm_to_datetime(&t, &__ymd, &__hmsm); + + *ymd = cpu_to_be32(__ymd); + *hmsm = cpu_to_be64(__hmsm); return OPAL_SUCCESS; } From patchwork Wed Nov 6 12:10:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QSr1xxpz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:31 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:24 +1000 Message-Id: <20191106121047.14389-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 06/29] elf: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/flash.c | 36 +++++--- core/init.c | 92 ++++++++++--------- include/elf.h | 235 +++++++++++++++++++++++++++++++++--------------- include/stack.h | 4 + 4 files changed, 244 insertions(+), 123 deletions(-) diff --git a/core/flash.c b/core/flash.c index 7fbfca22b..5fc3f3946 100644 --- a/core/flash.c +++ b/core/flash.c @@ -520,24 +520,38 @@ const char *flash_map_resource_name(enum resource_id id) static size_t sizeof_elf_from_hdr(void *buf) { - struct elf_hdr *elf = (struct elf_hdr*) buf; + struct elf_hdr *elf = (struct elf_hdr *)buf; size_t sz = 0; BUILD_ASSERT(SECURE_BOOT_HEADERS_SIZE > sizeof(struct elf_hdr)); - BUILD_ASSERT(SECURE_BOOT_HEADERS_SIZE > sizeof(struct elf64_hdr)); - BUILD_ASSERT(SECURE_BOOT_HEADERS_SIZE > sizeof(struct elf32_hdr)); + BUILD_ASSERT(SECURE_BOOT_HEADERS_SIZE > sizeof(struct elf64be_hdr)); + BUILD_ASSERT(SECURE_BOOT_HEADERS_SIZE > sizeof(struct elf32be_hdr)); if (elf->ei_ident == ELF_IDENT) { if (elf->ei_class == ELF_CLASS_64) { - struct elf64_hdr *elf64 = (struct elf64_hdr*) buf; - sz = le64_to_cpu(elf64->e_shoff) + - ((uint32_t)le16_to_cpu(elf64->e_shentsize) * - (uint32_t)le16_to_cpu(elf64->e_shnum)); + if (elf->ei_data == ELF_DATA_LSB) { + struct elf64le_hdr *kh = (struct elf64le_hdr *)buf; + sz = le64_to_cpu(kh->e_shoff) + + ((uint32_t)le16_to_cpu(kh->e_shentsize) * + (uint32_t)le16_to_cpu(kh->e_shnum)); + } else { + struct elf64be_hdr *kh = (struct elf64be_hdr *)buf; + sz = be64_to_cpu(kh->e_shoff) + + ((uint32_t)be16_to_cpu(kh->e_shentsize) * + (uint32_t)be16_to_cpu(kh->e_shnum)); + } } else if (elf->ei_class == ELF_CLASS_32) { - struct elf32_hdr *elf32 = (struct elf32_hdr*) buf; - sz = le32_to_cpu(elf32->e_shoff) + - (le16_to_cpu(elf32->e_shentsize) * - le16_to_cpu(elf32->e_shnum)); + if (elf->ei_data == ELF_DATA_LSB) { + struct elf32le_hdr *kh = (struct elf32le_hdr *)buf; + sz = le32_to_cpu(kh->e_shoff) + + (le16_to_cpu(kh->e_shentsize) * + le16_to_cpu(kh->e_shnum)); + } else { + struct elf32be_hdr *kh = (struct elf32be_hdr *)buf; + sz = be32_to_cpu(kh->e_shoff) + + (be16_to_cpu(kh->e_shentsize) * + be16_to_cpu(kh->e_shnum)); + } } } diff --git a/core/init.c b/core/init.c index cc1fdbc4d..26d3e016f 100644 --- a/core/init.c +++ b/core/init.c @@ -89,9 +89,9 @@ static void checksum_romem(void); static bool try_load_elf64_le(struct elf_hdr *header) { - struct elf64_hdr *kh = (struct elf64_hdr *)header; + struct elf64le_hdr *kh = (struct elf64le_hdr *)header; uint64_t load_base = (uint64_t)kh; - struct elf64_phdr *ph; + struct elf64le_phdr *ph; unsigned int i; printf("INIT: 64-bit LE kernel discovered\n"); @@ -103,7 +103,7 @@ static bool try_load_elf64_le(struct elf_hdr *header) * to work for the Linux Kernel because it's a fairly dumb ELF * but it will not work for any ELF binary. */ - ph = (struct elf64_phdr *)(load_base + le64_to_cpu(kh->e_phoff)); + ph = (struct elf64le_phdr *)(load_base + le64_to_cpu(kh->e_phoff)); for (i = 0; i < le16_to_cpu(kh->e_phnum); i++, ph++) { if (le32_to_cpu(ph->p_type) != ELF_PTYPE_LOAD) continue; @@ -137,23 +137,24 @@ static bool try_load_elf64_le(struct elf_hdr *header) static bool try_load_elf64(struct elf_hdr *header) { - struct elf64_hdr *kh = (struct elf64_hdr *)header; + struct elf64be_hdr *kh = (struct elf64be_hdr *)header; + struct elf64le_hdr *khle = (struct elf64le_hdr *)header; uint64_t load_base = (uint64_t)kh; - struct elf64_phdr *ph; - struct elf64_shdr *sh; + struct elf64be_phdr *ph; + struct elf64be_shdr *sh; unsigned int i; /* Check it's a ppc64 LE ELF */ - if (kh->ei_ident == ELF_IDENT && - kh->ei_data == ELF_DATA_LSB && - kh->e_machine == le16_to_cpu(ELF_MACH_PPC64)) { + if (khle->ei_ident == ELF_IDENT && + khle->ei_data == ELF_DATA_LSB && + le16_to_cpu(khle->e_machine) == ELF_MACH_PPC64) { return try_load_elf64_le(header); } /* Check it's a ppc64 ELF */ if (kh->ei_ident != ELF_IDENT || kh->ei_data != ELF_DATA_MSB || - kh->e_machine != ELF_MACH_PPC64) { + be16_to_cpu(kh->e_machine) != ELF_MACH_PPC64) { prerror("INIT: Kernel doesn't look like an ppc64 ELF\n"); return false; } @@ -165,16 +166,18 @@ static bool try_load_elf64(struct elf_hdr *header) * to work for the Linux Kernel because it's a fairly dumb ELF * but it will not work for any ELF binary. */ - ph = (struct elf64_phdr *)(load_base + kh->e_phoff); - for (i = 0; i < kh->e_phnum; i++, ph++) { - if (ph->p_type != ELF_PTYPE_LOAD) + ph = (struct elf64be_phdr *)(load_base + be64_to_cpu(kh->e_phoff)); + for (i = 0; i < be16_to_cpu(kh->e_phnum); i++, ph++) { + if (be32_to_cpu(ph->p_type) != ELF_PTYPE_LOAD) continue; - if (ph->p_vaddr > kh->e_entry || - (ph->p_vaddr + ph->p_memsz) < kh->e_entry) + if (be64_to_cpu(ph->p_vaddr) > be64_to_cpu(kh->e_entry) || + (be64_to_cpu(ph->p_vaddr) + be64_to_cpu(ph->p_memsz)) < + be64_to_cpu(kh->e_entry)) continue; /* Get our entry */ - kernel_entry = kh->e_entry - ph->p_vaddr + ph->p_offset; + kernel_entry = be64_to_cpu(kh->e_entry) - + be64_to_cpu(ph->p_vaddr) + be64_to_cpu(ph->p_offset); break; } @@ -189,23 +192,27 @@ static bool try_load_elf64(struct elf_hdr *header) * into an executable section or not to figure this out. Default * to assuming it obeys the ABI. */ - sh = (struct elf64_shdr *)(load_base + kh->e_shoff); - for (i = 0; i < kh->e_shnum; i++, sh++) { - if (sh->sh_addr <= kh->e_entry && - (sh->sh_addr + sh->sh_size) > kh->e_entry) + sh = (struct elf64be_shdr *)(load_base + be64_to_cpu(kh->e_shoff)); + for (i = 0; i < be16_to_cpu(kh->e_shnum); i++, sh++) { + if (be64_to_cpu(sh->sh_addr) <= be64_to_cpu(kh->e_entry) && + (be64_to_cpu(sh->sh_addr) + be64_to_cpu(sh->sh_size)) > + be64_to_cpu(kh->e_entry)) break; } - if (i == kh->e_shnum || !(sh->sh_flags & ELF_SFLAGS_X)) { + if (i == be16_to_cpu(kh->e_shnum) || + !(be64_to_cpu(sh->sh_flags) & ELF_SFLAGS_X)) { kernel_entry = *(uint64_t *)(kernel_entry + load_base); - kernel_entry = kernel_entry - ph->p_vaddr + ph->p_offset; + kernel_entry = kernel_entry - + be64_to_cpu(ph->p_vaddr) + be64_to_cpu(ph->p_offset); } kernel_entry += load_base; kernel_32bit = false; - kernel_size = kh->e_shoff + - ((uint32_t)kh->e_shentsize * (uint32_t)kh->e_shnum); + kernel_size = be64_to_cpu(kh->e_shoff) + + ((uint32_t)be16_to_cpu(kh->e_shentsize) * + (uint32_t)be16_to_cpu(kh->e_shnum)); printf("INIT: 64-bit kernel entry at 0x%llx, size 0x%lx\n", kernel_entry, kernel_size); @@ -215,9 +222,9 @@ static bool try_load_elf64(struct elf_hdr *header) static bool try_load_elf32_le(struct elf_hdr *header) { - struct elf32_hdr *kh = (struct elf32_hdr *)header; + struct elf32le_hdr *kh = (struct elf32le_hdr *)header; uint64_t load_base = (uint64_t)kh; - struct elf32_phdr *ph; + struct elf32le_phdr *ph; unsigned int i; printf("INIT: 32-bit LE kernel discovered\n"); @@ -229,7 +236,7 @@ static bool try_load_elf32_le(struct elf_hdr *header) * to work for the Linux Kernel because it's a fairly dumb ELF * but it will not work for any ELF binary. */ - ph = (struct elf32_phdr *)(load_base + le32_to_cpu(kh->e_phoff)); + ph = (struct elf32le_phdr *)(load_base + le32_to_cpu(kh->e_phoff)); for (i = 0; i < le16_to_cpu(kh->e_phnum); i++, ph++) { if (le32_to_cpu(ph->p_type) != ELF_PTYPE_LOAD) continue; @@ -259,22 +266,23 @@ static bool try_load_elf32_le(struct elf_hdr *header) static bool try_load_elf32(struct elf_hdr *header) { - struct elf32_hdr *kh = (struct elf32_hdr *)header; + struct elf32be_hdr *kh = (struct elf32be_hdr *)header; + struct elf32le_hdr *khle = (struct elf32le_hdr *)header; uint64_t load_base = (uint64_t)kh; - struct elf32_phdr *ph; + struct elf32be_phdr *ph; unsigned int i; /* Check it's a ppc32 LE ELF */ - if (header->ei_ident == ELF_IDENT && - header->ei_data == ELF_DATA_LSB && - header->e_machine == le16_to_cpu(ELF_MACH_PPC32)) { + if (khle->ei_ident == ELF_IDENT && + khle->ei_data == ELF_DATA_LSB && + le16_to_cpu(khle->e_machine) == ELF_MACH_PPC32) { return try_load_elf32_le(header); } /* Check it's a ppc32 ELF */ - if (header->ei_ident != ELF_IDENT || - header->ei_data != ELF_DATA_MSB || - header->e_machine != ELF_MACH_PPC32) { + if (kh->ei_ident != ELF_IDENT || + kh->ei_data != ELF_DATA_MSB || + be16_to_cpu(kh->e_machine) != ELF_MACH_PPC32) { prerror("INIT: Kernel doesn't look like an ppc32 ELF\n"); return false; } @@ -286,16 +294,18 @@ static bool try_load_elf32(struct elf_hdr *header) * to work for the Linux Kernel because it's a fairly dumb ELF * but it will not work for any ELF binary. */ - ph = (struct elf32_phdr *)(load_base + kh->e_phoff); - for (i = 0; i < kh->e_phnum; i++, ph++) { - if (ph->p_type != ELF_PTYPE_LOAD) + ph = (struct elf32be_phdr *)(load_base + be32_to_cpu(kh->e_phoff)); + for (i = 0; i < be16_to_cpu(kh->e_phnum); i++, ph++) { + if (be32_to_cpu(ph->p_type) != ELF_PTYPE_LOAD) continue; - if (ph->p_vaddr > kh->e_entry || - (ph->p_vaddr + ph->p_memsz) < kh->e_entry) + if (be32_to_cpu(ph->p_vaddr) > be32_to_cpu(kh->e_entry) || + (be32_to_cpu(ph->p_vaddr) + be32_to_cpu(ph->p_memsz)) < + be32_to_cpu(kh->e_entry)) continue; /* Get our entry */ - kernel_entry = kh->e_entry - ph->p_vaddr + ph->p_offset; + kernel_entry = be32_to_cpu(kh->e_entry) - + be32_to_cpu(ph->p_vaddr) + be32_to_cpu(ph->p_offset); break; } diff --git a/include/elf.h b/include/elf.h index 93524bb99..f3e071de1 100644 --- a/include/elf.h +++ b/include/elf.h @@ -5,11 +5,16 @@ #define __ELF_H #include +#include /* Generic ELF header */ struct elf_hdr { uint32_t ei_ident; +#if HAVE_BIG_ENDIAN #define ELF_IDENT 0x7F454C46 +#else +#define ELF_IDENT 0x464C457F +#endif uint8_t ei_class; #define ELF_CLASS_32 1 #define ELF_CLASS_64 2 @@ -18,68 +23,190 @@ struct elf_hdr { #define ELF_DATA_MSB 2 uint8_t ei_version; uint8_t ei_pad[9]; - uint16_t e_type; - uint16_t e_machine; +}; + #define ELF_MACH_PPC32 0x14 #define ELF_MACH_PPC64 0x15 - uint32_t e_version; + +/* 64-bit ELF header */ +struct elf64be_hdr { + uint32_t ei_ident; + uint8_t ei_class; + uint8_t ei_data; + uint8_t ei_version; + uint8_t ei_pad[9]; + __be16 e_type; + __be16 e_machine; + __be32 e_version; + __be64 e_entry; + __be64 e_phoff; + __be64 e_shoff; + __be32 e_flags; + __be16 e_ehsize; + __be16 e_phentsize; + __be16 e_phnum; + __be16 e_shentsize; + __be16 e_shnum; + __be16 e_shstrndx; +}; + +/* 64-bit ELF program header */ +struct elf64be_phdr { + __be32 p_type; +#define ELF_PTYPE_LOAD 1 + __be32 p_flags; +#define ELF_PFLAGS_R 0x4 +#define ELF_PFLAGS_W 0x2 +#define ELF_PFLAGS_X 0x1 + __be64 p_offset; + __be64 p_vaddr; + __be64 p_paddr; + __be64 p_filesz; + __be64 p_memsz; + __be64 p_align; +}; + +/* 64-bit ELF section header */ +struct elf64be_shdr { + __be32 sh_name; + __be32 sh_type; + __be64 sh_flags; +#define ELF_SFLAGS_X 0x4 +#define ELF_SFLAGS_A 0x2 +#define ELF_SFLAGS_W 0x1 + __be64 sh_addr; + __be64 sh_offset; + __be64 sh_size; + __be32 sh_link; + __be32 sh_info; + __be64 sh_addralign; + __be64 sh_entsize; +}; + +/* 32-bit ELF header */ +struct elf32be_hdr { + uint32_t ei_ident; + uint8_t ei_class; + uint8_t ei_data; + uint8_t ei_version; + uint8_t ei_pad[9]; + __be16 e_type; + __be16 e_machine; + __be32 e_version; + __be32 e_entry; + __be32 e_phoff; + __be32 e_shoff; + __be32 e_flags; + __be16 e_ehsize; + __be16 e_phentsize; + __be16 e_phnum; + __be16 e_shentsize; + __be16 e_shnum; + __be16 e_shstrndx; +}; + +/* 32-bit ELF program header*/ +struct elf32be_phdr { + __be32 p_type; + __be32 p_offset; + __be32 p_vaddr; + __be32 p_paddr; + __be32 p_filesz; + __be32 p_memsz; + __be32 p_flags; + __be32 p_align; }; /* 64-bit ELF header */ -struct elf64_hdr { +struct elf64le_hdr { uint32_t ei_ident; uint8_t ei_class; uint8_t ei_data; uint8_t ei_version; uint8_t ei_pad[9]; - uint16_t e_type; - uint16_t e_machine; - uint32_t e_version; - uint64_t e_entry; - uint64_t e_phoff; - uint64_t e_shoff; - uint32_t e_flags; - uint16_t e_ehsize; - uint16_t e_phentsize; - uint16_t e_phnum; - uint16_t e_shentsize; - uint16_t e_shnum; - uint16_t e_shstrndx; + __le16 e_type; + __le16 e_machine; + __le32 e_version; + __le64 e_entry; + __le64 e_phoff; + __le64 e_shoff; + __le32 e_flags; + __le16 e_ehsize; + __le16 e_phentsize; + __le16 e_phnum; + __le16 e_shentsize; + __le16 e_shnum; + __le16 e_shstrndx; }; /* 64-bit ELF program header */ -struct elf64_phdr { - uint32_t p_type; +struct elf64le_phdr { + __le32 p_type; #define ELF_PTYPE_LOAD 1 - uint32_t p_flags; + __le32 p_flags; #define ELF_PFLAGS_R 0x4 #define ELF_PFLAGS_W 0x2 #define ELF_PFLAGS_X 0x1 - uint64_t p_offset; - uint64_t p_vaddr; - uint64_t p_paddr; - uint64_t p_filesz; - uint64_t p_memsz; - uint64_t p_align; + __le64 p_offset; + __le64 p_vaddr; + __le64 p_paddr; + __le64 p_filesz; + __le64 p_memsz; + __le64 p_align; }; /* 64-bit ELF section header */ -struct elf64_shdr { - uint32_t sh_name; - uint32_t sh_type; - uint64_t sh_flags; +struct elf64le_shdr { + __le32 sh_name; + __le32 sh_type; + __le64 sh_flags; #define ELF_SFLAGS_X 0x4 #define ELF_SFLAGS_A 0x2 #define ELF_SFLAGS_W 0x1 - uint64_t sh_addr; - uint64_t sh_offset; - uint64_t sh_size; - uint32_t sh_link; - uint32_t sh_info; - uint64_t sh_addralign; - int64_t sh_entsize; + __le64 sh_addr; + __le64 sh_offset; + __le64 sh_size; + __le32 sh_link; + __le32 sh_info; + __le64 sh_addralign; + __le64 sh_entsize; +}; + +/* 32-bit ELF header */ +struct elf32le_hdr { + uint32_t ei_ident; + uint8_t ei_class; + uint8_t ei_data; + uint8_t ei_version; + uint8_t ei_pad[9]; + __le16 e_type; + __le16 e_machine; + __le32 e_version; + __le32 e_entry; + __le32 e_phoff; + __le32 e_shoff; + __le32 e_flags; + __le16 e_ehsize; + __le16 e_phentsize; + __le16 e_phnum; + __le16 e_shentsize; + __le16 e_shnum; + __le16 e_shstrndx; +}; + +/* 32-bit ELF program header*/ +struct elf32le_phdr { + __le32 p_type; + __le32 p_offset; + __le32 p_vaddr; + __le32 p_paddr; + __le32 p_filesz; + __le32 p_memsz; + __le32 p_flags; + __le32 p_align; }; + /* Some relocation related stuff used in relocate.c */ struct elf64_dyn { int64_t d_tag; @@ -101,39 +228,5 @@ struct elf64_rela { /* relocs we support */ #define R_PPC64_RELATIVE 22 -/* 32-bit ELF header */ -struct elf32_hdr { - uint32_t ei_ident; - uint8_t ei_class; - uint8_t ei_data; - uint8_t ei_version; - uint8_t ei_pad[9]; - uint16_t e_type; - uint16_t e_machine; - uint32_t e_version; - uint32_t e_entry; - uint32_t e_phoff; - uint32_t e_shoff; - uint32_t e_flags; - uint16_t e_ehsize; - uint16_t e_phentsize; - uint16_t e_phnum; - uint16_t e_shentsize; - uint16_t e_shnum; - uint16_t e_shstrndx; -}; - -/* 32-bit ELF program header*/ -struct elf32_phdr { - uint32_t p_type; - uint32_t p_offset; - uint32_t p_vaddr; - uint32_t p_paddr; - uint32_t p_filesz; - uint32_t p_memsz; - uint32_t p_flags; - uint32_t p_align; -}; - #endif /* __ELF_H */ diff --git a/include/stack.h b/include/stack.h index 09d22adb6..b0d6df17d 100644 --- a/include/stack.h +++ b/include/stack.h @@ -11,7 +11,11 @@ #define STACK_ENTRY_RESET 0x0100 /* System reset */ #define STACK_ENTRY_SOFTPATCH 0x1500 /* Soft patch (denorm emulation) */ +#if HAVE_BIG_ENDIAN #define STACK_TOC_OFFSET 40 +#else +#define STACK_TOC_OFFSET 24 +#endif /* Safety/ABI gap at top of stack */ #define STACK_TOP_GAP 0x100 From patchwork Wed Nov 6 12:10:25 2019 Content-Type: text/plain; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:34 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:25 +1000 Message-Id: <20191106121047.14389-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 07/29] spira: fix endian conversions in spira data structures X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Labels can't be used for static initialisers that require endian conversion. Use constants for these. Signed-off-by: Nicholas Piggin --- hdata/spira.c | 55 ++++++++++++++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/hdata/spira.c b/hdata/spira.c index 5e73b7d44..f1ce25dff 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -33,41 +33,61 @@ __section(".procin.data") struct proc_init_data proc_init_data = { .regs_ptr = HDIF_IDATA_PTR(offsetof(struct proc_init_data, regs), 0x10), .regs = { .nia = CPU_TO_BE64(0x180), - .msr = CPU_TO_BE64(0x9000000000000000ULL), /* SF | HV */ + .msr = CPU_TO_BE64(MSR_SF | MSR_HV), }, }; +extern struct cpu_ctl_init_data cpu_ctl_init_data; extern struct sp_addr_table cpu_ctl_spat_area; -__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area; -__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1; -__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2; +extern struct sp_attn_area cpu_ctl_sp_attn_area1; +extern struct sp_attn_area cpu_ctl_sp_attn_area2; extern struct hsr_data_area cpu_ctl_hsr_area; + +/* + * cpuctrl.data begins at CPU_CTL_OFF - cpu_ctl_init_data is located there. + * + sizeof(struct cpu_ctl_init_data) - cpu_ctl_spat_area + * + sizeof(struct sp_addr_table) - cpu_ctl_sp_attn_area1 + * + sizeof(struct sp_attn_area) - cpu_ctl_sp_attn_area2 + * + sizeof(struct sp_attn_area) - cpu_ctl_hsr_area + * + * Can't use CPU_TO_BE64 directly on the labels as a constant initialiser. + * + * CPU_CTL_INIT_DATA_OFF is offset from 0, the others are addressed from the + * relocated address (+SKIBOOT_BASE) + */ +#define CPU_CTL_INIT_DATA_OFF (CPU_CTL_OFF) +#define CPU_CTL_SPAT_AREA_OFF (CPU_CTL_INIT_DATA_OFF + sizeof(struct cpu_ctl_init_data) + SKIBOOT_BASE) +#define CPU_CTL_SP_ATTN_AREA1_OFF (CPU_CTL_SPAT_AREA_OFF + sizeof(struct sp_addr_table)) +#define CPU_CTL_SP_ATTN_AREA2_OFF (CPU_CTL_SP_ATTN_AREA1_OFF + sizeof(struct sp_attn_area)) +#define CPU_CTL_HSR_AREA_OFF (CPU_CTL_SP_ATTN_AREA2_OFF + sizeof(struct sp_attn_area)) + __section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1; +__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area; -extern struct cpu_ctl_init_data cpu_ctl_init_data; __section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = { .hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data), - .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), sizeof(struct cpu_ctl_legacy_table)), -#if !defined(TEST) + .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), + sizeof(struct cpu_ctl_legacy_table)), .cpu_ctl_lt = { .spat = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_spat_area) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SPAT_AREA_OFF), .size = CPU_TO_BE64(sizeof(struct sp_addr_table)), }, .sp_attn_area1 = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area1) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA1_OFF), .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), }, .sp_attn_area2 = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area2) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA2_OFF), .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), }, .hsr_area = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_hsr_area) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_HSR_AREA_OFF), .size = CPU_TO_BE64(sizeof(struct hsr_data_area)), }, }, -#endif }; /* Populate MDST table @@ -131,15 +151,12 @@ __section(".spira.data") struct spira spira = { .alloc_len = CPU_TO_BE32(sizeof(init_mdst_table)), }, -#if !defined(TEST) .cpu_ctrl = { - .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data), + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), .alloc_cnt = CPU_TO_BE16(1), .act_cnt = CPU_TO_BE16(1), - .alloc_len = - CPU_TO_BE32(sizeof(cpu_ctl_init_data)), + .alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)), }, -#endif }, }; @@ -170,15 +187,13 @@ __section(".spirah.data") struct spirah spirah = { .alloc_len = CPU_TO_BE32(sizeof(struct proc_init_data)), }, -#if !defined(TEST) .cpu_ctrl = { - .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data), + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), .alloc_cnt = CPU_TO_BE16(1), .act_cnt = CPU_TO_BE16(1), .alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)), }, -#endif .mdump_src = { .addr = CPU_TO_BE64(MDST_TABLE_OFF), .alloc_cnt = CPU_TO_BE16(MDST_TABLE_SIZE / sizeof(struct mdst_table)), From patchwork Wed Nov 6 12:10:26 2019 Content-Type: text/plain; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:36 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:26 +1000 Message-Id: <20191106121047.14389-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 08/29] hdata: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin Reviewed-by: Vasant Hegde --- hdata/memory.c | 3 ++- hdata/spira.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index 9af7ae71d..9e5e99b9c 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -135,7 +135,8 @@ static bool add_address_range(struct dt_node *root, "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", (long long)be64_to_cpu(arange->start), (long long)be64_to_cpu(arange->end), - chip_id, arange->mirror_attr, mem_type, mem_status); + chip_id, be32_to_cpu(arange->mirror_attr), + mem_type, mem_status); /* reg contains start and length */ reg[0] = cleanup_addr(be64_to_cpu(arange->start)); diff --git a/hdata/spira.c b/hdata/spira.c index f1ce25dff..661349fed 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -952,7 +952,7 @@ static void dt_init_secureboot_node(const struct iplparams_sysparams *sysparams) static void opal_dump_add_mpipl_boot(const struct iplparams_iplparams *p) { - u32 mdrt_cnt = spira.ntuples.mdump_res.act_cnt; + u32 mdrt_cnt = be16_to_cpu(spira.ntuples.mdump_res.act_cnt); u32 mdrt_max_cnt = MDRT_TABLE_SIZE / sizeof(struct mdrt_table); struct dt_node *dump_node; @@ -975,7 +975,7 @@ static void opal_dump_add_mpipl_boot(const struct iplparams_iplparams *p) return; } - if (p->cec_ipl_attrib != IPLPARAMS_ATTRIB_MEM_PRESERVE) { + if (be16_to_cpu(p->cec_ipl_attrib) != IPLPARAMS_ATTRIB_MEM_PRESERVE) { prlog(PR_DEBUG, "DUMP: Memory not preserved\n"); return; } @@ -1663,7 +1663,7 @@ static void add_npus(void) static void fixup_spira(void) { #if !defined(TEST) - spiras = (struct spiras *)CPU_TO_BE64(SPIRA_HEAP_BASE); + spiras = (struct spiras *)SPIRA_HEAP_BASE; #endif /* Validate SPIRA-S signature */ From patchwork Wed Nov 6 12:10:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190351 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QV41Wjfz9sP3 for ; Wed, 6 Nov 2019 23:15:40 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DQ62RgCG"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477QV35hBszF63J for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:38 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:27 +1000 Message-Id: <20191106121047.14389-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 09/29] naca: move naca definition from asm to C X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This results in the same layout and location of the naca and hv data structures. Signed-off-by: Nicholas Piggin --- asm/asm-offsets.c | 2 -- asm/head.S | 50 ------------------------------------------ hdata/Makefile.inc | 2 +- hdata/hdata.h | 2 ++ hdata/naca.c | 26 ++++++++++++++++++++++ hdata/naca.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++ hdata/spira.c | 11 ++++------ hdata/spira.h | 2 ++ include/mem-map.h | 2 ++ skiboot.lds.S | 5 +++++ 10 files changed, 96 insertions(+), 60 deletions(-) create mode 100644 hdata/naca.c create mode 100644 hdata/naca.h diff --git a/asm/asm-offsets.c b/asm/asm-offsets.c index e4584059c..61a25cab3 100644 --- a/asm/asm-offsets.c +++ b/asm/asm-offsets.c @@ -25,8 +25,6 @@ int main(void); int main(void) { - OFFSET(SPIRA_ACTUAL_SIZE, spira, reserved); - OFFSET(CPUTHREAD_PIR, cpu_thread, pir); OFFSET(CPUTHREAD_SAVE_R1, cpu_thread, save_r1); OFFSET(CPUTHREAD_STATE, cpu_thread, state); diff --git a/asm/head.S b/asm/head.S index 426b5d5c1..7ce3c7c97 100644 --- a/asm/head.S +++ b/asm/head.S @@ -806,56 +806,6 @@ enter_nap: bne 1b nap b . -/* - * - * NACA structure, accessed by the FPS to find the SPIRA - * - */ - . = 0x4000 -.global naca -naca: - .llong spirah /* 0x0000 : SPIRA-H */ - .llong 0 /* 0x0008 : Reserved */ - .llong 0 /* 0x0010 : Reserved */ - .llong hv_release_data /* 0x0018 : HV release data */ - .llong 0 /* 0x0020 : Reserved */ - .llong 0 /* 0x0028 : Reserved */ - .llong spira /* 0x0030 : SP Interface Root */ - .llong hv_lid_load_table /* 0x0038 : LID load table */ - .llong 0 /* 0x0040 : Reserved */ - .space 68 - .long 0 /* 0x008c : Reserved */ - .space 16 - .long SPIRA_ACTUAL_SIZE /* 0x00a0 : Actual size of SPIRA */ - .space 28 - .llong 0 /* 0x00c0 : resident module loadmap */ - .space 136 - .llong 0 /* 0x0150 : reserved */ - .space 40 - .llong 0 /* 0x0180 : reserved */ - .space 36 - .long 0 /* 0x01ac : control flags */ - .byte 0 /* 0x01b0 : reserved */ - .space 4 - .byte 0 /* 0x01b5 : default state for SW attn */ - .space 1 - .byte 0x01 /* 0x01b7 : PCIA format */ - .llong hdat_entry /* 0x01b8 : Primary thread entry */ - .llong hdat_entry /* 0x01c0 : Secondary thread entry */ - .space 0xe38 - - .balign 0x10 -hv_release_data: - .space 58 - .llong 0x666 /* VRM ? */ - - .balign 0x10 -hv_lid_load_table: - .long 0x10 - .long 0x10 - .long 0 - .long 0 - /* * diff --git a/hdata/Makefile.inc b/hdata/Makefile.inc index 6f47314d4..67f809bc1 100644 --- a/hdata/Makefile.inc +++ b/hdata/Makefile.inc @@ -1,7 +1,7 @@ # -*-Makefile-*- SUBDIRS += hdata -HDATA_OBJS = spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o +HDATA_OBJS = naca.o spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o HDATA_OBJS += cpu-common.o vpd-common.o hostservices.o i2c.o tpmrel.o DEVSRC_OBJ = hdata/built-in.a diff --git a/hdata/hdata.h b/hdata/hdata.h index f77847172..da5146e7a 100644 --- a/hdata/hdata.h +++ b/hdata/hdata.h @@ -5,6 +5,8 @@ #define __HDATA_H #include +#include "hdif.h" +#include "spira.h" struct dt_node; diff --git a/hdata/naca.c b/hdata/naca.c new file mode 100644 index 000000000..b215c39eb --- /dev/null +++ b/hdata/naca.c @@ -0,0 +1,26 @@ +#include +#include +#include + +#include "naca.h" +#include "spira.h" + +__section(".naca.data") struct naca naca = { + .spirah_addr = CPU_TO_BE64(SPIRAH_OFF), + .hv_release_data_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_release_data)), + .spira_addr = CPU_TO_BE64(SPIRA_OFF), + .lid_table_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_lid_load_table)), + .spira_size = CPU_TO_BE32(SPIRA_ACTUAL_SIZE), + .hv_load_map_addr = 0, + .attn_enabled = 0, + .pcia_supported = 1, + .__primary_thread_entry = CPU_TO_BE64(0x180), + .__secondary_thread_entry = CPU_TO_BE64(0x180), + .hv_release_data = { + .vrm = CPU_TO_BE64(0x666), /* ? */ + }, + .hv_lid_load_table = { + .w0 = CPU_TO_BE32(0x10), + .w1 = CPU_TO_BE32(0x10), + }, +}; diff --git a/hdata/naca.h b/hdata/naca.h new file mode 100644 index 000000000..1271b59a5 --- /dev/null +++ b/hdata/naca.h @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2019 IBM Corp. */ + +#ifndef __NACA_H +#define __NACA_H + +#include +#include +#include + +struct hv_release_data { + uint8_t reserved_0x0[58]; + __be64 vrm; +} __packed __attribute__((aligned(0x10))); + +struct hv_lid_load_table { + __be32 w0; + __be32 w1; + __be32 w2; + __be32 w3; +} __packed __attribute__((aligned(0x10))); + +/* + * NACA structure, accessed by the FSP to find the SPIRA + */ +struct naca { + __be64 spirah_addr; /* 0x0000 */ + uint8_t reserved_0x8[0x10]; + __be64 hv_release_data_addr; /* 0x0018 */ + uint8_t reserved_0x20[0x10]; + __be64 spira_addr; /* 0x0030 */ + __be64 lid_table_addr; /* 0x0038 */ + uint8_t reserved_0x40[0x60]; + __be32 spira_size; /* 0x00a0 */ + uint8_t reserved_0xa4[0x1c]; + __be64 hv_load_map_addr; /* 0x00c0 */ + uint8_t reserved_0xc8[0xe4]; + uint8_t flags[4]; /* 0x01ac */ + uint8_t reserved_0x1b0[0x5]; + uint8_t attn_enabled; /* 0x01b5 */ + uint8_t reserved_0x1b6[0x1]; + uint8_t pcia_supported; /* 0x01b7 */ + __be64 __primary_thread_entry; /* 0x01b8 */ + __be64 __secondary_thread_entry; /* 0x01c0 */ + uint8_t reserved_0x1d0[0xe38]; + + /* Not part of the naca but it's convenient to put them here */ + struct hv_release_data hv_release_data; + struct hv_lid_load_table hv_lid_load_table; +} __packed __attribute((aligned(0x10))); + +extern struct naca naca; + +#endif diff --git a/hdata/spira.c b/hdata/spira.c index 661349fed..6900b71e8 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -3,7 +3,6 @@ #include #include -#include "spira.h" #include #include #include @@ -15,6 +14,8 @@ #include "hdata.h" #include "hostservices.h" +#include "naca.h" +#include "spira.h" /* Processor Initialization structure, contains * the initial NIA and MSR values for the entry @@ -1706,15 +1707,11 @@ static void fixup_spira(void) static void update_spirah_addr(void) { #if !defined(TEST) - extern uint32_t naca; - uint64_t *spirah_offset = (uint64_t *)&naca; - uint64_t *spira_offset = (uint64_t *)((u64)(&naca) + 0x30); - if (proc_gen < proc_gen_p9) return; - *spirah_offset = SPIRAH_OFF; - *spira_offset = SPIRA_OFF; + naca.spirah_addr = CPU_TO_BE64(SPIRAH_OFF); + naca.spira_addr = CPU_TO_BE64(SPIRA_OFF); spirah.ntuples.hs_data_area.addr = CPU_TO_BE64(SPIRA_HEAP_BASE - SKIBOOT_BASE); spirah.ntuples.mdump_res.addr = CPU_TO_BE64(MDRT_TABLE_BASE - SKIBOOT_BASE); #endif diff --git a/hdata/spira.h b/hdata/spira.h index eb5d1ea1b..14fbc5f59 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -80,6 +80,8 @@ struct spira { u8 reserved[0x60]; } __packed __align(0x100); +#define SPIRA_ACTUAL_SIZE (sizeof(struct spira) - 0x60) + extern struct spira spira; /* SPIRA-H signature */ diff --git a/include/mem-map.h b/include/mem-map.h index 991465190..90529df22 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -21,6 +21,8 @@ */ #define EXCEPTION_VECTORS_END 0x2000 +#define NACA_OFF 0x4000 + /* The NACA and other stuff in head.S need to be at the start: we * give it 64k before placing the SPIRA and related data. */ diff --git a/skiboot.lds.S b/skiboot.lds.S index 32139b2c5..12981f3c8 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -59,6 +59,11 @@ SECTIONS KEEP(*(.head)) } + . = NACA_OFF; + .naca : { + KEEP(*(.naca.data)) + } + . = SPIRA_OFF; .spira : { KEEP(*(.spira.data)) From patchwork Wed Nov 6 12:10:28 2019 Content-Type: text/plain; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:41 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:28 +1000 Message-Id: <20191106121047.14389-11-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 10/29] io: endian conversions for io accessors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This requires a small change to flash drivers which assumed 4-byte LPC reads would not change endian. _raw accessors could be added if this becomes a signifcant pattern, but for now this hack works. Signed-off-by: Nicholas Piggin --- include/io.h | 79 ++++++++++++++++++++++++++++++++++-------- include/types.h | 4 +++ libflash/ipmi-hiomap.c | 20 +++++++---- libflash/mbox-flash.c | 20 +++++++---- 4 files changed, 96 insertions(+), 27 deletions(-) diff --git a/include/io.h b/include/io.h index c6203a274..57dddd49f 100644 --- a/include/io.h +++ b/include/io.h @@ -9,6 +9,7 @@ #include #include #include +#include #include /* @@ -35,10 +36,10 @@ static inline uint8_t in_8(const volatile uint8_t *addr) static inline uint16_t __in_be16(const volatile uint16_t *addr) { - uint16_t val; + __be16 val; asm volatile("lhzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be16_to_cpu(val); } static inline uint16_t in_be16(const volatile uint16_t *addr) @@ -47,17 +48,26 @@ static inline uint16_t in_be16(const volatile uint16_t *addr) return __in_be16(addr); } +static inline uint16_t __in_le16(const volatile uint16_t *addr) +{ + __le16 val; + asm volatile("lhzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le16_to_cpu(val); +} + static inline uint16_t in_le16(const volatile uint16_t *addr) { - return bswap_16(in_be16(addr)); + sync(); + return __in_le16(addr); } static inline uint32_t __in_be32(const volatile uint32_t *addr) { - uint32_t val; + __be32 val; asm volatile("lwzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be32_to_cpu(val); } static inline uint32_t in_be32(const volatile uint32_t *addr) @@ -66,17 +76,26 @@ static inline uint32_t in_be32(const volatile uint32_t *addr) return __in_be32(addr); } +static inline uint32_t __in_le32(const volatile uint32_t *addr) +{ + __le32 val; + asm volatile("lwzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le32_to_cpu(val); +} + static inline uint32_t in_le32(const volatile uint32_t *addr) { - return bswap_32(in_be32(addr)); + sync(); + return __in_le32(addr); } static inline uint64_t __in_be64(const volatile uint64_t *addr) { - uint64_t val; + __be64 val; asm volatile("ldcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be64_to_cpu(val); } static inline uint64_t in_be64(const volatile uint64_t *addr) @@ -85,9 +104,18 @@ static inline uint64_t in_be64(const volatile uint64_t *addr) return __in_be64(addr); } +static inline uint64_t __in_le64(const volatile uint64_t *addr) +{ + __le64 val; + asm volatile("ldcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le64_to_cpu(val); +} + static inline uint64_t in_le64(const volatile uint64_t *addr) { - return bswap_64(in_be64(addr)); + sync(); + return __in_le64(addr); } static inline void __out_8(volatile uint8_t *addr, uint8_t val) @@ -105,7 +133,7 @@ static inline void out_8(volatile uint8_t *addr, uint8_t val) static inline void __out_be16(volatile uint16_t *addr, uint16_t val) { asm volatile("sthcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be16(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be16(volatile uint16_t *addr, uint16_t val) @@ -114,15 +142,22 @@ static inline void out_be16(volatile uint16_t *addr, uint16_t val) return __out_be16(addr, val); } +static inline void __out_le16(volatile uint16_t *addr, uint16_t val) +{ + asm volatile("sthcix %0,0,%1" + : : "r"(cpu_to_le16(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le16(volatile uint16_t *addr, uint16_t val) { - out_be16(addr, bswap_16(val)); + sync(); + return __out_le16(addr, val); } static inline void __out_be32(volatile uint32_t *addr, uint32_t val) { asm volatile("stwcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be32(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be32(volatile uint32_t *addr, uint32_t val) @@ -131,15 +166,22 @@ static inline void out_be32(volatile uint32_t *addr, uint32_t val) return __out_be32(addr, val); } +static inline void __out_le32(volatile uint32_t *addr, uint32_t val) +{ + asm volatile("stwcix %0,0,%1" + : : "r"(cpu_to_le32(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le32(volatile uint32_t *addr, uint32_t val) { - out_be32(addr, bswap_32(val)); + sync(); + return __out_le32(addr, val); } static inline void __out_be64(volatile uint64_t *addr, uint64_t val) { asm volatile("stdcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be64(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be64(volatile uint64_t *addr, uint64_t val) @@ -148,9 +190,16 @@ static inline void out_be64(volatile uint64_t *addr, uint64_t val) return __out_be64(addr, val); } +static inline void __out_le64(volatile uint64_t *addr, uint64_t val) +{ + asm volatile("stdcix %0,0,%1" + : : "r"(cpu_to_le64(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le64(volatile uint64_t *addr, uint64_t val) { - out_be64(addr, bswap_64(val)); + sync(); + return __out_le64(addr, val); } /* Assistant to macros used to access PCI config space */ diff --git a/include/types.h b/include/types.h index a7a45f5cb..e7660f6b7 100644 --- a/include/types.h +++ b/include/types.h @@ -11,5 +11,9 @@ typedef beint16_t __be16; typedef beint32_t __be32; typedef beint64_t __be64; +typedef leint16_t __le16; +typedef leint32_t __le32; +typedef leint64_t __le64; + #endif /* __TYPES_H */ diff --git a/libflash/ipmi-hiomap.c b/libflash/ipmi-hiomap.c index 7327b83a3..7591dfee6 100644 --- a/libflash/ipmi-hiomap.c +++ b/libflash/ipmi-hiomap.c @@ -570,8 +570,13 @@ static int lpc_window_read(struct ipmi_hiomap *ctx, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(__be32 *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -615,12 +620,15 @@ static int lpc_window_write(struct ipmi_hiomap *ctx, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(__be32 *)buf); + + rc = lpc_write(OPAL_LPC_FW, off, dat, 4); chunk = 4; } else { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + uint8_t dat = *(uint8_t *)buf; + + rc = lpc_write(OPAL_LPC_FW, off, dat, 1); chunk = 1; } if (rc) { diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 9d47fe7ea..5df020f55 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -159,8 +159,13 @@ static int lpc_window_read(struct mbox_flash_data *mbox_flash, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(__be32 *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -194,12 +199,15 @@ static int lpc_window_write(struct mbox_flash_data *mbox_flash, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(__be32 *)buf); + + rc = lpc_write(OPAL_LPC_FW, off, dat, 4); chunk = 4; } else { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + uint8_t dat = *(uint8_t *)buf; + + rc = lpc_write(OPAL_LPC_FW, off, dat, 1); chunk = 1; } if (rc) { From patchwork Wed Nov 6 12:10:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QVv5vW2z9sNx for ; Wed, 6 Nov 2019 23:16:23 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:43 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:29 +1000 Message-Id: <20191106121047.14389-12-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 11/29] hmi: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/hmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index cb158c01c..3e38e04d5 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -399,7 +399,7 @@ static bool decode_core_fir(struct cpu_thread *cpu, if (core_fir & PPC_BIT(xstop_bits[i].bit)) { found = true; hmi_evt->u.xstop_error.xstop_reason - |= xstop_bits[i].reason; + |= cpu_to_be32(xstop_bits[i].reason); } } return found; @@ -430,7 +430,7 @@ static void find_core_checkstop_reason(struct OpalHMIEvent *hmi_evt, /* Initialize xstop_error fields. */ hmi_evt->u.xstop_error.xstop_reason = 0; - hmi_evt->u.xstop_error.u.pir = cpu->pir; + hmi_evt->u.xstop_error.u.pir = cpu_to_be32(cpu->pir); if (decode_core_fir(cpu, hmi_evt)) queue_hmi_event(hmi_evt, 0, out_flags); @@ -521,7 +521,7 @@ static void find_nx_checkstop_reason(int flat_chip_id, hmi_evt->severity = OpalHMI_SEV_FATAL; hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT; hmi_evt->u.xstop_error.xstop_type = CHECKSTOP_TYPE_NX; - hmi_evt->u.xstop_error.u.chip_id = flat_chip_id; + hmi_evt->u.xstop_error.u.chip_id = cpu_to_be32(flat_chip_id); /* Get DMA & Engine FIR data register value. */ if (xscom_read(flat_chip_id, nx_dma_engine_fir, &nx_dma_fir) != 0) { @@ -539,12 +539,12 @@ static void find_nx_checkstop_reason(int flat_chip_id, for (i = 0; i < ARRAY_SIZE(nx_dma_xstop_bits); i++) if (nx_dma_fir & PPC_BIT(nx_dma_xstop_bits[i].bit)) hmi_evt->u.xstop_error.xstop_reason - |= nx_dma_xstop_bits[i].reason; + |= cpu_to_be32(nx_dma_xstop_bits[i].reason); for (i = 0; i < ARRAY_SIZE(nx_pbi_xstop_bits); i++) if (nx_pbi_fir_val & PPC_BIT(nx_pbi_xstop_bits[i].bit)) hmi_evt->u.xstop_error.xstop_reason - |= nx_pbi_xstop_bits[i].reason; + |= cpu_to_be32(nx_pbi_xstop_bits[i].reason); /* * Set NXDMAENGFIR[38] to signal PRD that service action is required. @@ -705,8 +705,8 @@ static void find_npu2_checkstop_reason(int flat_chip_id, hmi_evt->severity = OpalHMI_SEV_WARNING; hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT; hmi_evt->u.xstop_error.xstop_type = CHECKSTOP_TYPE_NPU; - hmi_evt->u.xstop_error.xstop_reason = xstop_reason; - hmi_evt->u.xstop_error.u.chip_id = flat_chip_id; + hmi_evt->u.xstop_error.xstop_reason = cpu_to_be32(xstop_reason); + hmi_evt->u.xstop_error.u.chip_id = cpu_to_be32(flat_chip_id); /* Marking the event as recoverable so that we don't crash */ queue_hmi_event(hmi_evt, 1, out_flags); @@ -774,7 +774,7 @@ static void find_npu_checkstop_reason(int flat_chip_id, hmi_evt->severity = OpalHMI_SEV_WARNING; hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT; hmi_evt->u.xstop_error.xstop_type = CHECKSTOP_TYPE_NPU; - hmi_evt->u.xstop_error.u.chip_id = flat_chip_id; + hmi_evt->u.xstop_error.u.chip_id = cpu_to_be32(flat_chip_id); /* The HMI is "recoverable" because it shouldn't crash the system */ queue_hmi_event(hmi_evt, 1, out_flags); @@ -1116,7 +1116,7 @@ static int handle_tfac_errors(struct OpalHMIEvent *hmi_evt, uint64_t *out_flags) uint64_t tfmr = mfspr(SPR_TFMR); /* Initialize the hmi event with old value of TFMR */ - hmi_evt->tfmr = tfmr; + hmi_evt->tfmr = cpu_to_be64(tfmr); /* A TFMR parity/corrupt error makes us ignore all the local stuff.*/ if (tfmr & SPR_TFMR_TFMR_CORRUPT) { @@ -1204,7 +1204,7 @@ static int handle_hmi_exception(uint64_t hmer, struct OpalHMIEvent *hmi_evt, prlog(PR_DEBUG, "Received HMI interrupt: HMER = 0x%016llx\n", hmer); /* Initialize the hmi event with old value of HMER */ if (hmi_evt) - hmi_evt->hmer = hmer; + hmi_evt->hmer = cpu_to_be64(hmer); /* Handle Timer/TOD errors separately */ if (hmer & (SPR_HMER_TFAC_ERROR | SPR_HMER_TFMR_PARITY_ERROR)) { From patchwork Wed Nov 6 12:10:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QWL2tvhz9sNx for ; Wed, 6 Nov 2019 23:16:46 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SeGy5oOM"; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:45 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:30 +1000 Message-Id: <20191106121047.14389-13-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 12/29] cvc: allow BE cvc code to be called from LE context X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- asm/cvc_entry.S | 42 ++++++++++++++++++------------------------ libstb/cvc.c | 16 +++++++++++----- libstb/cvc.h | 2 +- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/asm/cvc_entry.S b/asm/cvc_entry.S index 3e8b3fdad..94cd1aec1 100644 --- a/asm/cvc_entry.S +++ b/asm/cvc_entry.S @@ -1,28 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/secureboot/base/rom_entry.S $ -# -# OpenPOWER HostBoot Project -# -# COPYRIGHT International Business Machines Corp. 2013,2016 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -#.include "kernel/ppcconsts.S" + +# Derived from automatically generated HostBoot rom_entry.S + +#include +#include # Updated hostboot location is src/securerom/rom_entry.S. # This also has a fix for TOC save frame pointer. @@ -49,7 +30,20 @@ call_rom_entry: mr %r5, %r6 mr %r6, %r7 mr %r7, %r8 +#if HAVE_BIG_ENDIAN bctrl +#else + bl $+4 +1: mflr %r9 + addi %r9,%r9,2f - 1b + mtspr SPR_HSRR0, %r9 + mfmsr %r9 + xori %r9,%r9,MSR_LE + mtspr SPR_HSRR1, %r9 + hrfid +2: .long 0x2104804e /* bctrl */ + FIXUP_ENDIAN +#endif ld %r2, STACK_TOC_OFFSET(%r1) addi %r1, %r1, 128 ld %r0, 16(%r1) diff --git a/libstb/cvc.c b/libstb/cvc.c index dca4ac857..4fc29c08d 100644 --- a/libstb/cvc.c +++ b/libstb/cvc.c @@ -305,16 +305,19 @@ int call_cvc_sha512(const uint8_t *data, size_t data_len, uint8_t *digest, if (!service) return OPAL_UNSUPPORTED; - if (service->version == 1) + if (service->version == 1) { + unsigned long msr = mfmsr(); __cvc_sha512_v1((void*) service->addr, data, data_len, digest); - else + assert(msr == mfmsr()); + } else { return OPAL_UNSUPPORTED; + } return OPAL_SUCCESS; } int call_cvc_verify(void *container, size_t len, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log) + size_t hw_key_hash_size, __be64 *log) { ROM_hw_params hw_params; ROM_response rc; @@ -335,12 +338,15 @@ int call_cvc_verify(void *container, size_t len, const void *hw_key_hash, memset(&hw_params, 0, sizeof(ROM_hw_params)); memcpy(&hw_params.hw_key_hash, hw_key_hash, hw_key_hash_size); - if (service->version == 1) + if (service->version == 1) { + unsigned long msr = mfmsr(); rc = __cvc_verify_v1((void*) service->addr, (ROM_container_raw*) container, &hw_params); - else + assert(msr == mfmsr()); + } else { return OPAL_UNSUPPORTED; + } if (log) *log = hw_params.log; diff --git a/libstb/cvc.h b/libstb/cvc.h index 6d8546fb2..ef105f76d 100644 --- a/libstb/cvc.h +++ b/libstb/cvc.h @@ -30,7 +30,7 @@ int cvc_init(void); * */ int call_cvc_verify(void *buf, size_t size, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log); + size_t hw_key_hash_size, __be64 *log); /* * call_cvc_sha512 - Call the CVC-sha512 service to calculate a sha512 hash. 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:50 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:31 +1000 Message-Id: <20191106121047.14389-14-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 13/29] xive: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cedric Le Goater Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert xive opal calls, dt construction, and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- hw/xive.c | 388 ++++++++++++++++++++++------------------- include/xive-p9-regs.h | 51 +++--- include/xive-regs.h | 26 +++ include/xive.h | 2 +- 4 files changed, 258 insertions(+), 209 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index f1f9c6a05..dd91be6bd 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -396,7 +396,7 @@ struct xive { /* Indirect END/EQ table. NULL entries are unallocated, count is * the numbre of pointers (ie, sub page placeholders). */ - uint64_t *eq_ind_base; + __be64 *eq_ind_base; uint32_t eq_ind_count; /* EQ allocation bitmap. Each bit represent 8 EQs */ @@ -405,7 +405,7 @@ struct xive { /* Indirect NVT/VP table. NULL entries are unallocated, count is * the numbre of pointers (ie, sub page placeholders). */ - uint64_t *vp_ind_base; + __be64 *vp_ind_base; uint32_t vp_ind_count; /* Pool of donated pages for provisioning indirect EQ and VP pages */ @@ -717,7 +717,7 @@ static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx) if (idx >= (x->eq_ind_count * EQ_PER_PAGE)) return NULL; - p = (struct xive_eq *)(x->eq_ind_base[idx / EQ_PER_PAGE] & + p = (struct xive_eq *)(be64_to_cpu(x->eq_ind_base[idx / EQ_PER_PAGE]) & VSD_ADDRESS_MASK); if (!p) return NULL; @@ -749,7 +749,7 @@ static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn) /* If using single-escalation, don't let anybody get to the individual * esclation interrupts */ - if (eq->w0 & EQ_W0_UNCOND_ESCALATE) + if (xive_get_field32(EQ_W0_UNCOND_ESCALATE, eq->w0)) return NULL; /* Grab the buried IVE */ @@ -777,7 +777,7 @@ static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx) struct xive_vp *p; assert(idx < (x->vp_ind_count * VP_PER_PAGE)); - p = (struct xive_vp *)(x->vp_ind_base[idx / VP_PER_PAGE] & + p = (struct xive_vp *)(be64_to_cpu(x->vp_ind_base[idx / VP_PER_PAGE]) & VSD_ADDRESS_MASK); if (!p) return NULL; @@ -791,8 +791,8 @@ static void xive_init_default_vp(struct xive_vp *vp, memset(vp, 0, sizeof(struct xive_vp)); /* Stash the EQ base in the pressure relief interrupt field */ - vp->w1 = (eq_blk << 28) | eq_idx; - vp->w0 = VP_W0_VALID; + vp->w1 = cpu_to_be32((eq_blk << 28) | eq_idx); + vp->w0 = xive_set_field32(VP_W0_VALID, 0, 1); } static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, @@ -801,18 +801,20 @@ static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, { memset(eq, 0, sizeof(struct xive_eq)); - eq->w1 = EQ_W1_GENERATION; - eq->w3 = ((uint64_t)backing_page) & 0xffffffff; - eq->w2 = (((uint64_t)backing_page)) >> 32 & 0x0fffffff; - eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | - SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); - eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); - eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE | - SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) | - EQ_W0_FIRMWARE; + eq->w1 = xive_set_field32(EQ_W1_GENERATION, 0, 1); + eq->w3 = cpu_to_be32(((uint64_t)backing_page) & 0xffffffff); + eq->w2 = cpu_to_be32(((((uint64_t)backing_page)) >> 32) & 0x0fffffff); + eq->w6 = xive_set_field32(EQ_W6_NVT_BLOCK, 0, vp_blk) | + xive_set_field32(EQ_W6_NVT_INDEX, 0, vp_idx); + eq->w7 = xive_set_field32(EQ_W7_F0_PRIORITY, 0, prio); + eq->w0 = xive_set_field32(EQ_W0_VALID, 0, 1) | + xive_set_field32(EQ_W0_ENQUEUE, 0, 1) | + xive_set_field32(EQ_W0_FIRMWARE, 0, 1) | + xive_set_field32(EQ_W0_QSIZE, 0, EQ_QSIZE_64K) | #ifdef EQ_ALWAYS_NOTIFY - eq->w0 |= EQ_W0_UCOND_NOTIFY; + xive_set_field32(EQ_W0_UCOND_NOTIFY, 0, 1) | #endif + 0 ; } static uint32_t *xive_get_eq_buf(uint32_t eq_blk, uint32_t eq_idx) @@ -824,8 +826,8 @@ static uint32_t *xive_get_eq_buf(uint32_t eq_blk, uint32_t eq_idx) assert(x); eq = xive_get_eq(x, eq_idx); assert(eq); - assert(eq->w0 & EQ_W0_VALID); - addr = (((uint64_t)eq->w2) & 0x0fffffff) << 32 | eq->w3; + assert(xive_get_field32(EQ_W0_VALID, eq->w0)); + addr = ((((uint64_t)be32_to_cpu(eq->w2)) & 0x0fffffff) << 32) | be32_to_cpu(eq->w3); return (uint32_t *)addr; } @@ -894,8 +896,8 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect) } } memset(page, 0, 0x10000); - x->eq_ind_base[ind_idx] = vsd_flags | - (((uint64_t)page) & VSD_ADDRESS_MASK); + x->eq_ind_base[ind_idx] = cpu_to_be64(vsd_flags | + (((uint64_t)page) & VSD_ADDRESS_MASK)); /* Any cache scrub needed ? */ } @@ -941,7 +943,7 @@ static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t orde vsd = ((uint64_t)page) & VSD_ADDRESS_MASK; vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); - x->vp_ind_base[i] = vsd; + x->vp_ind_base[i] = cpu_to_be64(vsd); } return true; } @@ -1248,7 +1250,7 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, * one written. */ for (i = start_dword + dword_count - 1; i >= start_dword ;i--) { - uint64_t dw = ((uint64_t *)new_data)[i - start_dword]; + uint64_t dw = be64_to_cpu(((__be64 *)new_data)[i - start_dword]); __xive_regw(x, dreg0 + i * 8, dreg0x + i, dw, NULL); } @@ -1618,7 +1620,7 @@ static bool xive_prealloc_tables(struct xive *x) } /* SBEs are initialized to 0b01 which corresponds to "ints off" */ memset(x->sbe_base, 0x55, SBE_SIZE); - xive_dbg(x, "SBE at %p size 0x%x\n", x->sbe_base, IVT_SIZE); + xive_dbg(x, "SBE at %p size 0x%x\n", x->sbe_base, SBE_SIZE); /* EAS/IVT entries are 8 bytes */ x->ivt_base = local_alloc(x->chip_id, IVT_SIZE, IVT_SIZE); @@ -1685,7 +1687,7 @@ static bool xive_prealloc_tables(struct xive *x) vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); vsd |= VSD_FIRMWARE; - x->vp_ind_base[i] = vsd; + x->vp_ind_base[i] = cpu_to_be64(vsd); } /* Allocate the queue overflow pages */ @@ -1699,7 +1701,7 @@ static bool xive_prealloc_tables(struct xive *x) static void xive_add_provisioning_properties(void) { - uint32_t chips[XIVE_MAX_CHIPS]; + __be32 chips[XIVE_MAX_CHIPS]; uint32_t i, count; dt_add_property_cells(xive_dt_node, @@ -1707,7 +1709,7 @@ static void xive_add_provisioning_properties(void) count = 1 << xive_chips_alloc_bits; for (i = 0; i < count; i++) - chips[i] = xive_block_to_chip[i]; + chips[i] = cpu_to_be32(xive_block_to_chip[i]); dt_add_property(xive_dt_node, "ibm,xive-provision-chips", chips, 4 * count); } @@ -1832,7 +1834,9 @@ uint32_t xive_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align) for (i = 0; i < count; i++) { struct xive_ive *ive = xive_get_ive(x, base + i); - ive->w = IVE_VALID | IVE_MASKED | SETFIELD(IVE_EQ_DATA, 0ul, base + i); + ive->w = xive_set_field64(IVE_VALID, 0ul, 1) | + xive_set_field64(IVE_MASKED, 0ul, 1) | + xive_set_field64(IVE_EQ_DATA, 0ul, base + i); } unlock(&x->lock); @@ -1878,8 +1882,9 @@ uint32_t xive_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align) for (i = 0; i < count; i++) { struct xive_ive *ive = xive_get_ive(x, base + i); - ive->w = IVE_VALID | IVE_MASKED | - SETFIELD(IVE_EQ_DATA, 0ul, base + i); + ive->w = xive_set_field64(IVE_VALID, 0ul, 1) | + xive_set_field64(IVE_MASKED, 0ul, 1) | + xive_set_field64(IVE_EQ_DATA, 0ul, base + i); } unlock(&x->lock); @@ -2015,17 +2020,17 @@ static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, ive = xive_get_ive(x, isn); if (!ive) return false; - if (!(ive->w & IVE_VALID) && !is_escalation) { + if (!xive_get_field64(IVE_VALID, ive->w) && !is_escalation) { xive_err(x, "ISN %x lead to invalid IVE !\n", isn); return false; } if (out_lirq) - *out_lirq = GETFIELD(IVE_EQ_DATA, ive->w); + *out_lirq = xive_get_field64(IVE_EQ_DATA, ive->w); /* Find the EQ and its xive instance */ - eq_blk = GETFIELD(IVE_EQ_BLOCK, ive->w); - eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w); + eq_blk = xive_get_field64(IVE_EQ_BLOCK, ive->w); + eq_idx = xive_get_field64(IVE_EQ_INDEX, ive->w); eq_x = xive_from_vc_blk(eq_blk); /* This can fail if the interrupt hasn't been initialized yet @@ -2040,15 +2045,15 @@ static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, /* XXX Check valid and format 0 */ /* No priority conversion, return the actual one ! */ - if (ive->w & IVE_MASKED) + if (xive_get_field64(IVE_MASKED, ive->w)) prio = 0xff; else - prio = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); + prio = xive_get_field32(EQ_W7_F0_PRIORITY, eq->w7); if (out_prio) *out_prio = prio; - vp_blk = GETFIELD(EQ_W6_NVT_BLOCK, eq->w6); - vp_idx = GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + vp_blk = xive_get_field32(EQ_W6_NVT_BLOCK, eq->w6); + vp_idx = xive_get_field32(EQ_W6_NVT_INDEX, eq->w6); server = VP2PIR(vp_blk, vp_idx); if (out_target) @@ -2098,8 +2103,8 @@ static inline bool xive_eq_for_target(uint32_t target, uint8_t prio, /* Grab it, it's in the pressure relief interrupt field, * top 4 bits are the block (word 1). */ - eq_blk = vp->w1 >> 28; - eq_idx = vp->w1 & 0x0fffffff; + eq_blk = be32_to_cpu(vp->w1) >> 28; + eq_idx = be32_to_cpu(vp->w1) & 0x0fffffff; /* Currently the EQ block and VP block should be the same */ if (eq_blk != vp_blk) { @@ -2124,7 +2129,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, struct xive_ive *ive; uint32_t eq_blk, eq_idx; bool is_escalation = GIRQ_IS_ESCALATION(isn); - uint64_t new_ive; + __be64 new_ive; int64_t rc; /* Find XIVE on which the IVE resides */ @@ -2135,7 +2140,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, ive = xive_get_ive(x, isn); if (!ive) return OPAL_PARAMETER; - if (!(ive->w & IVE_VALID) && !is_escalation) { + if (!xive_get_field64(IVE_VALID, ive->w) && !is_escalation) { xive_err(x, "ISN %x lead to invalid IVE !\n", isn); return OPAL_PARAMETER; } @@ -2151,14 +2156,14 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, /* Are we masking ? */ if (prio == 0xff && !is_escalation) { - new_ive |= IVE_MASKED; + new_ive = xive_set_field64(IVE_MASKED, new_ive, 1); xive_vdbg(x, "ISN %x masked !\n", isn); /* Put prio 7 in the EQ */ prio = XIVE_MAX_PRIO; } else { /* Unmasking */ - new_ive = ive->w & ~IVE_MASKED; + new_ive = xive_set_field64(IVE_MASKED, new_ive, 0); xive_vdbg(x, "ISN %x unmasked !\n", isn); /* For normal interrupt sources, keep track of which ones @@ -2182,20 +2187,21 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, /* Try to update it atomically to avoid an intermediary * stale state */ - new_ive = SETFIELD(IVE_EQ_BLOCK, new_ive, eq_blk); - new_ive = SETFIELD(IVE_EQ_INDEX, new_ive, eq_idx); + new_ive = xive_set_field64(IVE_EQ_BLOCK, new_ive, eq_blk); + new_ive = xive_set_field64(IVE_EQ_INDEX, new_ive, eq_idx); } - new_ive = SETFIELD(IVE_EQ_DATA, new_ive, lirq); + new_ive = xive_set_field64(IVE_EQ_DATA, new_ive, lirq); xive_vdbg(x,"ISN %x routed to eq %x/%x lirq=%08x IVE=%016llx !\n", - isn, eq_blk, eq_idx, lirq, new_ive); + isn, eq_blk, eq_idx, lirq, be64_to_cpu(new_ive)); /* Updating the cache differs between real IVEs and escalation * IVEs inside an EQ */ if (is_escalation) { + uint64_t n = be64_to_cpu(new_ive); rc = xive_eqc_cache_update(x, x->block_id, GIRQ_TO_IDX(isn), - 2, 1, &new_ive, true, synchronous); + 2, 1, &n, true, synchronous); } else { sync(); ive->w = new_ive; @@ -2390,7 +2396,7 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn) */ /* If it's invalid or masked, don't do anything */ - if ((ive->w & IVE_MASKED) || !(ive->w & IVE_VALID)) + if (xive_get_field64(IVE_MASKED, ive->w) || !xive_get_field64(IVE_VALID, ive->w)) return; /* Grab MMIO control address for that ESB */ @@ -2757,13 +2763,17 @@ static bool xive_check_eq_update(struct xive *x, uint32_t idx, struct xive_eq *e if (memcmp(eq, &eq2, sizeof(struct xive_eq)) != 0) { xive_err(x, "EQ update mismatch idx %d\n", idx); xive_err(x, "want: %08x %08x %08x %08x\n", - eq->w0, eq->w1, eq->w2, eq->w3); + be32_to_cpu(eq->w0), be32_to_cpu(eq->w1), + be32_to_cpu(eq->w2), be32_to_cpu(eq->w3)); xive_err(x, " %08x %08x %08x %08x\n", - eq->w4, eq->w5, eq->w6, eq->w7); + be32_to_cpu(eq->w4), be32_to_cpu(eq->w5), + be32_to_cpu(eq->w6), be32_to_cpu(eq->w7)); xive_err(x, "got : %08x %08x %08x %08x\n", - eq2.w0, eq2.w1, eq2.w2, eq2.w3); + be32_to_cpu(eq2.w0), be32_to_cpu(eq2.w1), + be32_to_cpu(eq2.w2), be32_to_cpu(eq2.w3)); xive_err(x, " %08x %08x %08x %08x\n", - eq2.w4, eq2.w5, eq2.w6, eq2.w7); + be32_to_cpu(eq2.w4), be32_to_cpu(eq2.w5), + be32_to_cpu(eq2.w6), be32_to_cpu(eq2.w7)); return false; } return true; @@ -2779,13 +2789,17 @@ static bool xive_check_vpc_update(struct xive *x, uint32_t idx, struct xive_vp * if (memcmp(vp, &vp2, sizeof(struct xive_vp)) != 0) { xive_err(x, "VP update mismatch idx %d\n", idx); xive_err(x, "want: %08x %08x %08x %08x\n", - vp->w0, vp->w1, vp->w2, vp->w3); + be32_to_cpu(vp->w0), be32_to_cpu(vp->w1), + be32_to_cpu(vp->w2), be32_to_cpu(vp->w3)); xive_err(x, " %08x %08x %08x %08x\n", - vp->w4, vp->w5, vp->w6, vp->w7); + be32_to_cpu(vp->w4), be32_to_cpu(vp->w5), + be32_to_cpu(vp->w6), be32_to_cpu(vp->w7)); xive_err(x, "got : %08x %08x %08x %08x\n", - vp2.w0, vp2.w1, vp2.w2, vp2.w3); + be32_to_cpu(vp2.w0), be32_to_cpu(vp2.w1), + be32_to_cpu(vp2.w2), be32_to_cpu(vp2.w3)); xive_err(x, " %08x %08x %08x %08x\n", - vp2.w4, vp2.w5, vp2.w6, vp2.w7); + be32_to_cpu(vp2.w4), be32_to_cpu(vp2.w5), + be32_to_cpu(vp2.w6), be32_to_cpu(vp2.w7)); return false; } return true; @@ -2817,7 +2831,7 @@ static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); sync(); - vp.w1 = (i << 16) | i; + vp.w1 = cpu_to_be32((i << 16) | i); xive_vpc_cache_update(x, blk, idx, 0, 8, &vp, false, true); if (!xive_check_vpc_update(x, idx, &vp)) { @@ -2860,6 +2874,7 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) /* Use the cache watch to write it out */ lock(&x_eq->lock); + xive_eqc_cache_update(x_eq, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); @@ -3066,7 +3081,7 @@ static void xive_init_cpu(struct cpu_thread *c) static void xive_init_cpu_properties(struct cpu_thread *cpu) { struct cpu_thread *t; - uint32_t iprop[8][2] = { }; + __be32 iprop[8][2] = { }; uint32_t i; assert(cpu_thread_count <= 8); @@ -3077,7 +3092,7 @@ static void xive_init_cpu_properties(struct cpu_thread *cpu) t = (i == 0) ? cpu : find_cpu_by_pir(cpu->pir + i); if (!t) continue; - iprop[i][0] = t->xstate->ipi_irq; + iprop[i][0] = cpu_to_be32(t->xstate->ipi_irq); iprop[i][1] = 0; /* Edge */ } dt_add_property(cpu->node, "interrupts", iprop, cpu_thread_count * 8); @@ -3148,7 +3163,7 @@ static uint32_t xive_read_eq(struct xive_cpu_state *xs, bool just_peek) unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); prerror("EQ @%p W0=%08x W1=%08x qbuf @%p\n", - eq, eq->w0, eq->w1, xs->eqbuf); + eq, be32_to_cpu(eq->w0), be32_to_cpu(eq->w1), xs->eqbuf); } log_add(xs, LOG_TYPE_POPQ, 7, cur, xs->eqbuf[(xs->eqptr + 1) & xs->eqmsk], @@ -3365,20 +3380,20 @@ static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) xive_cpu_err(me, "no ive attached\n"); return true; } - xive_cpu_err(me, "ive=%016llx\n", ive->w); + xive_cpu_err(me, "ive=%016llx\n", be64_to_cpu(ive->w)); for_each_chip(chip) { x = chip->xive; if (!x) continue; ive = x->ivt_base; for (i = 0; i < MAX_INT_ENTRIES; i++) { - if ((ive[i].w & IVE_EQ_DATA) == irq) { - eq_blk = GETFIELD(IVE_EQ_BLOCK, ive[i].w); - eq_idx = GETFIELD(IVE_EQ_INDEX, ive[i].w); + if (xive_get_field64(IVE_EQ_DATA, ive[i].w) == irq) { + eq_blk = xive_get_field64(IVE_EQ_BLOCK, ive[i].w); + eq_idx = xive_get_field64(IVE_EQ_INDEX, ive[i].w); xive_cpu_err(me, "Found source: 0x%x ive=%016llx\n" " eq 0x%x/%x", BLKIDX_TO_GIRQ(x->block_id, i), - ive[i].w, eq_blk, eq_idx); + be64_to_cpu(ive[i].w), eq_blk, eq_idx); xive_dump_eq(eq_blk, eq_idx); } } @@ -3396,7 +3411,7 @@ static inline bool check_misrouted_ipi(struct cpu_thread *c __unused, } #endif -static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) +static int64_t opal_xive_get_xirr(__be32 *out_xirr, bool just_poll) { struct cpu_thread *c = this_cpu(); struct xive_cpu_state *xs = c->xstate; @@ -3480,7 +3495,7 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) false, false); unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); - log_add(xs, LOG_TYPE_EQD, 2, eq->w0, eq->w1); + log_add(xs, LOG_TYPE_EQD, 2, cpu_to_be32(eq->w0), cpu_to_be32(eq->w1)); } #endif /* XIVE_PERCPU_LOG */ @@ -3503,7 +3518,7 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) if (check_misrouted_ipi(c, val)) val = 2; - *out_xirr = (old_cppr << 24) | val; + *out_xirr = cpu_to_be32((old_cppr << 24) | val); /* If we are polling, that's it */ if (just_poll) @@ -3540,9 +3555,9 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) skip: log_add(xs, LOG_TYPE_XIRR2, 5, xs->cppr, xs->pending, - *out_xirr, xs->eqptr, xs->eqgen); + be32_to_cpu(*out_xirr), xs->eqptr, xs->eqgen); xive_cpu_vdbg(c, " returning XIRR=%08x, pending=0x%x\n", - *out_xirr, xs->pending); + be32_to_cpu(*out_xirr), xs->pending); unlock(&xs->lock); @@ -3616,11 +3631,11 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags) } static int64_t opal_xive_get_irq_info(uint32_t girq, - uint64_t *out_flags, - uint64_t *out_eoi_page, - uint64_t *out_trig_page, - uint32_t *out_esb_shift, - uint32_t *out_src_chip) + __be64 *out_flags, + __be64 *out_eoi_page, + __be64 *out_trig_page, + __be32 *out_esb_shift, + __be32 *out_src_chip) { struct irq_source *is = irq_find_source(girq); struct xive_src *s = container_of(is, struct xive_src, is); @@ -3635,12 +3650,12 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, assert(is->ops == &xive_irq_source_ops); if (out_flags) - *out_flags = xive_convert_irq_flags(s->flags); + *out_flags = cpu_to_be64(xive_convert_irq_flags(s->flags)); idx = girq - s->esb_base; if (out_esb_shift) - *out_esb_shift = s->esb_shift; + *out_esb_shift = cpu_to_be32(s->esb_shift); mm_base = (uint64_t)s->esb_mmio + (1ull << s->esb_shift) * idx; @@ -3656,27 +3671,31 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, trig_page = mm_base; if (out_eoi_page) - *out_eoi_page = eoi_page; + *out_eoi_page = cpu_to_be64(eoi_page); if (out_trig_page) - *out_trig_page = trig_page; + *out_trig_page = cpu_to_be64(trig_page); if (out_src_chip) - *out_src_chip = GIRQ_TO_CHIP(girq); + *out_src_chip = cpu_to_be32(GIRQ_TO_CHIP(girq)); return OPAL_SUCCESS; } static int64_t opal_xive_get_irq_config(uint32_t girq, - uint64_t *out_vp, + __be64 *out_vp, uint8_t *out_prio, - uint32_t *out_lirq) + __be32 *out_lirq) { uint32_t vp; + uint32_t lirq; + uint8_t prio; if (xive_mode != XIVE_MODE_EXPL) return OPAL_WRONG_STATE; - if (xive_get_irq_targetting(girq, &vp, out_prio, out_lirq)) { - *out_vp = vp; + if (xive_get_irq_targetting(girq, &vp, &prio, &lirq)) { + *out_vp = cpu_to_be64(vp); + *out_prio = prio; + *out_lirq = cpu_to_be32(lirq); return OPAL_SUCCESS; } else return OPAL_PARAMETER; @@ -3707,11 +3726,11 @@ static int64_t opal_xive_set_irq_config(uint32_t girq, } static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, - uint64_t *out_qpage, - uint64_t *out_qsize, - uint64_t *out_qeoi_page, - uint32_t *out_escalate_irq, - uint64_t *out_qflags) + __be64 *out_qpage, + __be64 *out_qsize, + __be64 *out_qeoi_page, + __be32 *out_escalate_irq, + __be64 *out_qflags) { uint32_t blk, idx; struct xive *x; @@ -3737,16 +3756,17 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, /* If escalations are routed to a single queue, fix up * the escalation interrupt number here. */ - if (eq->w0 & EQ_W0_UNCOND_ESCALATE) + if (xive_get_field32(EQ_W0_UNCOND_ESCALATE, eq->w0)) esc_idx |= XIVE_ESCALATION_PRIO; + *out_escalate_irq = - MAKE_ESCALATION_GIRQ(blk, esc_idx); + cpu_to_be32(MAKE_ESCALATION_GIRQ(blk, esc_idx)); } /* If this is a single-escalation gather queue, that's all * there is to return */ - if (eq->w0 & EQ_W0_SILENT_ESCALATE) { + if (xive_get_field32(EQ_W0_SILENT_ESCALATE, eq->w0)) { if (out_qflags) *out_qflags = 0; if (out_qpage) @@ -3759,30 +3779,29 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, } if (out_qpage) { - if (eq->w0 & EQ_W0_ENQUEUE) - *out_qpage = - (((uint64_t)(eq->w2 & EQ_W2_OP_DESC_HI)) << 32) | eq->w3; + if (xive_get_field32(EQ_W0_ENQUEUE, eq->w0)) + *out_qpage = cpu_to_be64(((uint64_t)xive_get_field32(EQ_W2_OP_DESC_HI, eq->w2) << 32) | be32_to_cpu(eq->w3)); else *out_qpage = 0; } if (out_qsize) { - if (eq->w0 & EQ_W0_ENQUEUE) - *out_qsize = GETFIELD(EQ_W0_QSIZE, eq->w0) + 12; + if (xive_get_field32(EQ_W0_ENQUEUE, eq->w0)) + *out_qsize = cpu_to_be64(xive_get_field32(EQ_W0_QSIZE, eq->w0) + 12); else *out_qsize = 0; } if (out_qeoi_page) { *out_qeoi_page = - (uint64_t)x->eq_mmio + idx * 0x20000; + cpu_to_be64((uint64_t)x->eq_mmio + idx * 0x20000); } if (out_qflags) { *out_qflags = 0; - if (eq->w0 & EQ_W0_VALID) - *out_qflags |= OPAL_XIVE_EQ_ENABLED; - if (eq->w0 & EQ_W0_UCOND_NOTIFY) - *out_qflags |= OPAL_XIVE_EQ_ALWAYS_NOTIFY; - if (eq->w0 & EQ_W0_ESCALATE_CTL) - *out_qflags |= OPAL_XIVE_EQ_ESCALATE; + if (xive_get_field32(EQ_W0_VALID, eq->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ENABLED); + if (xive_get_field32(EQ_W0_UCOND_NOTIFY, eq->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ALWAYS_NOTIFY); + if (xive_get_field32(EQ_W0_ESCALATE_CTL, eq->w0)) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ESCALATE); } return OPAL_SUCCESS; @@ -3790,8 +3809,8 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, static void xive_cleanup_eq(struct xive_eq *eq) { - eq->w0 = eq->w0 & EQ_W0_FIRMWARE; - eq->w1 = EQ_W1_ESe_Q | EQ_W1_ESn_Q; + eq->w0 = xive_set_field32(EQ_W0_FIRMWARE, eq->w0, 1); + eq->w1 = cpu_to_be32(EQ_W1_ESe_Q | EQ_W1_ESn_Q); eq->w2 = eq->w3 = eq->w4 = eq->w5 = eq->w6 = eq->w7 = 0; } @@ -3824,7 +3843,7 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, /* If this is a silent escalation queue, it cannot be * configured directly */ - if (old_eq->w0 & EQ_W0_SILENT_ESCALATE) + if (xive_get_field32(EQ_W0_SILENT_ESCALATE, old_eq->w0)) return OPAL_PARAMETER; /* This shouldn't fail or xive_eq_for_target would have @@ -3846,14 +3865,14 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, case 16: case 21: case 24: - eq.w3 = ((uint64_t)qpage) & EQ_W3_OP_DESC_LO; - eq.w2 = (((uint64_t)qpage) >> 32) & EQ_W2_OP_DESC_HI; - eq.w0 |= EQ_W0_ENQUEUE; - eq.w0 = SETFIELD(EQ_W0_QSIZE, eq.w0, qsize - 12); + eq.w3 = cpu_to_be32(((uint64_t)qpage) & EQ_W3_OP_DESC_LO); + eq.w2 = cpu_to_be32((((uint64_t)qpage) >> 32) & EQ_W2_OP_DESC_HI); + eq.w0 = xive_set_field32(EQ_W0_ENQUEUE, eq.w0, 1) | + xive_set_field32(EQ_W0_QSIZE, eq.w0, qsize - 12); break; case 0: eq.w2 = eq.w3 = 0; - eq.w0 &= ~EQ_W0_ENQUEUE; + eq.w0 = xive_set_field32(EQ_W0_ENQUEUE, eq.w0, 0); break; default: return OPAL_PARAMETER; @@ -3862,34 +3881,34 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, /* Ensure the priority and target are correctly set (they will * not be right after allocation */ - eq.w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | - SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); - eq.w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); + eq.w6 = xive_set_field32(EQ_W6_NVT_BLOCK, 0, vp_blk) | + xive_set_field32(EQ_W6_NVT_INDEX, 0, vp_idx); + eq.w7 = xive_set_field32(EQ_W7_F0_PRIORITY, 0, prio); /* XXX Handle group i bit when needed */ /* Always notify flag */ if (qflags & OPAL_XIVE_EQ_ALWAYS_NOTIFY) - eq.w0 |= EQ_W0_UCOND_NOTIFY; + eq.w0 = xive_set_field32(EQ_W0_UCOND_NOTIFY, eq.w0, 1); else - eq.w0 &= ~EQ_W0_UCOND_NOTIFY; + eq.w0 = xive_set_field32(EQ_W0_UCOND_NOTIFY, eq.w0, 0); /* Escalation flag */ if (qflags & OPAL_XIVE_EQ_ESCALATE) - eq.w0 |= EQ_W0_ESCALATE_CTL; + eq.w0 = xive_set_field32(EQ_W0_ESCALATE_CTL, eq.w0, 1); else - eq.w0 &= ~EQ_W0_ESCALATE_CTL; + eq.w0 = xive_set_field32(EQ_W0_ESCALATE_CTL, eq.w0, 0); /* Unconditionally clear the current queue pointer, set * generation to 1 and disable escalation interrupts. */ - eq.w1 = EQ_W1_GENERATION | - (old_eq->w1 & (EQ_W1_ESe_P | EQ_W1_ESe_Q | - EQ_W1_ESn_P | EQ_W1_ESn_Q)); + eq.w1 = xive_set_field32(EQ_W1_GENERATION, 0, 1) | + xive_set_field32(EQ_W1_ES, 0, xive_get_field32(EQ_W1_ES, old_eq->w1)); /* Enable. We always enable backlog for an enabled queue * otherwise escalations won't work. */ - eq.w0 |= EQ_W0_VALID | EQ_W0_BACKLOG; + eq.w0 = xive_set_field32(EQ_W0_VALID, eq.w0, 1) | + xive_set_field32(EQ_W0_BACKLOG, eq.w0, 1); } else xive_cleanup_eq(&eq); @@ -3902,8 +3921,8 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, } static int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, - uint32_t *out_qtoggle, - uint32_t *out_qindex) + __be32 *out_qtoggle, + __be32 *out_qindex) { uint32_t blk, idx; struct xive *x; @@ -3933,11 +3952,11 @@ static int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, return rc; /* We don't do disable queues */ - if (!(eq->w0 & EQ_W0_VALID)) + if (!xive_get_field32(EQ_W0_VALID, eq->w0)) return OPAL_WRONG_STATE; - *out_qtoggle = GETFIELD(EQ_W1_GENERATION, eq->w1); - *out_qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1); + *out_qtoggle = cpu_to_be32(xive_get_field32(EQ_W1_GENERATION, eq->w1)); + *out_qindex = cpu_to_be32(xive_get_field32(EQ_W1_PAGE_OFF, eq->w1)); return OPAL_SUCCESS; } @@ -3965,13 +3984,13 @@ static int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, return OPAL_PARAMETER; /* We don't do disable queues */ - if (!(eq->w0 & EQ_W0_VALID)) + if (!xive_get_field32(EQ_W0_VALID, eq->w0)) return OPAL_WRONG_STATE; new_eq = *eq; - new_eq.w1 = SETFIELD(EQ_W1_GENERATION, new_eq.w1, qtoggle); - new_eq.w1 = SETFIELD(EQ_W1_PAGE_OFF, new_eq.w1, qindex); + new_eq.w1 = xive_set_field32(EQ_W1_GENERATION, new_eq.w1, qtoggle) | + xive_set_field32(EQ_W1_PAGE_OFF, new_eq.w1, qindex); lock(&x->lock); rc = xive_eqc_cache_update(x, blk, idx, 0, 4, &new_eq, false, false); @@ -4003,10 +4022,10 @@ static int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr) } static int64_t opal_xive_get_vp_info(uint64_t vp_id, - uint64_t *out_flags, - uint64_t *out_cam_value, - uint64_t *out_report_cl_pair, - uint32_t *out_chip_id) + __be64 *out_flags, + __be64 *out_cam_value, + __be64 *out_report_cl_pair, + __be32 *out_chip_id) { struct xive *x; struct xive_vp *vp; @@ -4049,22 +4068,22 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, eq = xive_get_eq(x, eq_idx); if (!eq) return OPAL_PARAMETER; - if (vp->w0 & VP_W0_VALID) - *out_flags |= OPAL_XIVE_VP_ENABLED; - if (eq->w0 & EQ_W0_SILENT_ESCALATE) - *out_flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; + if (xive_get_field32(VP_W0_VALID, vp->w0)) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_ENABLED); + if (xive_get_field32(EQ_W0_SILENT_ESCALATE, eq->w0)) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_SINGLE_ESCALATION); } if (out_cam_value) - *out_cam_value = (blk << NVT_SHIFT) | idx; + *out_cam_value = cpu_to_be64((blk << NVT_SHIFT) | idx); if (out_report_cl_pair) { - *out_report_cl_pair = ((uint64_t)(vp->w6 & 0x0fffffff)) << 32; - *out_report_cl_pair |= vp->w7 & 0xffffff00; + *out_report_cl_pair = cpu_to_be64(((uint64_t)(be32_to_cpu(vp->w6) & 0x0fffffff)) << 32); + *out_report_cl_pair |= cpu_to_be64(be32_to_cpu(vp->w7) & 0xffffff00); } if (out_chip_id) - *out_chip_id = xive_block_to_chip[blk]; + *out_chip_id = cpu_to_be32(xive_block_to_chip[blk]); return OPAL_SUCCESS; } @@ -4092,8 +4111,8 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) /* If trying to enable silent gather, make sure prio 7 is not * already enabled as a normal queue */ - if (enable && (eq_orig->w0 & EQ_W0_VALID) && - !(eq_orig->w0 & EQ_W0_SILENT_ESCALATE)) { + if (enable && xive_get_field32(EQ_W0_VALID, eq_orig->w0) && + !xive_get_field32(EQ_W0_SILENT_ESCALATE, eq_orig->w0)) { xive_dbg(x, "Attempt at enabling silent gather but" " prio 7 queue already in use\n"); return OPAL_PARAMETER; @@ -4103,15 +4122,17 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) if (enable) { /* W0: Enabled and "s" set, no other bit */ - eq.w0 &= EQ_W0_FIRMWARE; - eq.w0 |= EQ_W0_VALID | EQ_W0_SILENT_ESCALATE | - EQ_W0_ESCALATE_CTL | EQ_W0_BACKLOG; + eq.w0 = xive_set_field32(EQ_W0_FIRMWARE, 0, xive_get_field32(EQ_W0_FIRMWARE, eq.w0)) | + xive_set_field32(EQ_W0_VALID, 0, 1) | + xive_set_field32(EQ_W0_SILENT_ESCALATE, 0, 1) | + xive_set_field32(EQ_W0_ESCALATE_CTL, 0, 1) | + xive_set_field32(EQ_W0_BACKLOG, 0, 1); /* W1: Mark ESn as 01, ESe as 00 */ - eq.w1 &= ~EQ_W1_ESn_P; - eq.w1 |= EQ_W1_ESn_Q; - eq.w1 &= ~(EQ_W1_ESe); - } else if (eq.w0 & EQ_W0_SILENT_ESCALATE) + eq.w1 = xive_set_field32(EQ_W1_ESn_P, eq.w1, 0) | + xive_set_field32(EQ_W1_ESn_Q, eq.w1, 1) | + xive_set_field32(EQ_W1_ESe, eq.w1, 0); + } else if (xive_get_field32(EQ_W0_SILENT_ESCALATE, eq.w0)) xive_cleanup_eq(&eq); if (!memcmp(eq_orig, &eq, sizeof(eq))) @@ -4134,19 +4155,17 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) eq = *eq_orig; if (enable) { /* Set new "u" bit */ - eq.w0 |= EQ_W0_UNCOND_ESCALATE; + eq.w0 = xive_set_field32(EQ_W0_UNCOND_ESCALATE, eq.w0, 1); /* Re-route escalation interrupt (previous * route is lost !) to the gather queue */ - eq.w4 = SETFIELD(EQ_W4_ESC_EQ_BLOCK, - eq.w4, blk); - eq.w4 = SETFIELD(EQ_W4_ESC_EQ_INDEX, - eq.w4, idx + XIVE_ESCALATION_PRIO); - } else if (eq.w0 & EQ_W0_UNCOND_ESCALATE) { + eq.w4 = xive_set_field32(EQ_W4_ESC_EQ_BLOCK, eq.w4, blk) | + xive_set_field32(EQ_W4_ESC_EQ_INDEX, eq.w4, idx + XIVE_ESCALATION_PRIO); + } else if (xive_get_field32(EQ_W0_UNCOND_ESCALATE, eq.w0)) { /* Clear the "u" bit, disable escalations if it was set */ - eq.w0 &= ~EQ_W0_UNCOND_ESCALATE; - eq.w0 &= ~EQ_W0_ESCALATE_CTL; + eq.w0 = xive_set_field32(EQ_W0_UNCOND_ESCALATE, eq.w0, 0) | + xive_set_field32(EQ_W0_ESCALATE_CTL, eq.w0, 0); } if (!memcmp(eq_orig, &eq, sizeof(eq))) continue; @@ -4187,9 +4206,9 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id, vp_new = *vp; if (flags & OPAL_XIVE_VP_ENABLED) { - vp_new.w0 |= VP_W0_VALID; - vp_new.w6 = report_cl_pair >> 32; - vp_new.w7 = report_cl_pair & 0xffffffff; + vp_new.w0 = xive_set_field32(VP_W0_VALID, vp_new.w0, 1); + vp_new.w6 = cpu_to_be32(report_cl_pair >> 32); + vp_new.w7 = cpu_to_be32(report_cl_pair & 0xffffffff); if (flags & OPAL_XIVE_VP_SINGLE_ESCALATION) rc = xive_setup_silent_gather(vp_id, true); @@ -4221,7 +4240,7 @@ bail: return rc; } -static int64_t opal_xive_get_vp_state(uint64_t vp_id, uint64_t *out_state) +static int64_t opal_xive_get_vp_state(uint64_t vp_id, __be64 *out_state) { struct xive *x; struct xive_vp *vp; @@ -4247,14 +4266,14 @@ static int64_t opal_xive_get_vp_state(uint64_t vp_id, uint64_t *out_state) if (rc) return rc; - if (!(vp->w0 & VP_W0_VALID)) + if (!xive_get_field32(VP_W0_VALID, vp->w0)) return OPAL_WRONG_STATE; /* * Return word4 and word5 which contain the saved HW thread * context. The IPB register is all we care for now on P9. */ - *out_state = (((uint64_t)vp->w4) << 32) | vp->w5; + *out_state = cpu_to_be64((((uint64_t)be32_to_cpu(vp->w4)) << 32) | be32_to_cpu(vp->w5)); return OPAL_SUCCESS; } @@ -4343,7 +4362,7 @@ static void xive_cleanup_vp_ind(struct xive *x) xive_dbg(x, "Cleaning up %d VP ind entries...\n", x->vp_ind_count); for (i = 0; i < x->vp_ind_count; i++) { - if (x->vp_ind_base[i] & VSD_FIRMWARE) { + if (be64_to_cpu(x->vp_ind_base[i]) & VSD_FIRMWARE) { xive_dbg(x, " %04x ... skip (firmware)\n", i); continue; } @@ -4361,7 +4380,7 @@ static void xive_cleanup_eq_ind(struct xive *x) xive_dbg(x, "Cleaning up %d EQ ind entries...\n", x->eq_ind_count); for (i = 0; i < x->eq_ind_count; i++) { - if (x->eq_ind_base[i] & VSD_FIRMWARE) { + if (be64_to_cpu(x->eq_ind_base[i]) & VSD_FIRMWARE) { xive_dbg(x, " %04x ... skip (firmware)\n", i); continue; } @@ -4416,16 +4435,16 @@ static void xive_reset_one(struct xive *x) * we will incorrectly free the EQs that are reserved * for the physical CPUs */ - if (eq->w0 & EQ_W0_VALID) { - if (!(eq->w0 & EQ_W0_FIRMWARE)) + if (xive_get_field32(EQ_W0_VALID, eq->w0)) { + if (!xive_get_field32(EQ_W0_FIRMWARE, eq->w0)) xive_dbg(x, "EQ 0x%x:0x%x is valid at reset: %08x %08x\n", - x->block_id, idx, eq->w0, eq->w1); + x->block_id, idx, be32_to_cpu(eq->w0), be32_to_cpu(eq->w1)); eq0 = *eq; xive_cleanup_eq(&eq0); xive_eqc_cache_update(x, x->block_id, idx, 0, 4, &eq0, false, true); } - if (eq->w0 & EQ_W0_FIRMWARE) + if (xive_get_field32(EQ_W0_FIRMWARE, eq->w0)) eq_firmware = true; } if (!eq_firmware) @@ -4456,7 +4475,7 @@ static void xive_reset_one(struct xive *x) /* Is the VP valid ? */ vp = xive_get_vp(x, i); - if (!vp || !(vp->w0 & VP_W0_VALID)) + if (!vp || !xive_get_field32(VP_W0_VALID, vp->w0)) continue; /* Clear it */ @@ -4626,7 +4645,7 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) } /* VP must be disabled */ - if (vp->w0 & VP_W0_VALID) { + if (xive_get_field32(VP_W0_VALID, vp->w0)) { prlog(PR_ERR, "XIVE: freeing active VP %d\n", vp_id); return OPAL_XIVE_FREE_ACTIVE; } @@ -4634,8 +4653,8 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) /* Not populated */ if (vp->w1 == 0) continue; - eq_blk = vp->w1 >> 28; - eq_idx = vp->w1 & 0x0fffffff; + eq_blk = be32_to_cpu(vp->w1) >> 28; + eq_idx = be32_to_cpu(vp->w1) & 0x0fffffff; lock(&x->lock); @@ -4646,7 +4665,7 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) struct xive *eq_x = xive_from_vc_blk(eq_blk); struct xive_eq eq, *orig_eq = xive_get_eq(eq_x, eq_idx + j); - if (!(orig_eq->w0 & EQ_W0_VALID)) + if (!xive_get_field32(EQ_W0_VALID, orig_eq->w0)) continue; prlog(PR_WARNING, "XIVE: freeing VP %d with queue %d active\n", @@ -4734,7 +4753,7 @@ static int64_t opal_xive_alloc_vp_block(uint32_t alloc_order) * it out of the cache. */ memset(vp, 0, sizeof(*vp)); - vp->w1 = (blk << 28) | eqs; + vp->w1 = cpu_to_be32((blk << 28) | eqs); } return vp_base; fail: @@ -4771,7 +4790,9 @@ static int64_t xive_try_allocate_irq(struct xive *x) unlock(&x->lock); return OPAL_PARAMETER; } - ive->w = IVE_VALID | IVE_MASKED | SETFIELD(IVE_EQ_DATA, 0ul, girq); + ive->w = xive_set_field64(IVE_VALID, 0ul, 1) | + xive_set_field64(IVE_MASKED, 0ul, 1) | + xive_set_field64(IVE_EQ_DATA, 0ul, girq); unlock(&x->lock); return girq; @@ -4840,7 +4861,8 @@ static int64_t opal_xive_free_irq(uint32_t girq) xive_update_irq_mask(s, girq - s->esb_base, true); /* Mark the IVE masked and invalid */ - ive->w = IVE_MASKED | IVE_VALID; + ive->w = xive_set_field64(IVE_VALID, 0ul, 1) | + xive_set_field64(IVE_MASKED, 0ul, 1); xive_ivc_scrub(x, x->block_id, idx); /* Free it */ @@ -4980,7 +5002,7 @@ static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir) false, false); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); prlog(PR_INFO, "CPU[%04x]: EQ @%p W0=%08x W1=%08x qbuf @%p\n", - pir, eq, eq->w0, eq->w1, xs->eqbuf); + pir, eq, be32_to_cpu(eq->w0), be32_to_cpu(eq->w1), xs->eqbuf); return OPAL_SUCCESS; } diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h index f6b7c20b3..126ab525a 100644 --- a/include/xive-p9-regs.h +++ b/include/xive-p9-regs.h @@ -310,7 +310,7 @@ struct xive_ive { /* Use a single 64-bit definition to make it easier to * perform atomic updates */ - uint64_t w; + __be64 w; #define IVE_VALID PPC_BIT(0) #define IVE_EQ_BLOCK PPC_BITMASK(4,7) /* Destination EQ block# */ #define IVE_EQ_INDEX PPC_BITMASK(8,31) /* Destination EQ index */ @@ -320,7 +320,7 @@ struct xive_ive { /* EQ */ struct xive_eq { - uint32_t w0; + __be32 w0; #define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */ #define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ #define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ @@ -335,30 +335,31 @@ struct xive_eq { #define EQ_QSIZE_4K 0 #define EQ_QSIZE_64K 4 #define EQ_W0_HWDEP PPC_BITMASK32(24,31) - uint32_t w1; + __be32 w1; #define EQ_W1_ESn PPC_BITMASK32(0,1) #define EQ_W1_ESn_P PPC_BIT32(0) #define EQ_W1_ESn_Q PPC_BIT32(1) #define EQ_W1_ESe PPC_BITMASK32(2,3) #define EQ_W1_ESe_P PPC_BIT32(2) #define EQ_W1_ESe_Q PPC_BIT32(3) +#define EQ_W1_ES PPC_BITMASK32(0,3) #define EQ_W1_GENERATION PPC_BIT32(9) #define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31) - uint32_t w2; + __be32 w2; #define EQ_W2_MIGRATION_REG PPC_BITMASK32(0,3) #define EQ_W2_OP_DESC_HI PPC_BITMASK32(4,31) - uint32_t w3; + __be32 w3; #define EQ_W3_OP_DESC_LO PPC_BITMASK32(0,31) - uint32_t w4; + __be32 w4; #define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4,7) #define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8,31) - uint32_t w5; + __be32 w5; #define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1,31) - uint32_t w6; + __be32 w6; #define EQ_W6_FORMAT_BIT PPC_BIT32(8) #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) - uint32_t w7; + __be32 w7; #define EQ_W7_F0_IGNORE PPC_BIT32(0) #define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1) #define EQ_W7_F0_PRIORITY PPC_BITMASK32(8,15) @@ -368,24 +369,24 @@ struct xive_eq { /* VP */ struct xive_vp { - uint32_t w0; + __be32 w0; #define VP_W0_VALID PPC_BIT32(0) - uint32_t w1; - uint32_t w2; - uint32_t w3; - uint32_t w4; - uint32_t w5; - uint32_t w6; - uint32_t w7; - uint32_t w8; + __be32 w1; + __be32 w2; + __be32 w3; + __be32 w4; + __be32 w5; + __be32 w6; + __be32 w7; + __be32 w8; #define VP_W8_GRP_VALID PPC_BIT32(0) - uint32_t w9; - uint32_t wa; - uint32_t wb; - uint32_t wc; - uint32_t wd; - uint32_t we; - uint32_t wf; + __be32 w9; + __be32 wa; + __be32 wb; + __be32 wc; + __be32 wd; + __be32 we; + __be32 wf; }; #endif /* XIVE_P9_REGS_H */ diff --git a/include/xive-regs.h b/include/xive-regs.h index a6a6ce35a..7f0054ef5 100644 --- a/include/xive-regs.h +++ b/include/xive-regs.h @@ -8,6 +8,32 @@ #ifndef XIVE_REGS_H #define XIVE_REGS_H +static inline uint64_t xive_get_field64(uint64_t mask, beint64_t word) +{ + return (be64_to_cpu(word) & mask) >> MASK_TO_LSH(mask); +} + +static inline beint64_t xive_set_field64(uint64_t mask, beint64_t word, + uint64_t value) +{ + uint64_t tmp = (be64_to_cpu(word) & ~mask) | + ((value << MASK_TO_LSH(mask)) & mask); + return cpu_to_be64(tmp); +} + +static inline uint32_t xive_get_field32(uint32_t mask, beint32_t word) +{ + return (be32_to_cpu(word) & mask) >> MASK_TO_LSH(mask); +} + +static inline beint32_t xive_set_field32(uint32_t mask, beint32_t word, + uint32_t value) +{ + uint32_t tmp = (be32_to_cpu(word) & ~mask) | + ((value << MASK_TO_LSH(mask)) & mask); + return cpu_to_be32(tmp); +} + /* * TM registers are special, see below */ diff --git a/include/xive.h b/include/xive.h index 5706d275a..592a6dc09 100644 --- a/include/xive.h +++ b/include/xive.h @@ -27,7 +27,7 @@ uint32_t xive_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align); #define XIVE_HW_SRC_PSI 8 uint64_t xive_get_notify_port(uint32_t chip_id, uint32_t ent); -uint32_t xive_get_notify_base(uint32_t girq); +__attrconst uint32_t xive_get_notify_base(uint32_t girq); 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:53 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:32 +1000 Message-Id: <20191106121047.14389-15-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 14/29] phb4: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert phb4 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/phb4.c | 342 +++++++++++++++++++++++++------------------------ include/phb4.h | 2 +- 2 files changed, 177 insertions(+), 167 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index f02e675f0..5f8295192 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -273,7 +273,7 @@ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn, return OPAL_HARDWARE; /* Fetch the PE# from cache */ - *pe = p->tbl_rtt[bdfn]; + *pe = be16_to_cpu(p->tbl_rtt[bdfn]); return OPAL_SUCCESS; } @@ -923,7 +923,7 @@ static void phb4_init_ioda_cache(struct phb4 *p) * and this occurs before PEs have been assigned. */ for (i = 0; i < RTT_TABLE_ENTRIES; i++) - p->tbl_rtt[i] = PHB4_RESERVED_PE_NUM(p); + p->tbl_rtt[i] = cpu_to_be16(PHB4_RESERVED_PE_NUM(p)); memset(p->tbl_peltv, 0x0, p->tbl_peltv_size); memset(p->tve_cache, 0x0, sizeof(p->tve_cache)); @@ -1748,126 +1748,139 @@ static void phb4_err_clear(struct phb4 *p) static void phb4_read_phb_status(struct phb4 *p, struct OpalIoPhb4ErrorData *stat) { - uint16_t val = 0; uint32_t i; - uint64_t *pPEST; + __be64 *pPEST; + uint16_t __16; + uint32_t __32; + uint64_t __64; memset(stat, 0, sizeof(struct OpalIoPhb4ErrorData)); /* Error data common part */ - stat->common.version = OPAL_PHB_ERROR_DATA_VERSION_1; - stat->common.ioType = OPAL_PHB_ERROR_DATA_TYPE_PHB4; - stat->common.len = sizeof(struct OpalIoPhb4ErrorData); + stat->common.version = cpu_to_be32(OPAL_PHB_ERROR_DATA_VERSION_1); + stat->common.ioType = cpu_to_be32(OPAL_PHB_ERROR_DATA_TYPE_PHB4); + stat->common.len = cpu_to_be32(sizeof(struct OpalIoPhb4ErrorData)); /* Use ASB for config space if the PHB is fenced */ if (p->flags & PHB4_AIB_FENCED) p->flags |= PHB4_CFG_USE_ASB; /* Grab RC bridge control, make it 32-bit */ - phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &val); - stat->brdgCtl = val; + phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &__16); + stat->brdgCtl = cpu_to_be32(__16); /* * Grab various RC PCIe capability registers. All device, slot * and link status are 16-bit, so we grab the pair control+status * for each of them */ - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, - &stat->deviceStatus); - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, - &stat->slotStatus); - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, - &stat->linkStatus); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, &__32); + stat->deviceStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, &__32); + stat->slotStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, &__32); + stat->linkStatus = cpu_to_be32(__32); /* * I assume those are the standard config space header, cmd & status * together makes 32-bit. Secondary status is 16-bit so I'll clear * the top on that one */ - phb4_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); - phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &val); - stat->devSecStatus = val; + phb4_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &__32); + stat->devCmdStatus = cpu_to_be32(__32); + phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &__16); + stat->devSecStatus = cpu_to_be32(__32); /* Grab a bunch of AER regs */ - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, - &stat->rootErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, - &stat->uncorrErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, - &stat->corrErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, - &stat->tlpHdr1); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, - &stat->tlpHdr2); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, - &stat->tlpHdr3); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, - &stat->tlpHdr4); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, - &stat->sourceId); + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, &__32); + stat->rootErrorStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, &__32); + stat->uncorrErrorStatus = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, &__32); + stat->corrErrorStatus = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, &__32); + stat->tlpHdr1 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, &__32); + stat->tlpHdr2 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, &__32); + stat->tlpHdr3 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, &__32); + stat->tlpHdr4 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, &__32); + stat->sourceId = cpu_to_be32(__32); + /* PEC NFIR, same as P8/PHB3 */ - xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &stat->nFir); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x3, &stat->nFirMask); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x8, &stat->nFirWOF); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &__64); + stat->nFir = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x3, &__64); + stat->nFirMask = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x8, &__64); + stat->nFirWOF = cpu_to_be64(__64); /* PHB4 inbound and outbound error Regs */ - stat->phbPlssr = phb4_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS); - stat->phbCsr = phb4_read_reg_asb(p, PHB_DMA_CHAN_STATUS); - stat->lemFir = phb4_read_reg_asb(p, PHB_LEM_FIR_ACCUM); - stat->lemErrorMask = phb4_read_reg_asb(p, PHB_LEM_ERROR_MASK); - stat->lemWOF = phb4_read_reg_asb(p, PHB_LEM_WOF); - stat->phbErrorStatus = phb4_read_reg_asb(p, PHB_ERR_STATUS); - stat->phbFirstErrorStatus = phb4_read_reg_asb(p, PHB_ERR1_STATUS); - stat->phbErrorLog0 = phb4_read_reg_asb(p, PHB_ERR_LOG_0); - stat->phbErrorLog1 = phb4_read_reg_asb(p, PHB_ERR_LOG_1); - stat->phbTxeErrorStatus = phb4_read_reg_asb(p, PHB_TXE_ERR_STATUS); - stat->phbTxeFirstErrorStatus = phb4_read_reg_asb(p, PHB_TXE_ERR1_STATUS); - stat->phbTxeErrorLog0 = phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_0); - stat->phbTxeErrorLog1 = phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_1); - stat->phbRxeArbErrorStatus = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_STATUS); - stat->phbRxeArbFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR1_STATUS); - stat->phbRxeArbErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_0); - stat->phbRxeArbErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_1); - stat->phbRxeMrgErrorStatus = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_STATUS); - stat->phbRxeMrgFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR1_STATUS); - stat->phbRxeMrgErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_0); - stat->phbRxeMrgErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_1); - stat->phbRxeTceErrorStatus = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_STATUS); - stat->phbRxeTceFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR1_STATUS); - stat->phbRxeTceErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_0); - stat->phbRxeTceErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_1); + stat->phbPlssr = cpu_to_be64(phb4_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS)); + stat->phbCsr = cpu_to_be64(phb4_read_reg_asb(p, PHB_DMA_CHAN_STATUS)); + stat->lemFir = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_FIR_ACCUM)); + stat->lemErrorMask = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_ERROR_MASK)); + stat->lemWOF = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_WOF)); + stat->phbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_STATUS)); + stat->phbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR1_STATUS)); + stat->phbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_LOG_0)); + stat->phbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_LOG_1)); + stat->phbTxeErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_STATUS)); + stat->phbTxeFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR1_STATUS)); + stat->phbTxeErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_0)); + stat->phbTxeErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_1)); + stat->phbRxeArbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_STATUS)); + stat->phbRxeArbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR1_STATUS)); + stat->phbRxeArbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_0)); + stat->phbRxeArbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_1)); + stat->phbRxeMrgErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_STATUS)); + stat->phbRxeMrgFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR1_STATUS)); + stat->phbRxeMrgErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_0)); + stat->phbRxeMrgErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_1)); + stat->phbRxeTceErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_STATUS)); + stat->phbRxeTceFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR1_STATUS)); + stat->phbRxeTceErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_0)); + stat->phbRxeTceErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_1)); /* PHB4 REGB error registers */ - stat->phbPblErrorStatus = phb4_read_reg_asb(p, PHB_PBL_ERR_STATUS); - stat->phbPblFirstErrorStatus = phb4_read_reg_asb(p, PHB_PBL_ERR1_STATUS); - stat->phbPblErrorLog0 = phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_0); - stat->phbPblErrorLog1 = phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_1); + stat->phbPblErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_STATUS)); + stat->phbPblFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR1_STATUS)); + stat->phbPblErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_0)); + stat->phbPblErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_1)); - stat->phbPcieDlpErrorStatus = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERR_STATUS); - stat->phbPcieDlpErrorLog1 = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG1); - stat->phbPcieDlpErrorLog2 = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG2); + stat->phbPcieDlpErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERR_STATUS)); + stat->phbPcieDlpErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG1)); + stat->phbPcieDlpErrorLog2 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG2)); - stat->phbRegbErrorStatus = phb4_read_reg_asb(p, PHB_REGB_ERR_STATUS); - stat->phbRegbFirstErrorStatus = phb4_read_reg_asb(p, PHB_REGB_ERR1_STATUS); - stat->phbRegbErrorLog0 = phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_0); - stat->phbRegbErrorLog1 = phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_1); + stat->phbRegbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_STATUS)); + stat->phbRegbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR1_STATUS)); + stat->phbRegbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_0)); + stat->phbRegbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_1)); /* * Grab PESTA & B content. The error bit (bit#0) should * be fetched from IODA and the left content from memory * resident tables. */ - pPEST = (uint64_t *)p->tbl_pest; + pPEST = (__be64 *)p->tbl_pest; phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, true); for (i = 0; i < p->max_num_pes; i++) { - stat->pestA[i] = phb4_read_reg_asb(p, PHB_IODA_DATA0); + stat->pestA[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); stat->pestA[i] |= pPEST[2 * i]; } phb4_ioda_sel(p, IODA3_TBL_PESTB, 0, true); for (i = 0; i < p->max_num_pes; i++) { - stat->pestB[i] = phb4_read_reg_asb(p, PHB_IODA_DATA0); + stat->pestB[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); stat->pestB[i] |= pPEST[2 * i + 1]; } } @@ -2017,17 +2030,17 @@ static void phb4_eeh_dump_regs(struct phb4 *p) } phb4_read_phb_status(p, s); - PHBERR(p, " brdgCtl = %08x\n", s->brdgCtl); + PHBERR(p, " brdgCtl = %08x\n", be32_to_cpu(s->brdgCtl)); /* PHB4 cfg regs */ - PHBERR(p, " deviceStatus = %08x\n", s->deviceStatus); - PHBERR(p, " slotStatus = %08x\n", s->slotStatus); - PHBERR(p, " linkStatus = %08x\n", s->linkStatus); - PHBERR(p, " devCmdStatus = %08x\n", s->devCmdStatus); - PHBERR(p, " devSecStatus = %08x\n", s->devSecStatus); - PHBERR(p, " rootErrorStatus = %08x\n", s->rootErrorStatus); - PHBERR(p, " corrErrorStatus = %08x\n", s->corrErrorStatus); - PHBERR(p, " uncorrErrorStatus = %08x\n", s->uncorrErrorStatus); + PHBERR(p, " deviceStatus = %08x\n", be32_to_cpu(s->deviceStatus)); + PHBERR(p, " slotStatus = %08x\n", be32_to_cpu(s->slotStatus)); + PHBERR(p, " linkStatus = %08x\n", be32_to_cpu(s->linkStatus)); + PHBERR(p, " devCmdStatus = %08x\n", be32_to_cpu(s->devCmdStatus)); + PHBERR(p, " devSecStatus = %08x\n", be32_to_cpu(s->devSecStatus)); + PHBERR(p, " rootErrorStatus = %08x\n", be32_to_cpu(s->rootErrorStatus)); + PHBERR(p, " corrErrorStatus = %08x\n", be32_to_cpu(s->corrErrorStatus)); + PHBERR(p, " uncorrErrorStatus = %08x\n", be32_to_cpu(s->uncorrErrorStatus)); /* Two non OPAL API registers that are useful */ phb4_pcicfg_read16(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, ®); @@ -2037,57 +2050,57 @@ static void phb4_eeh_dump_regs(struct phb4 *p) PHBERR(p, " devStat = %08x\n", reg); /* Byte swap TLP headers so they are the same as the PCIe spec */ - PHBERR(p, " tlpHdr1 = %08x\n", bswap_32(s->tlpHdr1)); - PHBERR(p, " tlpHdr2 = %08x\n", bswap_32(s->tlpHdr2)); - PHBERR(p, " tlpHdr3 = %08x\n", bswap_32(s->tlpHdr3)); - PHBERR(p, " tlpHdr4 = %08x\n", bswap_32(s->tlpHdr4)); - PHBERR(p, " sourceId = %08x\n", s->sourceId); - PHBERR(p, " nFir = %016llx\n", s->nFir); - PHBERR(p, " nFirMask = %016llx\n", s->nFirMask); - PHBERR(p, " nFirWOF = %016llx\n", s->nFirWOF); - PHBERR(p, " phbPlssr = %016llx\n", s->phbPlssr); - PHBERR(p, " phbCsr = %016llx\n", s->phbCsr); - PHBERR(p, " lemFir = %016llx\n", s->lemFir); - PHBERR(p, " lemErrorMask = %016llx\n", s->lemErrorMask); - PHBERR(p, " lemWOF = %016llx\n", s->lemWOF); - PHBERR(p, " phbErrorStatus = %016llx\n", s->phbErrorStatus); - PHBERR(p, " phbFirstErrorStatus = %016llx\n", s->phbFirstErrorStatus); - PHBERR(p, " phbErrorLog0 = %016llx\n", s->phbErrorLog0); - PHBERR(p, " phbErrorLog1 = %016llx\n", s->phbErrorLog1); - PHBERR(p, " phbTxeErrorStatus = %016llx\n", s->phbTxeErrorStatus); - PHBERR(p, " phbTxeFirstErrorStatus = %016llx\n", s->phbTxeFirstErrorStatus); - PHBERR(p, " phbTxeErrorLog0 = %016llx\n", s->phbTxeErrorLog0); - PHBERR(p, " phbTxeErrorLog1 = %016llx\n", s->phbTxeErrorLog1); - PHBERR(p, " phbRxeArbErrorStatus = %016llx\n", s->phbRxeArbErrorStatus); - PHBERR(p, "phbRxeArbFrstErrorStatus = %016llx\n", s->phbRxeArbFirstErrorStatus); - PHBERR(p, " phbRxeArbErrorLog0 = %016llx\n", s->phbRxeArbErrorLog0); - PHBERR(p, " phbRxeArbErrorLog1 = %016llx\n", s->phbRxeArbErrorLog1); - PHBERR(p, " phbRxeMrgErrorStatus = %016llx\n", s->phbRxeMrgErrorStatus); - PHBERR(p, "phbRxeMrgFrstErrorStatus = %016llx\n", s->phbRxeMrgFirstErrorStatus); - PHBERR(p, " phbRxeMrgErrorLog0 = %016llx\n", s->phbRxeMrgErrorLog0); - PHBERR(p, " phbRxeMrgErrorLog1 = %016llx\n", s->phbRxeMrgErrorLog1); - PHBERR(p, " phbRxeTceErrorStatus = %016llx\n", s->phbRxeTceErrorStatus); - PHBERR(p, "phbRxeTceFrstErrorStatus = %016llx\n", s->phbRxeTceFirstErrorStatus); - PHBERR(p, " phbRxeTceErrorLog0 = %016llx\n", s->phbRxeTceErrorLog0); - PHBERR(p, " phbRxeTceErrorLog1 = %016llx\n", s->phbRxeTceErrorLog1); - PHBERR(p, " phbPblErrorStatus = %016llx\n", s->phbPblErrorStatus); - PHBERR(p, " phbPblFirstErrorStatus = %016llx\n", s->phbPblFirstErrorStatus); - PHBERR(p, " phbPblErrorLog0 = %016llx\n", s->phbPblErrorLog0); - PHBERR(p, " phbPblErrorLog1 = %016llx\n", s->phbPblErrorLog1); - PHBERR(p, " phbPcieDlpErrorLog1 = %016llx\n", s->phbPcieDlpErrorLog1); - PHBERR(p, " phbPcieDlpErrorLog2 = %016llx\n", s->phbPcieDlpErrorLog2); - PHBERR(p, " phbPcieDlpErrorStatus = %016llx\n", s->phbPcieDlpErrorStatus); - - PHBERR(p, " phbRegbErrorStatus = %016llx\n", s->phbRegbErrorStatus); - PHBERR(p, " phbRegbFirstErrorStatus = %016llx\n", s->phbRegbFirstErrorStatus); - PHBERR(p, " phbRegbErrorLog0 = %016llx\n", s->phbRegbErrorLog0); - PHBERR(p, " phbRegbErrorLog1 = %016llx\n", s->phbRegbErrorLog1); + PHBERR(p, " tlpHdr1 = %08x\n", cpu_to_le32(be32_to_cpu(s->tlpHdr1))); + PHBERR(p, " tlpHdr2 = %08x\n", cpu_to_le32(be32_to_cpu(s->tlpHdr2))); + PHBERR(p, " tlpHdr3 = %08x\n", cpu_to_le32(be32_to_cpu(s->tlpHdr3))); + PHBERR(p, " tlpHdr4 = %08x\n", cpu_to_le32(be32_to_cpu(s->tlpHdr4))); + PHBERR(p, " sourceId = %08x\n", be32_to_cpu(s->sourceId)); + PHBERR(p, " nFir = %016llx\n", be64_to_cpu(s->nFir)); + PHBERR(p, " nFirMask = %016llx\n", be64_to_cpu(s->nFirMask)); + PHBERR(p, " nFirWOF = %016llx\n", be64_to_cpu(s->nFirWOF)); + PHBERR(p, " phbPlssr = %016llx\n", be64_to_cpu(s->phbPlssr)); + PHBERR(p, " phbCsr = %016llx\n", be64_to_cpu(s->phbCsr)); + PHBERR(p, " lemFir = %016llx\n", be64_to_cpu(s->lemFir)); + PHBERR(p, " lemErrorMask = %016llx\n", be64_to_cpu(s->lemErrorMask)); + PHBERR(p, " lemWOF = %016llx\n", be64_to_cpu(s->lemWOF)); + PHBERR(p, " phbErrorStatus = %016llx\n", be64_to_cpu(s->phbErrorStatus)); + PHBERR(p, " phbFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbFirstErrorStatus)); + PHBERR(p, " phbErrorLog0 = %016llx\n", be64_to_cpu(s->phbErrorLog0)); + PHBERR(p, " phbErrorLog1 = %016llx\n", be64_to_cpu(s->phbErrorLog1)); + PHBERR(p, " phbTxeErrorStatus = %016llx\n", be64_to_cpu(s->phbTxeErrorStatus)); + PHBERR(p, " phbTxeFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbTxeFirstErrorStatus)); + PHBERR(p, " phbTxeErrorLog0 = %016llx\n", be64_to_cpu(s->phbTxeErrorLog0)); + PHBERR(p, " phbTxeErrorLog1 = %016llx\n", be64_to_cpu(s->phbTxeErrorLog1)); + PHBERR(p, " phbRxeArbErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeArbErrorStatus)); + PHBERR(p, "phbRxeArbFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeArbFirstErrorStatus)); + PHBERR(p, " phbRxeArbErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeArbErrorLog0)); + PHBERR(p, " phbRxeArbErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeArbErrorLog1)); + PHBERR(p, " phbRxeMrgErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorStatus)); + PHBERR(p, "phbRxeMrgFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeMrgFirstErrorStatus)); + PHBERR(p, " phbRxeMrgErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorLog0)); + PHBERR(p, " phbRxeMrgErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorLog1)); + PHBERR(p, " phbRxeTceErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeTceErrorStatus)); + PHBERR(p, "phbRxeTceFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeTceFirstErrorStatus)); + PHBERR(p, " phbRxeTceErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeTceErrorLog0)); + PHBERR(p, " phbRxeTceErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeTceErrorLog1)); + PHBERR(p, " phbPblErrorStatus = %016llx\n", be64_to_cpu(s->phbPblErrorStatus)); + PHBERR(p, " phbPblFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbPblFirstErrorStatus)); + PHBERR(p, " phbPblErrorLog0 = %016llx\n", be64_to_cpu(s->phbPblErrorLog0)); + PHBERR(p, " phbPblErrorLog1 = %016llx\n", be64_to_cpu(s->phbPblErrorLog1)); + PHBERR(p, " phbPcieDlpErrorLog1 = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorLog1)); + PHBERR(p, " phbPcieDlpErrorLog2 = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorLog2)); + PHBERR(p, " phbPcieDlpErrorStatus = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorStatus)); + + PHBERR(p, " phbRegbErrorStatus = %016llx\n", be64_to_cpu(s->phbRegbErrorStatus)); + PHBERR(p, " phbRegbFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbRegbFirstErrorStatus)); + PHBERR(p, " phbRegbErrorLog0 = %016llx\n", be64_to_cpu(s->phbRegbErrorLog0)); + PHBERR(p, " phbRegbErrorLog1 = %016llx\n", be64_to_cpu(s->phbRegbErrorLog1)); for (i = 0; i < p->max_num_pes; i++) { if (!s->pestA[i] && !s->pestB[i]) continue; PHBERR(p, " PEST[%03x] = %016llx %016llx\n", - i, s->pestA[i], s->pestB[i]); + i, be64_to_cpu(s->pestA[i]), be64_to_cpu(s->pestB[i])); } free(s); } @@ -2131,7 +2144,7 @@ static int64_t phb4_set_pe(struct phb *phb, /* Map or unmap the RTT range */ for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++) if ((idx & mask) == (bdfn & mask)) - p->tbl_rtt[idx] = pe_number; + p->tbl_rtt[idx] = cpu_to_be16(pe_number); /* Invalidate the RID Translation Cache (RTC) inside the PHB */ out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL); @@ -3443,14 +3456,15 @@ static struct pci_slot *phb4_slot_create(struct phb *phb) static uint64_t phb4_get_pesta(struct phb4 *p, uint64_t pe_number) { - uint64_t pesta, *pPEST; + uint64_t pesta; + __be64 *pPEST; - pPEST = (uint64_t *)p->tbl_pest; + pPEST = (__be64 *)p->tbl_pest; phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false); pesta = phb4_read_reg(p, PHB_IODA_DATA0); if (pesta & IODA3_PESTA_MMIO_FROZEN) - pesta |= pPEST[2*pe_number]; + pesta |= be64_to_cpu(pPEST[2*pe_number]); return pesta; } @@ -3808,13 +3822,13 @@ static int64_t phb4_err_inject_cfg(struct phb4 *phb, uint64_t pe_number, ctrl = PHB_PAPR_ERR_INJ_CTL_CFG; for (bdfn = 0; bdfn < RTT_TABLE_ENTRIES; bdfn++) { - if (phb->tbl_rtt[bdfn] != pe_number) + if (be16_to_cpu(phb->tbl_rtt[bdfn]) != pe_number) continue; /* The PE can be associated with PCI bus or device */ is_bus_pe = false; if ((bdfn + 8) < RTT_TABLE_ENTRIES && - phb->tbl_rtt[bdfn + 8] == pe_number) + be16_to_cpu(phb->tbl_rtt[bdfn + 8]) == pe_number) is_bus_pe = true; /* Figure out the PCI config address */ @@ -5344,7 +5358,7 @@ static void phb4_allocate_tables(struct phb4 *p) p->tbl_rtt = local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE); assert(p->tbl_rtt); for (i = 0; i < RTT_TABLE_ENTRIES; i++) - p->tbl_rtt[i] = PHB4_RESERVED_PE_NUM(p); + p->tbl_rtt[i] = cpu_to_be16(PHB4_RESERVED_PE_NUM(p)); p->tbl_peltv = local_alloc(p->chip_id, p->tbl_peltv_size, p->tbl_peltv_size); assert(p->tbl_peltv); @@ -5482,11 +5496,11 @@ static bool phb4_calculate_windows(struct phb4 *p) "ibm,mmio-windows", -1); assert(prop->len >= (2 * sizeof(uint64_t))); - p->mm0_base = ((const uint64_t *)prop->prop)[0]; - p->mm0_size = ((const uint64_t *)prop->prop)[1]; + p->mm0_base = be64_to_cpu(((__be64 *)prop->prop)[0]); + p->mm0_size = be64_to_cpu(((__be64 *)prop->prop)[1]); if (prop->len > 16) { - p->mm1_base = ((const uint64_t *)prop->prop)[2]; - p->mm1_size = ((const uint64_t *)prop->prop)[3]; + p->mm1_base = be64_to_cpu(((__be64 *)prop->prop)[2]); + p->mm1_size = be64_to_cpu(((__be64 *)prop->prop)[3]); } /* Sort them so that 0 is big and 1 is small */ @@ -5558,16 +5572,12 @@ static const struct irq_source_ops phb4_lsi_ops = { .attributes = phb4_lsi_attributes, }; -#ifdef HAVE_BIG_ENDIAN -static u64 lane_eq_default[8] = { - 0x5454545454545454UL, 0x5454545454545454UL, - 0x5454545454545454UL, 0x5454545454545454UL, - 0x7777777777777777UL, 0x7777777777777777UL, - 0x7777777777777777UL, 0x7777777777777777UL +static __be64 lane_eq_default[8] = { + CPU_TO_BE64(0x5454545454545454UL), CPU_TO_BE64(0x5454545454545454UL), + CPU_TO_BE64(0x5454545454545454UL), CPU_TO_BE64(0x5454545454545454UL), + CPU_TO_BE64(0x7777777777777777UL), CPU_TO_BE64(0x7777777777777777UL), + CPU_TO_BE64(0x7777777777777777UL), CPU_TO_BE64(0x7777777777777777UL), }; -#else -#error lane_eq_default needs to be big endian (device tree property) -#endif static void phb4_create(struct dt_node *np) { @@ -5602,11 +5612,11 @@ static void phb4_create(struct dt_node *np) /* Get the various XSCOM register bases from the device-tree */ prop = dt_require_property(np, "ibm,xscom-bases", 5 * sizeof(uint32_t)); - p->pe_xscom = ((const uint32_t *)prop->prop)[0]; - p->pe_stk_xscom = ((const uint32_t *)prop->prop)[1]; - p->pci_xscom = ((const uint32_t *)prop->prop)[2]; - p->pci_stk_xscom = ((const uint32_t *)prop->prop)[3]; - p->etu_xscom = ((const uint32_t *)prop->prop)[4]; + p->pe_xscom = be32_to_cpu(((__be32 *)prop->prop)[0]); + p->pe_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[1]); + p->pci_xscom = be32_to_cpu(((__be32 *)prop->prop)[2]); + p->pci_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[3]); + p->etu_xscom = be32_to_cpu(((__be32 *)prop->prop)[4]); /* * We skip the initial PERST assertion requested by the generic code @@ -5769,7 +5779,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint64_t mmio1_bar = 0, mmio1_bmask, mmio1_sz; uint64_t reg[4]; void *foo; - uint64_t mmio_win[4]; + __be64 mmio_win[4]; unsigned int mmio_win_sz; struct dt_node *np; char *path; @@ -5829,13 +5839,13 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, /* Build MMIO windows list */ mmio_win_sz = 0; if (mmio0_bar) { - mmio_win[mmio_win_sz++] = mmio0_bar; - mmio_win[mmio_win_sz++] = mmio0_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_sz); bar_en |= XPEC_NEST_STK_BAR_EN_MMIO0; } if (mmio1_bar) { - mmio_win[mmio_win_sz++] = mmio1_bar; - mmio_win[mmio_win_sz++] = mmio1_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_sz); bar_en |= XPEC_NEST_STK_BAR_EN_MMIO1; } @@ -5865,12 +5875,12 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, prlog_once(PR_DEBUG, "Version reg: 0x%016llx\n", in_be64(foo)); /* Create PHB node */ - reg[0] = phb_bar; - reg[1] = 0x1000; - reg[2] = irq_bar; - reg[3] = 0x10000000; + reg[0] = cpu_to_be64(phb_bar); + reg[1] = cpu_to_be64(0x1000); + reg[2] = cpu_to_be64(irq_bar); + reg[3] = cpu_to_be64(0x10000000); - np = dt_new_addr(dt_root, "pciex", reg[0]); + np = dt_new_addr(dt_root, "pciex", phb_bar); if (!np) return; diff --git a/include/phb4.h b/include/phb4.h index 1c68ec2e2..ca701a311 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -183,7 +183,7 @@ struct phb4 { uint64_t creset_start_time; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:56 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:33 +1000 Message-Id: <20191106121047.14389-16-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 15/29] occ sensors: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert occ sensors dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/occ-sensor.c | 100 ++++++++++++++++++++++++++---------------------- hw/occ.c | 46 +++++++++++----------- include/occ.h | 50 ++++++++++++------------ 3 files changed, 103 insertions(+), 93 deletions(-) diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c index 8434c1930..d269bff84 100644 --- a/hw/occ-sensor.c +++ b/hw/occ-sensor.c @@ -116,7 +116,7 @@ struct occ_sensor_data_header *get_sensor_header_block(int occ_num) static inline struct occ_sensor_name *get_names_block(struct occ_sensor_data_header *hb) { - return ((struct occ_sensor_name *)((u64)hb + hb->names_offset)); + return ((struct occ_sensor_name *)((u64)hb + be32_to_cpu(hb->names_offset))); } static inline u32 sensor_handler(int occ_num, int sensor_id, int attr) @@ -131,11 +131,11 @@ static inline u32 sensor_handler(int occ_num, int sensor_id, int attr) */ static void scale_sensor(struct occ_sensor_name *md, u64 *sensor) { - u32 factor = md->scale_factor; + u32 factor = be32_to_cpu(md->scale_factor); int i; s8 exp; - if (md->type == OCC_SENSOR_TYPE_CURRENT) + if (be16_to_cpu(md->type) == OCC_SENSOR_TYPE_CURRENT) *sensor *= 1000; //convert to mA *sensor *= factor >> 8; @@ -152,7 +152,7 @@ static void scale_sensor(struct occ_sensor_name *md, u64 *sensor) static void scale_energy(struct occ_sensor_name *md, u64 *sensor) { - u32 factor = md->freq; + u32 factor = be32_to_cpu(md->freq); int i; s8 exp; @@ -174,17 +174,17 @@ static u64 read_sensor(struct occ_sensor_record *sensor, int attr) { switch (attr) { case SENSOR_SAMPLE: - return sensor->sample; + return be16_to_cpu(sensor->sample); case SENSOR_SAMPLE_MIN: - return sensor->sample_min; + return be16_to_cpu(sensor->sample_min); case SENSOR_SAMPLE_MAX: - return sensor->sample_max; + return be16_to_cpu(sensor->sample_max); case SENSOR_CSM_MIN: - return sensor->csm_min; + return be16_to_cpu(sensor->csm_min); case SENSOR_CSM_MAX: - return sensor->csm_max; + return be16_to_cpu(sensor->csm_max); case SENSOR_ACCUMULATOR: - return sensor->accumulator; + return be64_to_cpu(sensor->accumulator); default: break; } @@ -197,14 +197,16 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) struct occ_sensor_name *md; u8 *ping, *pong; void *buffer = NULL; + u32 reading_offset; if (!hb) return NULL; md = get_names_block(hb); - ping = (u8 *)((u64)hb + hb->reading_ping_offset); - pong = (u8 *)((u64)hb + hb->reading_pong_offset); + ping = (u8 *)((u64)hb + be32_to_cpu(hb->reading_ping_offset)); + pong = (u8 *)((u64)hb + be32_to_cpu(hb->reading_pong_offset)); + reading_offset = be32_to_cpu(md[id].reading_offset); /* Check which buffer is valid and read the data from that. * Ping Pong Action @@ -216,11 +218,11 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) if (*ping && *pong) { u64 tping, tpong; - u64 ping_buf = (u64)ping + md[id].reading_offset; - u64 pong_buf = (u64)pong + md[id].reading_offset; + u64 ping_buf = (u64)ping + reading_offset; + u64 pong_buf = (u64)pong + reading_offset; - tping = ((struct occ_sensor_record *)ping_buf)->timestamp; - tpong = ((struct occ_sensor_record *)pong_buf)->timestamp; + tping = be64_to_cpu(((struct occ_sensor_record *)ping_buf)->timestamp); + tpong = be64_to_cpu(((struct occ_sensor_record *)pong_buf)->timestamp); if (tping > tpong) buffer = ping; @@ -236,7 +238,7 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) } assert(buffer); - buffer = (void *)((u64)buffer + md[id].reading_offset); + buffer = (void *)((u64)buffer + reading_offset); return buffer; } @@ -264,7 +266,7 @@ int occ_sensor_read(u32 handle, u64 *data) if (hb->valid != 1) return OPAL_HARDWARE; - if (id > hb->nr_sensors) + if (id > be16_to_cpu(hb->nr_sensors)) return OPAL_PARAMETER; buff = select_sensor_buffer(hb, id); @@ -276,7 +278,7 @@ int occ_sensor_read(u32 handle, u64 *data) return OPAL_SUCCESS; md = get_names_block(hb); - if (md[id].type == OCC_SENSOR_TYPE_POWER && attr == SENSOR_ACCUMULATOR) + if (be16_to_cpu(md[id].type) == OCC_SENSOR_TYPE_POWER && attr == SENSOR_ACCUMULATOR) scale_energy(&md[id], data); else scale_sensor(&md[id], data); @@ -320,7 +322,8 @@ static bool occ_sensor_sanity(struct occ_sensor_data_header *hb, int chipid) return false; } - if (!hb->names_offset || !hb->reading_ping_offset || + if (!hb->names_offset || + !hb->reading_ping_offset || !hb->reading_pong_offset) { prerror("OCC: Chip %d Invalid sensor buffer pointers\n", chipid); @@ -357,9 +360,10 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, { char sname[30] = ""; char prefix[30] = ""; + uint16_t location = be16_to_cpu(md->location); int i; - if (md->location != OCC_SENSOR_LOC_SYSTEM) + if (location != OCC_SENSOR_LOC_SYSTEM) snprintf(prefix, sizeof(prefix), "%s %d ", "Chip", chipid); for (i = 0; i < ARRAY_SIZE(str_maps); i++) @@ -368,7 +372,7 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, char *end; int num = -1; - if (md->location != OCC_SENSOR_LOC_CORE) + if (location != OCC_SENSOR_LOC_CORE) num = parse_entity(md->name, &end); if (num != -1) { @@ -384,7 +388,7 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, } /* Fallback to OCC literal if mapping is not found */ - if (md->location == OCC_SENSOR_LOC_SYSTEM) { + if (location == OCC_SENSOR_LOC_SYSTEM) { dt_add_property_string(node, "label", md->name); } else { snprintf(sname, sizeof(sname), "%s%s", prefix, md->name); @@ -444,15 +448,15 @@ static bool check_sensor_sample(struct occ_sensor_data_header *hb, u32 offset) { struct occ_sensor_record *ping, *pong; - ping = (struct occ_sensor_record *)((u64)hb + hb->reading_ping_offset - + offset); - pong = (struct occ_sensor_record *)((u64)hb + hb->reading_pong_offset - + offset); + ping = (struct occ_sensor_record *)((u64)hb + + be32_to_cpu(hb->reading_ping_offset) + offset); + pong = (struct occ_sensor_record *)((u64)hb + + be32_to_cpu(hb->reading_pong_offset) + offset); return ping->sample || pong->sample; } static void add_sensor_node(const char *loc, const char *type, int i, int attr, - struct occ_sensor_name *md, u32 *phandle, u32 *ptype, + struct occ_sensor_name *md, __be32 *phandle, u32 *ptype, u32 pir, u32 occ_num, u32 chipid) { char name[30]; @@ -468,10 +472,10 @@ static void add_sensor_node(const char *loc, const char *type, int i, int attr, dt_add_property_string(node, "occ_label", md->name); add_sensor_label(node, md, chipid); - if (md->location == OCC_SENSOR_LOC_CORE) + if (be16_to_cpu(md->location) == OCC_SENSOR_LOC_CORE) dt_add_property_cells(node, "ibm,pir", pir); - *ptype = md->type; + *ptype = be16_to_cpu(md->type); if (attr == SENSOR_SAMPLE) { handler = sensor_handler(occ_num, i, SENSOR_CSM_MAX); @@ -482,7 +486,7 @@ static void add_sensor_node(const char *loc, const char *type, int i, int attr, } dt_add_property_string(node, "compatible", "ibm,opal-sensor"); - *phandle = node->phandle; + *phandle = cpu_to_be32(node->phandle); } bool occ_sensors_init(void) @@ -520,7 +524,9 @@ bool occ_sensors_init(void) for_each_chip(chip) { struct occ_sensor_data_header *hb; struct occ_sensor_name *md; - u32 *phandles, *ptype, phcount = 0; + __be32 *phandles; + u32 *ptype, phcount = 0; + unsigned int nr_sensors; hb = get_sensor_header_block(occ_num); md = get_names_block(hb); @@ -529,30 +535,34 @@ bool occ_sensors_init(void) if (!occ_sensor_sanity(hb, chip->id)) continue; - phandles = malloc(hb->nr_sensors * sizeof(u32)); + nr_sensors = be16_to_cpu(hb->nr_sensors); + + phandles = malloc(nr_sensors * sizeof(__be32)); assert(phandles); - ptype = malloc(hb->nr_sensors * sizeof(u32)); + ptype = malloc(nr_sensors * sizeof(u32)); assert(ptype); - for (i = 0; i < hb->nr_sensors; i++) { - const char *type, *loc; + for (i = 0; i < nr_sensors; i++) { + const char *type_name, *loc; struct cpu_thread *c = NULL; uint32_t pir = 0; + uint16_t type = be16_to_cpu(md[i].type); + uint16_t location = be16_to_cpu(md[i].location); if (md[i].structure_type != OCC_SENSOR_READING_FULL) continue; - if (!(md[i].type & HWMON_SENSORS_MASK)) + if (!(type & HWMON_SENSORS_MASK)) continue; - if (md[i].location == OCC_SENSOR_LOC_GPU && !has_gpu) + if (location == OCC_SENSOR_LOC_GPU && !has_gpu) continue; - if (md[i].type == OCC_SENSOR_TYPE_POWER && - !check_sensor_sample(hb, md[i].reading_offset)) + if (type == OCC_SENSOR_TYPE_POWER && + !check_sensor_sample(hb, be32_to_cpu(md[i].reading_offset))) continue; - if (md[i].location == OCC_SENSOR_LOC_CORE) { + if (location == OCC_SENSOR_LOC_CORE) { int num = parse_entity(md[i].name, NULL); for_each_available_core_in_chip(c, chip->id) @@ -563,16 +573,16 @@ bool occ_sensors_init(void) pir = c->pir; } - type = get_sensor_type_string(md[i].type); - loc = get_sensor_loc_string(md[i].location); + type_name = get_sensor_type_string(type); + loc = get_sensor_loc_string(location); - add_sensor_node(loc, type, i, SENSOR_SAMPLE, &md[i], + add_sensor_node(loc, type_name, i, SENSOR_SAMPLE, &md[i], &phandles[phcount], &ptype[phcount], pir, occ_num, chip->id); phcount++; /* Add energy sensors */ - if (md[i].type == OCC_SENSOR_TYPE_POWER && + if (type == OCC_SENSOR_TYPE_POWER && md[i].structure_type == OCC_SENSOR_READING_FULL) { add_sensor_node(loc, "energy", i, SENSOR_ACCUMULATOR, &md[i], diff --git a/hw/occ.c b/hw/occ.c index db2744ff7..65bd425a0 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -97,7 +97,7 @@ struct occ_pstate_table { u8 flags; u8 vdd; u8 vcs; - u32 freq_khz; + __be32 freq_khz; } pstates[MAX_PSTATES]; s8 core_max[MAX_P8_CORES]; u8 pad[100]; @@ -115,7 +115,7 @@ struct occ_pstate_table { u8 id; u8 flags; u16 reserved; - u32 freq_khz; + __be32 freq_khz; } pstates[MAX_PSTATES]; u8 core_max[MAX_P9_CORES]; u8 pad[56]; @@ -375,7 +375,7 @@ static bool wait_for_all_occ_init(void) chip->occ_functional = true; prlog(PR_DEBUG, "OCC: Chip %02x Data (%016llx) = %016llx\n", - chip->id, (uint64_t)occ_data, *(uint64_t *)occ_data); + chip->id, (uint64_t)occ_data, be64_to_cpu(*(__be64 *)occ_data)); } end_time = mftb(); prlog(PR_NOTICE, "OCC: All Chip Rdy after %lu ms\n", @@ -398,8 +398,8 @@ static bool wait_for_all_occ_init(void) * the list and break from the loop as this is the last valid * element in the pstate table. */ -static void parse_pstates_v2(struct occ_pstate_table *data, u32 *dt_id, - u32 *dt_freq, int nr_pstates, int pmax, int pmin) +static void parse_pstates_v2(struct occ_pstate_table *data, __be32 *dt_id, + __be32 *dt_freq, int nr_pstates, int pmax, int pmin) { int i, j; @@ -407,8 +407,8 @@ static void parse_pstates_v2(struct occ_pstate_table *data, u32 *dt_id, if (cmp_pstates(data->v2.pstates[i].id, pmax) > 0) continue; - dt_id[j] = data->v2.pstates[i].id; - dt_freq[j] = data->v2.pstates[i].freq_khz / 1000; + dt_id[j] = cpu_to_be32(data->v2.pstates[i].id); + dt_freq[j] = cpu_to_be32(be32_to_cpu(data->v2.pstates[i].freq_khz) / 1000); j++; if (data->v2.pstates[i].id == pmin) @@ -420,8 +420,8 @@ static void parse_pstates_v2(struct occ_pstate_table *data, u32 *dt_id, nr_pstates, j); } -static void parse_pstates_v9(struct occ_pstate_table *data, u32 *dt_id, - u32 *dt_freq, int nr_pstates, int pmax, int pmin) +static void parse_pstates_v9(struct occ_pstate_table *data, __be32 *dt_id, + __be32 *dt_freq, int nr_pstates, int pmax, int pmin) { int i, j; @@ -429,8 +429,8 @@ static void parse_pstates_v9(struct occ_pstate_table *data, u32 *dt_id, if (cmp_pstates(data->v9.pstates[i].id, pmax) > 0) continue; - dt_id[j] = data->v9.pstates[i].id; - dt_freq[j] = data->v9.pstates[i].freq_khz / 1000; + dt_id[j] = cpu_to_be32(data->v9.pstates[i].id); + dt_freq[j] = cpu_to_be32(be32_to_cpu(data->v9.pstates[i].freq_khz) / 1000); j++; if (data->v9.pstates[i].id == pmin) @@ -482,7 +482,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, uint64_t occ_data_area; struct occ_pstate_table *occ_data; /* Arrays for device tree */ - u32 *dt_id, *dt_freq; + __be32 *dt_id, *dt_freq; int pmax, pmin, pnom; u8 nr_pstates; bool ultra_turbo_supported; @@ -500,8 +500,8 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, occ_data_area = (uint64_t)occ_data; prlog(PR_DEBUG, "OCC: Data (%16llx) = %16llx %16llx\n", occ_data_area, - *(uint64_t *)occ_data_area, - *(uint64_t *)(occ_data_area + 8)); + be64_to_cpu(*(__be64 *)occ_data_area), + be64_to_cpu(*(__be64 *)(occ_data_area + 8))); if (!occ_data->valid) { /** @@ -629,9 +629,9 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, return false; } - dt_id = malloc(nr_pstates * sizeof(u32)); + dt_id = malloc(nr_pstates * sizeof(__be32)); assert(dt_id); - dt_freq = malloc(nr_pstates * sizeof(u32)); + dt_freq = malloc(nr_pstates * sizeof(__be32)); assert(dt_freq); switch (major) { @@ -649,9 +649,9 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, /* Add the device-tree entries */ dt_add_property(power_mgt, "ibm,pstate-ids", dt_id, - nr_pstates * sizeof(u32)); + nr_pstates * sizeof(__be32)); dt_add_property(power_mgt, "ibm,pstate-frequencies-mhz", dt_freq, - nr_pstates * sizeof(u32)); + nr_pstates * sizeof(__be32)); dt_add_property_cells(power_mgt, "ibm,pstate-min", pmin); dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom); dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax); @@ -667,7 +667,7 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, if (ultra_turbo_supported) { int pturbo, pultra_turbo; u8 nr_cores = get_available_nr_cores_in_chip(chip->id); - u32 *dt_cmax; + __be32 *dt_cmax; dt_cmax = malloc(nr_cores * sizeof(u32)); assert(dt_cmax); @@ -676,13 +676,13 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, pturbo = occ_data->v2.pstate_turbo; pultra_turbo = occ_data->v2.pstate_ultra_turbo; for (i = 0; i < nr_cores; i++) - dt_cmax[i] = occ_data->v2.core_max[i]; + dt_cmax[i] = cpu_to_be32(occ_data->v2.core_max[i]); break; case 0x9: pturbo = occ_data->v9.pstate_turbo; pultra_turbo = occ_data->v9.pstate_ultra_turbo; for (i = 0; i < nr_cores; i++) - dt_cmax[i] = occ_data->v9.core_max[i]; + dt_cmax[i] = cpu_to_be32(occ_data->v9.core_max[i]); break; default: return false; @@ -1600,7 +1600,7 @@ int occ_sensor_group_enable(u32 group_hndl, int token, bool enable) return opal_occ_command(&chips[i], token, &sensor_mask_data); } -void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, u32 *ptype, +void occ_add_sensor_groups(struct dt_node *sg, __be32 *phandles, u32 *ptype, int nr_phandles, int chipid) { struct group_info { @@ -1687,7 +1687,7 @@ void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, u32 *ptype, dt_add_property_cells(node, "ibm,chip-id", chipid); dt_add_property_cells(node, "reg", handle); if (groups[j].ops == OPAL_SENSOR_GROUP_ENABLE) { - u32 *_phandles; + __be32 *_phandles; int k, pcount = 0; _phandles = malloc(sizeof(u32) * nr_phandles); diff --git a/include/occ.h b/include/occ.h index 0030af5ae..f3b8f6a9a 100644 --- a/include/occ.h +++ b/include/occ.h @@ -34,7 +34,7 @@ bool occ_get_gpu_presence(struct proc_chip *chip, int gpu_num); extern bool occ_sensors_init(void); extern int occ_sensor_read(u32 handle, u64 *data); extern int occ_sensor_group_clear(u32 group_hndl, int token); -extern void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, +extern void occ_add_sensor_groups(struct dt_node *sg, __be32 *phandles, u32 *ptype, int nr_phandles, int chipid); extern int occ_sensor_group_enable(u32 group_hndl, int token, bool enable); @@ -186,15 +186,15 @@ enum sensor_struct_type { struct occ_sensor_data_header { u8 valid; u8 version; - u16 nr_sensors; + __be16 nr_sensors; u8 reading_version; u8 pad[3]; - u32 names_offset; + __be32 names_offset; u8 names_version; u8 name_length; u16 reserved; - u32 reading_ping_offset; - u32 reading_pong_offset; + __be32 reading_ping_offset; + __be32 reading_pong_offset; } __attribute__((__packed__)); /** @@ -220,13 +220,13 @@ struct occ_sensor_data_header { struct occ_sensor_name { char name[MAX_CHARS_SENSOR_NAME]; char units[MAX_CHARS_SENSOR_UNIT]; - u16 gsid; - u32 freq; - u32 scale_factor; - u16 type; - u16 location; + __be16 gsid; + __be32 freq; + __be32 scale_factor; + __be16 type; + __be16 location; u8 structure_type; - u32 reading_offset; + __be32 reading_offset; u8 sensor_data; u8 pad[8]; } __attribute__((__packed__)); @@ -258,18 +258,18 @@ struct occ_sensor_name { */ struct occ_sensor_record { u16 gsid; - u64 timestamp; - u16 sample; - u16 sample_min; - u16 sample_max; - u16 csm_min; - u16 csm_max; - u16 profiler_min; - u16 profiler_max; - u16 job_scheduler_min; - u16 job_scheduler_max; - u64 accumulator; - u32 update_tag; + __be64 timestamp; + __be16 sample; + __be16 sample_min; + __be16 sample_max; + __be16 csm_min; + __be16 csm_max; + __be16 profiler_min; + __be16 profiler_max; + __be16 job_scheduler_min; + __be16 job_scheduler_max; + __be64 accumulator; + __be32 update_tag; u8 pad[8]; } __attribute__((__packed__)); @@ -284,8 +284,8 @@ struct occ_sensor_record { */ struct occ_sensor_counter { u16 gsid; - u64 timestamp; - u64 accumulator; + __be64 timestamp; + __be64 accumulator; u8 sample; u8 pad[5]; } __attribute__((__packed__)); From patchwork Wed Nov 6 12:10:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QYs28Lxz9sNx for ; Wed, 6 Nov 2019 23:18:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:11:58 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:34 +1000 Message-Id: <20191106121047.14389-17-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 16/29] memconsole: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert memconsole dt construction and in-memory tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- core/console.c | 22 +++++++++++----------- include/console.h | 16 ++++++++-------- platforms/ibm-fsp/common.c | 4 ++-- platforms/ibm-fsp/hostservices.c | 12 ++++++------ 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/core/console.c b/core/console.c index ac88f0c71..030c1d918 100644 --- a/core/console.c +++ b/core/console.c @@ -30,11 +30,11 @@ static struct lock con_lock = LOCK_UNLOCKED; /* This is mapped via TCEs so we keep it alone in a page */ struct memcons memcons __section(".data.memcons") = { - .magic = MEMCONS_MAGIC, - .obuf_phys = INMEM_CON_START, - .ibuf_phys = INMEM_CON_START + INMEM_CON_OUT_LEN, - .obuf_size = INMEM_CON_OUT_LEN, - .ibuf_size = INMEM_CON_IN_LEN, + .magic = CPU_TO_BE64(MEMCONS_MAGIC), + .obuf_phys = CPU_TO_BE64(INMEM_CON_START), + .ibuf_phys = CPU_TO_BE64(INMEM_CON_START + INMEM_CON_OUT_LEN), + .obuf_size = CPU_TO_BE32(INMEM_CON_OUT_LEN), + .ibuf_size = CPU_TO_BE32(INMEM_CON_IN_LEN), }; static bool dummy_console_enabled(void) @@ -197,7 +197,7 @@ static void inmem_write(char c) if (con_wrapped) opos |= MEMCONS_OUT_POS_WRAP; lwsync(); - memcons.out_pos = opos; + memcons.out_pos = cpu_to_be32(opos); /* If head reaches tail, push tail around & drop chars */ if (con_in == con_out) @@ -207,12 +207,12 @@ static void inmem_write(char c) static size_t inmem_read(char *buf, size_t req) { size_t read = 0; - char *ibuf = (char *)memcons.ibuf_phys; + char *ibuf = (char *)be64_to_cpu(memcons.ibuf_phys); - while (req && memcons.in_prod != memcons.in_cons) { - *(buf++) = ibuf[memcons.in_cons]; + while (req && be32_to_cpu(memcons.in_prod) != be32_to_cpu(memcons.in_cons)) { + *(buf++) = ibuf[be32_to_cpu(memcons.in_cons)]; lwsync(); - memcons.in_cons = (memcons.in_cons + 1) % INMEM_CON_IN_LEN; + memcons.in_cons = cpu_to_be32((be32_to_cpu(memcons.in_cons) + 1) % INMEM_CON_IN_LEN); req--; read++; } @@ -428,7 +428,7 @@ void dummy_console_add_nodes(void) { struct dt_property *p; - add_opal_console_node(0, "raw", memcons.obuf_size); + add_opal_console_node(0, "raw", be32_to_cpu(memcons.obuf_size)); /* Mambo might have left a crap one, clear it */ p = __dt_find_property(dt_chosen, "linux,stdout-path"); diff --git a/include/console.h b/include/console.h index 230b825b0..61448e28e 100644 --- a/include/console.h +++ b/include/console.h @@ -14,17 +14,17 @@ * (This is v3 of the format, the previous one sucked) */ struct memcons { - uint64_t magic; + __be64 magic; #define MEMCONS_MAGIC 0x6630696567726173LL - uint64_t obuf_phys; - uint64_t ibuf_phys; - uint32_t obuf_size; - uint32_t ibuf_size; - uint32_t out_pos; + __be64 obuf_phys; + __be64 ibuf_phys; + __be32 obuf_size; + __be32 ibuf_size; + __be32 out_pos; #define MEMCONS_OUT_POS_WRAP 0x80000000u #define MEMCONS_OUT_POS_MASK 0x00ffffffu - uint32_t in_prod; - uint32_t in_cons; + __be32 in_prod; + __be32 in_cons; }; extern struct memcons memcons; diff --git a/platforms/ibm-fsp/common.c b/platforms/ibm-fsp/common.c index a0339ec25..edb60eb4a 100644 --- a/platforms/ibm-fsp/common.c +++ b/platforms/ibm-fsp/common.c @@ -25,9 +25,9 @@ static void map_debug_areas(void) fsp_tce_map(PSI_DMA_LOG_BUF, (void*)INMEM_CON_START, INMEM_CON_LEN); debug_descriptor.memcons_tce = PSI_DMA_MEMCONS; - t = memcons.obuf_phys - INMEM_CON_START + PSI_DMA_LOG_BUF; + t = be64_to_cpu(memcons.obuf_phys) - INMEM_CON_START + PSI_DMA_LOG_BUF; debug_descriptor.memcons_obuf_tce = t; - t = memcons.ibuf_phys - INMEM_CON_START + PSI_DMA_LOG_BUF; + t = be64_to_cpu(memcons.ibuf_phys) - INMEM_CON_START + PSI_DMA_LOG_BUF; debug_descriptor.memcons_ibuf_tce = t; /* We only have space in the TCE table for the trace diff --git a/platforms/ibm-fsp/hostservices.c b/platforms/ibm-fsp/hostservices.c index c1824d85b..8ef492df6 100644 --- a/platforms/ibm-fsp/hostservices.c +++ b/platforms/ibm-fsp/hostservices.c @@ -178,11 +178,11 @@ static bool hbrt_con_wrapped; #define HBRT_CON_OUT_LEN (HBRT_CON_LEN - HBRT_CON_IN_LEN) static struct memcons hbrt_memcons __section(".data.memcons") = { - .magic = MEMCONS_MAGIC, - .obuf_phys = HBRT_CON_START, - .ibuf_phys = HBRT_CON_START + HBRT_CON_OUT_LEN, - .obuf_size = HBRT_CON_OUT_LEN, - .ibuf_size = HBRT_CON_IN_LEN, + .magic = CPU_TO_BE64(MEMCONS_MAGIC), + .obuf_phys = CPU_TO_BE64(HBRT_CON_START), + .ibuf_phys = CPU_TO_BE64(HBRT_CON_START + HBRT_CON_OUT_LEN), + .obuf_size = CPU_TO_BE32(HBRT_CON_OUT_LEN), + .ibuf_size = CPU_TO_BE32(HBRT_CON_IN_LEN), }; static void hservice_putc(char c) @@ -206,7 +206,7 @@ static void hservice_putc(char c) if (hbrt_con_wrapped) opos |= MEMCONS_OUT_POS_WRAP; lwsync(); - hbrt_memcons.out_pos = opos; + hbrt_memcons.out_pos = cpu_to_be32(opos); } static void hservice_puts(const char *str) From patchwork Wed Nov 6 12:10:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QZW3vznz9sNx for ; Wed, 6 Nov 2019 23:19:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:01 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:35 +1000 Message-Id: <20191106121047.14389-18-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 17/29] ipmi: endian conversion X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hw/ipmi/ipmi-sel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ipmi/ipmi-sel.c b/hw/ipmi/ipmi-sel.c index 794aa3801..a774fb401 100644 --- a/hw/ipmi/ipmi-sel.c +++ b/hw/ipmi/ipmi-sel.c @@ -192,7 +192,7 @@ static void ipmi_init_esel_record(void) { memset(&sel_record, 0, sizeof(struct sel_record)); sel_record.record_type = SEL_REC_TYPE_AMI_ESEL; - sel_record.generator_id = SEL_GENERATOR_ID_AMI; + sel_record.generator_id = cpu_to_le16(SEL_GENERATOR_ID_AMI); sel_record.evm_ver = SEL_EVM_VER_2; sel_record.sensor_type = SENSOR_TYPE_SYS_EVENT; sel_record.sensor_number = From patchwork Wed Nov 6 12:10:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qb83G4rz9sNx for ; Wed, 6 Nov 2019 23:20:04 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:04 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:36 +1000 Message-Id: <20191106121047.14389-19-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 18/29] sbe-p9: endian conversion X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin Reviewed-by: Vasant Hegde --- hw/sbe-p9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index 1b5f29ec1..53f378e18 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -123,7 +123,7 @@ static u64 p9_sbe_rreg(u32 chip_id, u64 reg) return 0xffffffff; } - return be64_to_cpu(data); + return data; } static void p9_sbe_reg_dump(u32 chip_id) From patchwork Wed Nov 6 12:10:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qbh0RjQz9sNx for ; Wed, 6 Nov 2019 23:20:32 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jeuKb/NR"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477Qbg5Yr8zF69j for ; Wed, 6 Nov 2019 23:20:31 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::543; helo=mail-pg1-x543.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jeuKb/NR"; dkim-atps=neutral Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QQ12kmNzF5vn for ; Wed, 6 Nov 2019 23:12:09 +1100 (AEDT) Received: by mail-pg1-x543.google.com with SMTP id k13so5691982pgh.3 for ; Wed, 06 Nov 2019 04:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mHy+oliLH18Dm3l3Nmhknw3vMHrgJQtghOWSg2ORkNo=; b=jeuKb/NR9FlKC4TZrhrt98x8VThn2Q7qkmwoku5GucmF0BfqJIuqO9W1xECeIv2crR 1ETcKgKjJ7T6AQBlida4stosHzGtFQ1HAPOW/lzkxgHCs0x/Us81Yu34Z/Apjf/sdNiW sTkzvvXDAbZXHbT1WgoModHKd78P9r8qrxVGs3B05AW9mw2ra4r8DAObGd1ueInNOxhx Fl0MyyCYjvxdC4Iaw/7rlc6NwdKVIevo83CNPZdLOnxUM4jxrjqfRNzJNMImWxFluJTF o1AptXX5U8njT6OwqeFJ87fwNRgpe8PdEZikaR1Ib6hpFuj+Xbam3P4jtNj7eNSGPLnQ ZeVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mHy+oliLH18Dm3l3Nmhknw3vMHrgJQtghOWSg2ORkNo=; b=YTNeCoyNIWqAVyMhzr+l8SVnE5crB306kKi648A5SHkyuFD8lNIiJajRvXqomLXyqy v1QhJECVQe+iFv1ubN8Mitg9/pELlyzntB9TRCijf/ywOpfzGclOKQXP53G1Ch0Kah08 JF0H3Pl6gSnfPmk7MEnIkRHriON8Med30GTxVGNpRy1WhksoIbih4E+gNFExAkJLfCzx uDWNxWrT/XonA1QSLuOhSKFzxdqra2NdgjgPyRMRZQrmBiyYBUTDh/fQZDyrUzCViDij Wa2CTDX6WWkRgqhOQTc6Coge+7YJZsETG6XS4OIPJfD31KgMBROjt3+4EutTF0eKtDUF 8oUg== X-Gm-Message-State: APjAAAULxP8ger5706vl27RXxkeLUvAbIqa9iZqI9mtEdp7i7iQHjXag 4BrupPoiyQQ/tzn7aOjzZEEMKWdD0oc= X-Google-Smtp-Source: APXvYqylOiZmutoBKDJr3k0HJhleg6El6FJy8pNJD7TY7nWM5eFbg8hBnPFIBmWY/NmFz5JLcndn8g== X-Received: by 2002:a63:fe16:: with SMTP id p22mr2493711pgh.318.1573042327232; Wed, 06 Nov 2019 04:12:07 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:06 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:37 +1000 Message-Id: <20191106121047.14389-20-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 19/29] fsp: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin Reviewed-by: Vasant Hegde --- hw/fsp/fsp-codeupdate.c | 4 +- hw/fsp/fsp-codeupdate.h | 86 ++++++++++++++++++++--------------------- hw/fsp/fsp-sysdump.c | 2 +- hw/fsp/fsp-sysparam.c | 2 +- hw/fsp/fsp.c | 16 ++++---- 5 files changed, 55 insertions(+), 55 deletions(-) diff --git a/hw/fsp/fsp-codeupdate.c b/hw/fsp/fsp-codeupdate.c index 67732a739..7e58cebeb 100644 --- a/hw/fsp/fsp-codeupdate.c +++ b/hw/fsp/fsp-codeupdate.c @@ -783,7 +783,7 @@ static int validate_candidate_image(uint64_t buffer, memcpy(validate_buf, (void *)buffer, VALIDATE_BUF_SIZE); header = (struct update_image_header *)validate_buf; - if (validate_magic_num(be32_to_cpu(header->magic)) != 0) { + if (validate_magic_num(be16_to_cpu(header->magic)) != 0) { *result = VALIDATE_INVALID_IMG; rc = OPAL_SUCCESS; goto out; @@ -1125,7 +1125,7 @@ static int64_t validate_sglist(struct opal_sg_list *list) return OPAL_PARAMETER; /* All non-terminal entries size must be aligned */ - if (prev_entry && (prev_entry->length & 0xfff)) + if (prev_entry && (be64_to_cpu(prev_entry->length) & 0xfff)) return OPAL_PARAMETER; prev_entry = entry; diff --git a/hw/fsp/fsp-codeupdate.h b/hw/fsp/fsp-codeupdate.h index 237043c8e..0262c69ce 100644 --- a/hw/fsp/fsp-codeupdate.h +++ b/hw/fsp/fsp-codeupdate.h @@ -76,17 +76,17 @@ struct fw_image_vpd { struct master_lid_header { char key[3]; /* "MLH" */ uint8_t version; /* 0x02 */ - uint16_t header_size; - uint16_t entry_size; + __be16 header_size; + __be16 entry_size; uint8_t reserved[56]; }; /* LID index entry */ struct lid_index_entry { - uint32_t id; - uint32_t size; - uint32_t offset; - uint32_t crc; + __be32 id; + __be32 size; + __be32 offset; + __be32 crc; }; /* SP flags */ @@ -99,7 +99,7 @@ struct lid_index_entry { * sp_flag addr = header->data + header->ext_fw_id_size */ struct update_image_ga_date { - uint32_t sp_flag; + __be32 sp_flag; char sp_ga_date[8]; /* YYYYMMDD */ }; @@ -108,39 +108,39 @@ struct update_image_ga_date { /* Image header structure */ struct update_image_header { - uint16_t magic; - uint16_t version; - uint32_t package_size; - uint32_t crc; - uint16_t lid_index_offset; - uint16_t number_lids; - uint16_t package_flags; - uint16_t mi_keyword_size; + __be16 magic; + __be16 version; + __be32 package_size; + __be32 crc; + __be16 lid_index_offset; + __be16 number_lids; + __be16 package_flags; + __be16 mi_keyword_size; char mi_keyword_data[40]; - uint16_t ext_fw_id_size; + __be16 ext_fw_id_size; /* Rest of the image data including ext fw id, sp flags */ char data[]; }; /* FipS header */ struct fips_header { - uint16_t magic; - uint16_t version; - uint32_t lid_id; - uint32_t lid_date; /* YYYYMMDD */ - uint16_t lid_time; /* HHMM */ - uint16_t lid_class; - uint32_t crc; - uint32_t lid_size; /* Number of bytes below header */ - uint32_t header_size; + __be16 magic; + __be16 version; + __be32 lid_id; + __be32 lid_date; /* YYYYMMDD */ + __be16 lid_time; /* HHMM */ + __be16 lid_class; + __be32 crc; + __be32 lid_size; /* Number of bytes below header */ + __be32 header_size; uint8_t mtd_number; uint8_t valid; /* 1 = valid, 0 = invalid */ uint8_t reserved; uint8_t lid_info_size; char lid_info[64]; /* code level */ - uint32_t update_date; /* YYYYMMDD */ - uint16_t update_time; /* HHMM */ - uint16_t phylum_len; + __be32 update_date; /* YYYYMMDD */ + __be16 update_time; /* HHMM */ + __be16 phylum_len; uint8_t lid_phylum[]; }; @@ -165,30 +165,30 @@ struct fips_header { * not all ADF sections in common marker LID. */ struct com_marker_header { - uint32_t version; - uint32_t MI_offset; /* Offset to MI section */ - uint32_t iseries_offset; + __be32 version; + __be32 MI_offset; /* Offset to MI section */ + __be32 iseries_offset; }; /* MI Keyword section */ struct com_marker_mi_section { - uint32_t MI_size; + __be32 MI_size; char mi_keyword[40]; /* MI Keyword */ char lst_disrupt_fix_lvl[3]; char skip[21]; /* Skip not interested fields */ - uint32_t adf_offset; /* Offset to ADF section */ + __be32 adf_offset; /* Offset to ADF section */ }; /* Additional Data Fields */ struct com_marker_adf_sec { - uint32_t adf_cnt; /* ADF count */ + __be32 adf_cnt; /* ADF count */ char adf_data[]; /* ADF data */ }; /* ADF common header */ struct com_marker_adf_header { - uint32_t size; /* Section size */ - uint32_t name; /* Section name */ + __be32 size; /* Section size */ + __be32 name; /* Section name */ }; /* @@ -200,9 +200,9 @@ struct com_marker_adf_header { struct com_marker_adf_sp { struct com_marker_adf_header header; - uint32_t sp_name_offset; /* Offset from start of ADF */ - uint32_t sp_name_size; - uint32_t skip[4]; /* Skip rest of fields */ + __be32 sp_name_offset; /* Offset from start of ADF */ + __be32 sp_name_size; + __be32 skip[4]; /* Skip rest of fields */ }; /* @@ -213,10 +213,10 @@ struct com_marker_adf_sp #define ADF_NAME_FW_IP 0x46495050 /* FIPP */ struct com_marker_fw_ip { struct com_marker_adf_header header; - uint32_t sp_flag_offset; /* Offset from start of ADF */ - uint32_t sp_flag_size; - uint32_t sp_ga_offset; /* Offset from start of ADF*/ - uint32_t sp_ga_size; + __be32 sp_flag_offset; /* Offset from start of ADF */ + __be32 sp_flag_size; + __be32 sp_ga_offset; /* Offset from start of ADF*/ + __be32 sp_ga_size; }; #endif /* __CODEUPDATE_H */ diff --git a/hw/fsp/fsp-sysdump.c b/hw/fsp/fsp-sysdump.c index cf4af34d1..1a9b46653 100644 --- a/hw/fsp/fsp-sysdump.c +++ b/hw/fsp/fsp-sysdump.c @@ -237,7 +237,7 @@ static int __dump_region_add_entry(uint32_t id, uint64_t addr, uint32_t size) } /* Add entry to dump memory region table */ - dump_mem_region[cur_mdst_entry].data_region = (u8)cpu_to_be32(id); + dump_mem_region[cur_mdst_entry].data_region = (u8)id; dump_mem_region[cur_mdst_entry].addr = cpu_to_be64(addr); dump_mem_region[cur_mdst_entry].size = cpu_to_be32(size); diff --git a/hw/fsp/fsp-sysparam.c b/hw/fsp/fsp-sysparam.c index 0e1e8181f..e30a686d4 100644 --- a/hw/fsp/fsp-sysparam.c +++ b/hw/fsp/fsp-sysparam.c @@ -422,7 +422,7 @@ static void add_opal_sysparam_node(void) { struct dt_node *sysparams; char *names, *s; - uint32_t *ids, *lens; + __be32 *ids, *lens; uint8_t *perms; unsigned int i, count, size = 0; diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 7193c6f4c..c11beb00e 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -181,8 +181,8 @@ static void fsp_trace_msg(struct fsp_msg *msg, u8 dir __unused) size_t len = offsetof(struct trace_fsp_msg, data[msg->dlen]); fsp.fsp_msg.dlen = msg->dlen; - fsp.fsp_msg.word0 = msg->word0; - fsp.fsp_msg.word1 = msg->word1; + fsp.fsp_msg.word0 = cpu_to_be32(msg->word0); + fsp.fsp_msg.word1 = cpu_to_be32(msg->word1); fsp.fsp_msg.dir = dir; memcpy(fsp.fsp_msg.data, msg->data.bytes, msg->dlen); trace_add(&fsp, TRACE_FSP_MSG, len); @@ -634,12 +634,12 @@ static void fsp_trace_event(struct fsp *fsp, u32 evt, #ifdef FSP_TRACE_EVENT size_t len = sizeof(struct trace_fsp_event); - tfsp.fsp_evt.event = evt; - tfsp.fsp_evt.fsp_state = fsp->state; - tfsp.fsp_evt.data[0] = data0; - tfsp.fsp_evt.data[1] = data1; - tfsp.fsp_evt.data[2] = data2; - tfsp.fsp_evt.data[3] = data3; + tfsp.fsp_evt.event = cpu_to_be16(evt); + tfsp.fsp_evt.fsp_state = cpu_to_be16(fsp->state); + tfsp.fsp_evt.data[0] = cpu_to_be32(data0); + tfsp.fsp_evt.data[1] = cpu_to_be32(data1); + tfsp.fsp_evt.data[2] = cpu_to_be32(data2); + tfsp.fsp_evt.data[3] = cpu_to_be32(data3); trace_add(&tfsp, TRACE_FSP_EVENT, len); #endif /* FSP_TRACE_EVENT */ } From patchwork Wed Nov 6 12:10:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QcB2xk3z9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:09 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:38 +1000 Message-Id: <20191106121047.14389-21-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 20/29] libflash: ecc endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- libflash/ecc.c | 36 ++++++++++++++++++++---------------- libflash/ecc.h | 8 ++++---- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/libflash/ecc.c b/libflash/ecc.c index 0b85fb3ea..fde6d8900 100644 --- a/libflash/ecc.c +++ b/libflash/ecc.c @@ -142,30 +142,34 @@ static inline uint64_t eccflipbit(uint64_t data, uint8_t bit) return data ^ (1ul << (63 - bit)); } -static int eccbyte(uint64_t *dst, struct ecc64 *src) +static int eccbyte(beint64_t *dst, struct ecc64 *src) { uint8_t ecc, badbit; uint64_t data; - data = src->data; + data = be64_to_cpu(src->data); ecc = src->ecc; - badbit = eccverify(be64_to_cpu(data), ecc); + badbit = eccverify(data, ecc); if (badbit == UE) { - FL_ERR("ECC: uncorrectable error: %016lx %02x\n", - (long unsigned int)be64_to_cpu(data), ecc); + FL_ERR("ECC: uncorrectable error: %016llx %02x\n", data, ecc); return badbit; } - *dst = data; if (badbit <= UE) FL_INF("ECC: correctable error: %i\n", badbit); if (badbit < 64) - *dst = (uint64_t)be64_to_cpu(eccflipbit(be64_to_cpu(data), - badbit)); + *dst = cpu_to_be64(eccflipbit(data, badbit)); + else + *dst = cpu_to_be64(data); return 0; } +static beint64_t *inc_beint64_by(const void *p, uint64_t i) +{ + return (beint64_t *)(((char *)p) + i); +} + static uint64_t *inc_uint64_by(const void *p, uint64_t i) { return (uint64_t *)(((char *)p) + i); @@ -200,7 +204,7 @@ static uint64_t whole_ecc_structs(uint64_t i) * @retval: 0 - success * @retfal: other - fail */ -int memcpy_from_ecc(uint64_t *dst, struct ecc64 *src, uint64_t len) +int memcpy_from_ecc(beint64_t *dst, struct ecc64 *src, uint64_t len) { uint32_t i; @@ -256,7 +260,7 @@ int memcpy_from_ecc(uint64_t *dst, struct ecc64 *src, uint64_t len) * @retval: 0 - success * @retfal: other - fail */ -int memcpy_from_ecc_unaligned(uint64_t *dst, struct ecc64 *src, +int memcpy_from_ecc_unaligned(beint64_t *dst, struct ecc64 *src, uint64_t len, uint8_t alignment) { char data[BYTES_PER_ECC]; @@ -273,14 +277,14 @@ int memcpy_from_ecc_unaligned(uint64_t *dst, struct ecc64 *src, * required - otherwise jump straight to memcpy_from_ecc() */ if (alignment) { - rc = eccbyte((uint64_t *)data, src); + rc = eccbyte((beint64_t *)data, src); if (rc) return rc; memcpy(dst, &data[alignment], bytes_wanted); src = inc_ecc64_by(src, sizeof(struct ecc64)); - dst = inc_uint64_by(dst, bytes_wanted); + dst = inc_beint64_by(dst, bytes_wanted); len -= bytes_wanted; } @@ -299,7 +303,7 @@ int memcpy_from_ecc_unaligned(uint64_t *dst, struct ecc64 *src, } if (len) { - rc = eccbyte((uint64_t *)data, src); + rc = eccbyte((beint64_t *)data, src); if (rc) return rc; @@ -323,7 +327,7 @@ int memcpy_from_ecc_unaligned(uint64_t *dst, struct ecc64 *src, * @retval: 0 - success * @retfal: other - fail */ -int memcpy_to_ecc(struct ecc64 *dst, const uint64_t *src, uint64_t len) +int memcpy_to_ecc(struct ecc64 *dst, const beint64_t *src, uint64_t len) { struct ecc64 ecc_word; uint64_t i; @@ -390,7 +394,7 @@ int memcpy_to_ecc(struct ecc64 *dst, const uint64_t *src, uint64_t len) * @retfal: other - fail */ -int memcpy_to_ecc_unaligned(struct ecc64 *dst, const uint64_t *src, +int memcpy_to_ecc_unaligned(struct ecc64 *dst, const beint64_t *src, uint64_t len, uint8_t alignment) { struct ecc64 ecc_word; @@ -412,7 +416,7 @@ int memcpy_to_ecc_unaligned(struct ecc64 *dst, const uint64_t *src, sizeof(struct ecc64) - alignment); dst = inc_ecc64_by(dst, sizeof(struct ecc64) - alignment); - src = inc_uint64_by(src, bytes_wanted); + src = inc_beint64_by(src, bytes_wanted); len -= bytes_wanted; } diff --git a/libflash/ecc.h b/libflash/ecc.h index 608d50008..75c3adf22 100644 --- a/libflash/ecc.h +++ b/libflash/ecc.h @@ -16,12 +16,12 @@ struct ecc64 { uint8_t ecc; } __attribute__((__packed__)); -extern int memcpy_from_ecc(uint64_t *dst, struct ecc64 *src, uint64_t len); -extern int memcpy_from_ecc_unaligned(uint64_t *dst, struct ecc64 *src, uint64_t len, +extern int memcpy_from_ecc(beint64_t *dst, struct ecc64 *src, uint64_t len); +extern int memcpy_from_ecc_unaligned(beint64_t *dst, struct ecc64 *src, uint64_t len, uint8_t alignment); -extern int memcpy_to_ecc(struct ecc64 *dst, const uint64_t *src, uint64_t len); -extern int memcpy_to_ecc_unaligned(struct ecc64 *dst, const uint64_t *src, uint64_t len, +extern int memcpy_to_ecc(struct ecc64 *dst, const beint64_t *src, uint64_t len); +extern int memcpy_to_ecc_unaligned(struct ecc64 *dst, const beint64_t *src, uint64_t len, uint8_t alignment); /* From patchwork Wed Nov 6 12:10:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qcb6gdrz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:11 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:39 +1000 Message-Id: <20191106121047.14389-22-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 21/29] prd: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hw/prd.c | 74 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/hw/prd.c b/hw/prd.c index db25985b8..958357e1e 100644 --- a/hw/prd.c +++ b/hw/prd.c @@ -84,7 +84,7 @@ static void prd_msg_consumed(void *data, int status) lock(&events_lock); switch (msg->hdr.type) { case OPAL_PRD_MSG_TYPE_ATTN: - proc = msg->attn.proc; + proc = be64_to_cpu(msg->attn.proc); /* If other ipoll events have been received in the time * between prd_msg creation and consumption, we'll need to @@ -92,17 +92,17 @@ static void prd_msg_consumed(void *data, int status) * clear the event if we don't have any further ipoll_status * bits. */ - ipoll_status[proc] &= ~msg->attn.ipoll_status; + ipoll_status[proc] &= ~be64_to_cpu(msg->attn.ipoll_status); if (!ipoll_status[proc]) event = EVENT_ATTN; break; case OPAL_PRD_MSG_TYPE_OCC_ERROR: - proc = msg->occ_error.chip; + proc = be64_to_cpu(msg->occ_error.chip); event = EVENT_OCC_ERROR; break; case OPAL_PRD_MSG_TYPE_OCC_RESET: - proc = msg->occ_reset.chip; + proc = be64_to_cpu(msg->occ_reset.chip); event = EVENT_OCC_RESET; break; case OPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE: @@ -126,15 +126,15 @@ static void prd_msg_consumed(void *data, int status) platform.prd->msg_response(notify_status); break; case OPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH: - proc = msg->sbe_passthrough.chip; + proc = be64_to_cpu(msg->sbe_passthrough.chip); event = EVENT_SBE_PASSTHROUGH; break; case OPAL_PRD_MSG_TYPE_FSP_OCC_RESET: - proc = msg->occ_reset.chip; + proc = be64_to_cpu(msg->occ_reset.chip); event = EVENT_FSP_OCC_RESET; break; case OPAL_PRD_MSG_TYPE_FSP_OCC_LOAD_START: - proc = msg->occ_reset.chip; + proc = be64_to_cpu(msg->occ_reset.chip); event = EVENT_FSP_OCC_LOAD_START; break; default: @@ -164,9 +164,9 @@ static int populate_ipoll_msg(struct opal_prd_msg *msg, uint32_t proc) return -1; } - msg->attn.proc = proc; - msg->attn.ipoll_status = ipoll_status[proc]; - msg->attn.ipoll_mask = ipoll_mask; + msg->attn.proc = cpu_to_be64(proc); + msg->attn.ipoll_status = cpu_to_be64(ipoll_status[proc]); + msg->attn.ipoll_mask = cpu_to_be64(ipoll_mask); return 0; } @@ -196,27 +196,27 @@ static void send_next_pending_event(void) return; prd_msg->token = 0; - prd_msg->hdr.size = sizeof(*prd_msg); + prd_msg->hdr.size = cpu_to_be16(sizeof(*prd_msg)); if (event & EVENT_ATTN) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_ATTN; populate_ipoll_msg(prd_msg, proc); } else if (event & EVENT_OCC_ERROR) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_OCC_ERROR; - prd_msg->occ_error.chip = proc; + prd_msg->occ_error.chip = cpu_to_be64(proc); } else if (event & EVENT_OCC_RESET) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_OCC_RESET; - prd_msg->occ_reset.chip = proc; + prd_msg->occ_reset.chip = cpu_to_be64(proc); occ_msg_queue_occ_reset(); } else if (event & EVENT_SBE_PASSTHROUGH) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH; - prd_msg->sbe_passthrough.chip = proc; + prd_msg->sbe_passthrough.chip = cpu_to_be64(proc); } else if (event & EVENT_FSP_OCC_RESET) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_FSP_OCC_RESET; - prd_msg->occ_reset.chip = proc; + prd_msg->occ_reset.chip = cpu_to_be64(proc); } else if (event & EVENT_FSP_OCC_LOAD_START) { prd_msg->hdr.type = OPAL_PRD_MSG_TYPE_FSP_OCC_LOAD_START; - prd_msg->occ_reset.chip = proc; + prd_msg->occ_reset.chip = cpu_to_be64(proc); } /* @@ -225,7 +225,7 @@ static void send_next_pending_event(void) */ if (prd_enabled) { rc = _opal_queue_msg(OPAL_MSG_PRD, prd_msg, prd_msg_consumed, - prd_msg->hdr.size, prd_msg); + sizeof(*prd_msg), prd_msg); if (!rc) prd_msg_inuse = true; } @@ -337,7 +337,7 @@ void prd_fw_resp_fsp_response(int status) fw_resp->type = cpu_to_be64(PRD_FW_MSG_TYPE_RESP_GENERIC); fw_resp->generic_resp.status = cpu_to_be64(status); - fw_resp_len_old = prd_msg_fsp_req->fw_resp.len; + fw_resp_len_old = be64_to_cpu(prd_msg_fsp_req->fw_resp.len); prd_msg_fsp_req->fw_resp.len = cpu_to_be64(PRD_FW_MSG_BASE_SIZE + sizeof(fw_resp->generic_resp)); @@ -353,11 +353,11 @@ void prd_fw_resp_fsp_response(int status) * OPAL_MSG_PRD to pass data to kernel. So that it works fine on * older kernel (which does not support OPAL_MSG_PRD2). */ - if (prd_msg_fsp_req->hdr.size < OPAL_MSG_FIXED_PARAMS_SIZE) + if (be16_to_cpu(prd_msg_fsp_req->hdr.size) < OPAL_MSG_FIXED_PARAMS_SIZE) msg_type = OPAL_MSG_PRD; rc = _opal_queue_msg(msg_type, prd_msg_fsp_req, prd_msg_consumed, - prd_msg_fsp_req->hdr.size, prd_msg_fsp_req); + be16_to_cpu(prd_msg_fsp_req->hdr.size), prd_msg_fsp_req); if (!rc) prd_msg_inuse = true; unlock(&events_lock); @@ -411,7 +411,7 @@ int prd_hbrt_fsp_msg_notify(void *data, u32 dsize) * OPAL_MSG_PRD to pass data to kernel. So that it works fine on * older kernel (which does not support OPAL_MSG_PRD2). */ - if (prd_msg_fsp_notify->hdr.size < OPAL_MSG_FIXED_PARAMS_SIZE) + if (be16_to_cpu(prd_msg_fsp_notify->hdr.size) < OPAL_MSG_FIXED_PARAMS_SIZE) msg_type = OPAL_MSG_PRD; rc = _opal_queue_msg(msg_type, prd_msg_fsp_notify, @@ -430,8 +430,8 @@ static int prd_msg_handle_attn_ack(struct opal_prd_msg *msg) int rc; lock(&ipoll_lock); - rc = __ipoll_update_mask(msg->attn_ack.proc, false, - msg->attn_ack.ipoll_ack & prd_ipoll_mask); + rc = __ipoll_update_mask(be64_to_cpu(msg->attn_ack.proc), false, + be64_to_cpu(msg->attn_ack.ipoll_ack) & prd_ipoll_mask); unlock(&ipoll_lock); if (rc) @@ -447,7 +447,7 @@ static int prd_msg_handle_init(struct opal_prd_msg *msg) lock(&ipoll_lock); for_each_chip(chip) { __ipoll_update_mask(chip->id, false, - msg->init.ipoll & prd_ipoll_mask); + be64_to_cpu(msg->init.ipoll) & prd_ipoll_mask); } unlock(&ipoll_lock); @@ -497,7 +497,7 @@ static int prd_msg_handle_firmware_req(struct opal_prd_msg *msg) /* does the total (outer) PRD message len provide enough data for the * claimed (inner) FW message? */ - if (msg->hdr.size < fw_req_len + + if (be16_to_cpu(msg->hdr.size) < fw_req_len + offsetof(struct opal_prd_msg, fw_req.data)) return -EINVAL; @@ -524,8 +524,8 @@ static int prd_msg_handle_firmware_req(struct opal_prd_msg *msg) case PRD_FW_MSG_TYPE_ERROR_LOG: assert(platform.prd); assert(platform.prd->send_error_log); - rc = platform.prd->send_error_log(fw_req->errorlog.plid, - fw_req->errorlog.size, + rc = platform.prd->send_error_log(be32_to_cpu(fw_req->errorlog.plid), + be32_to_cpu(fw_req->errorlog.size), fw_req->errorlog.data); /* Return generic response to HBRT */ fw_resp->type = cpu_to_be64(PRD_FW_MSG_TYPE_RESP_GENERIC); @@ -581,7 +581,7 @@ static int prd_msg_handle_firmware_req(struct opal_prd_msg *msg) prd_msg_fsp_req->hdr.type = OPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE; prd_msg_fsp_req->hdr.size = cpu_to_be16(resp_msg_size); prd_msg_fsp_req->token = 0; - prd_msg_fsp_req->fw_resp.len = fw_req_len; + prd_msg_fsp_req->fw_resp.len = cpu_to_be64(fw_req_len); /* copy HBRT data to local memory */ fw_resp = (struct prd_fw_msg *)prd_msg_fsp_req->fw_resp.data; @@ -625,7 +625,7 @@ static int prd_msg_handle_firmware_req(struct opal_prd_msg *msg) if (!rc) { rc = _opal_queue_msg(OPAL_MSG_PRD, prd_msg, prd_msg_consumed, - prd_msg->hdr.size, prd_msg); + be16_to_cpu(prd_msg->hdr.size), prd_msg); if (rc) prd_msg_inuse = false; } else { @@ -645,11 +645,11 @@ static int64_t opal_prd_msg(struct opal_prd_msg *msg) /* fini is a little special: the kernel (which may not have the entire * opal_prd_msg definition) can send a FINI message, so we don't check * the full size */ - if (msg->hdr.size >= sizeof(struct opal_prd_msg_header) && + if (be16_to_cpu(msg->hdr.size) >= sizeof(struct opal_prd_msg_header) && msg->hdr.type == OPAL_PRD_MSG_TYPE_FINI) return prd_msg_handle_fini(); - if (msg->hdr.size < sizeof(*msg)) + if (be16_to_cpu(msg->hdr.size) < sizeof(*msg)) return OPAL_PARAMETER; switch (msg->hdr.type) { @@ -669,21 +669,21 @@ static int64_t opal_prd_msg(struct opal_prd_msg *msg) assert(platform.prd); assert(platform.prd->fsp_occ_reset_status); rc = platform.prd->fsp_occ_reset_status( - msg->fsp_occ_reset_status.chip, - msg->fsp_occ_reset_status.status); + be64_to_cpu(msg->fsp_occ_reset_status.chip), + be64_to_cpu(msg->fsp_occ_reset_status.status)); break; case OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP: assert(platform.prd); assert(platform.prd->wakeup); - rc = platform.prd->wakeup(msg->spl_wakeup.core, - msg->spl_wakeup.mode); + rc = platform.prd->wakeup(be32_to_cpu(msg->spl_wakeup.core), + be32_to_cpu(msg->spl_wakeup.mode)); break; case OPAL_PRD_MSG_TYPE_FSP_OCC_LOAD_START_STATUS: assert(platform.prd); assert(platform.prd->fsp_occ_load_start_status); rc = platform.prd->fsp_occ_load_start_status( - msg->fsp_occ_reset_status.chip, - msg->fsp_occ_reset_status.status); + be64_to_cpu(msg->fsp_occ_reset_status.chip), + be64_to_cpu(msg->fsp_occ_reset_status.status)); break; default: prlog(PR_DEBUG, "PRD: Unsupported prd message type : 0x%x\n", From patchwork Wed Nov 6 12:10:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qcw2pSHz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:14 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:40 +1000 Message-Id: <20191106121047.14389-23-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 22/29] opal-dump: MPIPL endan conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/opal-dump.c | 80 +++++++++++++++++++++++++--------------------- include/opal-api.h | 14 ++++---- 2 files changed, 51 insertions(+), 43 deletions(-) diff --git a/core/opal-dump.c b/core/opal-dump.c index 3bea1f105..f1f85ef51 100644 --- a/core/opal-dump.c +++ b/core/opal-dump.c @@ -68,18 +68,18 @@ static int opal_mpipl_max_tags = MAX_OPAL_MPIPL_TAGS; static int opal_mpipl_add_entry(u8 region, u64 src, u64 dest, u64 size) { - int i, max_cnt; + int i; + int mdst_cnt = be16_to_cpu(ntuple_mdst->act_cnt); + int mddt_cnt = be16_to_cpu(ntuple_mddt->act_cnt); struct mdst_table *mdst; struct mddt_table *mddt; - max_cnt = MDST_TABLE_SIZE / sizeof(struct mdst_table); - if (ntuple_mdst->act_cnt >= max_cnt) { + if (mdst_cnt >= MDST_TABLE_SIZE / sizeof(struct mdst_table)) { prlog(PR_DEBUG, "MDST table is full\n"); return OPAL_RESOURCE; } - max_cnt = MDDT_TABLE_SIZE / sizeof(struct mddt_table); - if (ntuple_mdst->act_cnt >= max_cnt) { + if (mddt_cnt >= MDDT_TABLE_SIZE / sizeof(struct mddt_table)) { prlog(PR_DEBUG, "MDDT table is full\n"); return OPAL_RESOURCE; } @@ -89,16 +89,16 @@ static int opal_mpipl_add_entry(u8 region, u64 src, u64 dest, u64 size) mddt = (void *)(MDDT_TABLE_BASE); /* Check for duplicate entry */ - for (i = 0; i < ntuple_mdst->act_cnt; i++) { - if (mdst->addr == (src | HRMOR_BIT)) { + for (i = 0; i < mdst_cnt; i++) { + if (be64_to_cpu(mdst->addr) == (src | HRMOR_BIT)) { prlog(PR_DEBUG, "Duplicate source address : 0x%llx", src); return OPAL_PARAMETER; } mdst++; } - for (i = 0; i < ntuple_mddt->act_cnt; i++) { - if (mddt->addr == (dest | HRMOR_BIT)) { + for (i = 0; i < mddt_cnt; i++) { + if (be64_to_cpu(mddt->addr) == (dest | HRMOR_BIT)) { prlog(PR_DEBUG, "Duplicate destination address : 0x%llx", dest); return OPAL_PARAMETER; @@ -107,16 +107,16 @@ static int opal_mpipl_add_entry(u8 region, u64 src, u64 dest, u64 size) } /* Add OPAL source address to MDST entry */ - mdst->addr = src | HRMOR_BIT; + mdst->addr = cpu_to_be64(src | HRMOR_BIT); mdst->data_region = region; - mdst->size = size; - ntuple_mdst->act_cnt++; + mdst->size = cpu_to_be32(size); + ntuple_mdst->act_cnt = cpu_to_be16(mdst_cnt + 1); /* Add OPAL destination address to MDDT entry */ - mddt->addr = dest | HRMOR_BIT; + mddt->addr = cpu_to_be64(dest | HRMOR_BIT); mddt->data_region = region; - mddt->size = size; - ntuple_mddt->act_cnt++; + mddt->size = cpu_to_be32(size); + ntuple_mddt->act_cnt = cpu_to_be16(mddt_cnt + 1); prlog(PR_TRACE, "Added new entry. src : 0x%llx, dest : 0x%llx," " size : 0x%llx\n", src, dest, size); @@ -128,17 +128,19 @@ static int opal_mpipl_remove_entry_mdst(bool remove_all, u8 region, u64 src) { bool found = false; int i, j; + int mdst_cnt = be16_to_cpu(ntuple_mdst->act_cnt); struct mdst_table *tmp_mdst; struct mdst_table *mdst = (void *)(MDST_TABLE_BASE); - for (i = 0; i < ntuple_mdst->act_cnt;) { + for (i = 0; i < mdst_cnt;) { if (mdst->data_region != region) { mdst++; i++; continue; } - if (remove_all != true && mdst->addr != (src | HRMOR_BIT)) { + if (remove_all != true && + be64_to_cpu(mdst->addr) != (src | HRMOR_BIT)) { mdst++; i++; continue; @@ -147,14 +149,14 @@ static int opal_mpipl_remove_entry_mdst(bool remove_all, u8 region, u64 src) tmp_mdst = mdst; memset(tmp_mdst, 0, sizeof(struct mdst_table)); - for (j = i; j < ntuple_mdst->act_cnt - 1; j++) { + for (j = i; j < mdst_cnt - 1; j++) { memcpy((void *)tmp_mdst, (void *)(tmp_mdst + 1), sizeof(struct mdst_table)); tmp_mdst++; memset(tmp_mdst, 0, sizeof(struct mdst_table)); } - ntuple_mdst->act_cnt--; + mdst_cnt--; if (remove_all == false) { found = true; @@ -162,6 +164,8 @@ static int opal_mpipl_remove_entry_mdst(bool remove_all, u8 region, u64 src) } } /* end - for loop */ + ntuple_mdst->act_cnt = cpu_to_be16((u16)mdst_cnt); + if (remove_all == false && found == false) { prlog(PR_DEBUG, "Source address [0x%llx] not found in MDST table\n", src); @@ -176,17 +180,19 @@ static int opal_mpipl_remove_entry_mddt(bool remove_all, u8 region, u64 dest) { bool found = false; int i, j; + int mddt_cnt = be16_to_cpu(ntuple_mddt->act_cnt); struct mddt_table *tmp_mddt; struct mddt_table *mddt = (void *)(MDDT_TABLE_BASE); - for (i = 0; i < ntuple_mddt->act_cnt;) { + for (i = 0; i < mddt_cnt;) { if (mddt->data_region != region) { mddt++; i++; continue; } - if (remove_all != true && mddt->addr != (dest | HRMOR_BIT)) { + if (remove_all != true && + be64_to_cpu(mddt->addr) != (dest | HRMOR_BIT)) { mddt++; i++; continue; @@ -195,14 +201,14 @@ static int opal_mpipl_remove_entry_mddt(bool remove_all, u8 region, u64 dest) tmp_mddt = mddt; memset(tmp_mddt, 0, sizeof(struct mddt_table)); - for (j = i; j < ntuple_mddt->act_cnt - 1; j++) { + for (j = i; j < mddt_cnt - 1; j++) { memcpy((void *)tmp_mddt, (void *)(tmp_mddt + 1), sizeof(struct mddt_table)); tmp_mddt++; memset(tmp_mddt, 0, sizeof(struct mddt_table)); } - ntuple_mddt->act_cnt--; + mddt_cnt--; if (remove_all == false) { found = true; @@ -210,6 +216,8 @@ static int opal_mpipl_remove_entry_mddt(bool remove_all, u8 region, u64 dest) } } /* end - for loop */ + ntuple_mddt->act_cnt = cpu_to_be16((u16)mddt_cnt); + if (remove_all == false && found == false) { prlog(PR_DEBUG, "Dest address [0x%llx] not found in MDDT table\n", dest); @@ -258,8 +266,8 @@ static void opal_mpipl_register(void) /* Reserve memory used to capture architected register state */ mem_reserve_fw("ibm,firmware-arch-registers", arch_regs_dest, arch_regs_size); - proc_dump->alloc_addr = arch_regs_dest | HRMOR_BIT; - proc_dump->alloc_size = arch_regs_size; + proc_dump->alloc_addr = cpu_to_be64(arch_regs_dest | HRMOR_BIT); + proc_dump->alloc_size = cpu_to_be32(arch_regs_size); prlog(PR_NOTICE, "Architected register dest addr : 0x%llx, " "size : 0x%llx\n", arch_regs_dest, arch_regs_size); } @@ -339,7 +347,7 @@ static int64_t opal_mpipl_update(enum opal_mpipl_ops ops, /* Clear MDRT table */ memset((void *)MDRT_TABLE_BASE, 0, MDRT_TABLE_SIZE); /* Set MDRT count to max allocated count */ - ntuple_mdrt->act_cnt = MDRT_TABLE_SIZE / sizeof(struct mdrt_table); + ntuple_mdrt->act_cnt = cpu_to_be16(MDRT_TABLE_SIZE / sizeof(struct mdrt_table)); rc = OPAL_SUCCESS; prlog(PR_NOTICE, "Payload Invalidated MPIPL\n"); break; @@ -426,13 +434,13 @@ static void post_mpipl_arch_regs_data(void) /* Fill CPU register details */ opal_mpipl_cpu_data->version = OPAL_MPIPL_VERSION; - opal_mpipl_cpu_data->cpu_data_version = proc_dump->version; + opal_mpipl_cpu_data->cpu_data_version = cpu_to_be32((u32)proc_dump->version); opal_mpipl_cpu_data->cpu_data_size = proc_dump->thread_size; opal_mpipl_cpu_data->region_cnt = cpu_to_be32(1); - opal_mpipl_cpu_data->region[0].src = proc_dump->dest_addr & ~(HRMOR_BIT); - opal_mpipl_cpu_data->region[0].dest = proc_dump->dest_addr & ~(HRMOR_BIT); - opal_mpipl_cpu_data->region[0].size = proc_dump->act_size; + opal_mpipl_cpu_data->region[0].src = proc_dump->dest_addr & ~(cpu_to_be64(HRMOR_BIT)); + opal_mpipl_cpu_data->region[0].dest = proc_dump->dest_addr & ~(cpu_to_be64(HRMOR_BIT)); + opal_mpipl_cpu_data->region[0].size = cpu_to_be64(be32_to_cpu(proc_dump->act_size)); /* Update tag */ opal_mpipl_tags[OPAL_MPIPL_TAG_CPU] = (u64)opal_mpipl_cpu_data; @@ -442,7 +450,7 @@ static void post_mpipl_get_opal_data(void) { struct mdrt_table *mdrt = (void *)(MDRT_TABLE_BASE); int i, j = 0, count = 0; - u32 mdrt_cnt = ntuple_mdrt->act_cnt; + int mdrt_cnt = be16_to_cpu(ntuple_mdrt->act_cnt); struct opal_mpipl_region *region; /* Count OPAL dump regions */ @@ -466,8 +474,8 @@ static void post_mpipl_get_opal_data(void) /* Fill OPAL dump details */ opal_mpipl_data->version = OPAL_MPIPL_VERSION; - opal_mpipl_data->crashing_pir = mpipl_metadata->crashing_pir; - opal_mpipl_data->region_cnt = count; + opal_mpipl_data->crashing_pir = cpu_to_be32(mpipl_metadata->crashing_pir); + opal_mpipl_data->region_cnt = cpu_to_be32(count); region = opal_mpipl_data->region; mdrt = (void *)(MDRT_TABLE_BASE); @@ -477,9 +485,9 @@ static void post_mpipl_get_opal_data(void) continue; } - region[j].src = mdrt->src_addr & ~(HRMOR_BIT); - region[j].dest = mdrt->dest_addr & ~(HRMOR_BIT); - region[j].size = mdrt->size; + region[j].src = mdrt->src_addr & ~(cpu_to_be64(HRMOR_BIT)); + region[j].dest = mdrt->dest_addr & ~(cpu_to_be64(HRMOR_BIT)); + region[j].size = cpu_to_be64(be32_to_cpu(mdrt->size)); prlog(PR_NOTICE, "OPAL reserved region %d - src : 0x%llx, " "dest : 0x%llx, size : 0x%llx\n", j, region[j].src, diff --git a/include/opal-api.h b/include/opal-api.h index dd74e662c..0ae91cc5f 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -1226,9 +1226,9 @@ enum opal_mpipl_tags { /* Preserved memory details */ struct opal_mpipl_region { - u64 src; - u64 dest; - u64 size; + __be64 src; + __be64 dest; + __be64 size; }; /* Structure version */ @@ -1237,10 +1237,10 @@ struct opal_mpipl_region { struct opal_mpipl_fadump { u8 version; u8 reserved[7]; - u32 crashing_pir; /* OPAL crashing CPU PIR */ - u32 cpu_data_version; - u32 cpu_data_size; - u32 region_cnt; + __be32 crashing_pir; /* OPAL crashing CPU PIR */ + __be32 cpu_data_version; + __be32 cpu_data_size; + __be32 region_cnt; struct opal_mpipl_region region[]; }; From patchwork Wed Nov 6 12:10:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QdD0Rf6z9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:17 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:41 +1000 Message-Id: <20191106121047.14389-24-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 23/29] sfc-ctrl: endian conversions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hw/sfc-ctrl.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/sfc-ctrl.c b/hw/sfc-ctrl.c index f17b8de29..d66be09eb 100644 --- a/hw/sfc-ctrl.c +++ b/hw/sfc-ctrl.c @@ -110,33 +110,32 @@ struct sfc_ctrl { /* Command register support */ static inline int sfc_reg_read(uint8_t reg, uint32_t *val) { - uint32_t tmp; int rc; *val = 0xffffffff; - rc = lpc_fw_read32(&tmp, SFC_CMDREG_OFFSET + reg); + rc = lpc_fw_read32(val, SFC_CMDREG_OFFSET + reg); if (rc) return rc; - *val = be32_to_cpu(tmp); return 0; } static inline int sfc_reg_write(uint8_t reg, uint32_t val) { - return lpc_fw_write32(cpu_to_be32(val), SFC_CMDREG_OFFSET + reg); + return lpc_fw_write32(val, SFC_CMDREG_OFFSET + reg); } static int sfc_buf_write(uint32_t len, const void *data) { - uint32_t tmp, off = 0; + __be32 tmp; + uint32_t off = 0; int rc; if (len > SFC_CMDBUF_SIZE) return FLASH_ERR_PARM_ERROR; while (len >= 4) { - tmp = *(const uint32_t *)data; - rc = lpc_fw_write32(tmp, SFC_CMDBUF_OFFSET + off); + tmp = cpu_to_be32(*(const uint32_t *)data); + rc = lpc_fw_write32((u32)tmp, SFC_CMDBUF_OFFSET + off); if (rc) return rc; off += 4; @@ -150,9 +149,9 @@ static int sfc_buf_write(uint32_t len, const void *data) * in memory with memcpy. The swap in the register on LE doesn't * matter, the result in memory will be in the right order. */ - tmp = -1; - memcpy(&tmp, data, len); - return lpc_fw_write32(tmp, SFC_CMDBUF_OFFSET + off); + tmp = cpu_to_be32(-1); + memcpy(&tmp, data, len); /* XXX: is this right? */ + return lpc_fw_write32((u32)tmp, SFC_CMDBUF_OFFSET + off); } static int sfc_buf_read(uint32_t len, void *data) From patchwork Wed Nov 6 12:10:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QdY27ywz9sNx for ; Wed, 6 Nov 2019 23:22:09 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OzS9dbLA"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477QdY0j4NzF67Z for ; Wed, 6 Nov 2019 23:22:09 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::443; helo=mail-pf1-x443.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OzS9dbLA"; dkim-atps=neutral Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QQG4fwszF5w1 for ; Wed, 6 Nov 2019 23:12:22 +1100 (AEDT) Received: by mail-pf1-x443.google.com with SMTP id 193so17420745pfc.13 for ; Wed, 06 Nov 2019 04:12:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3RDJ/ge38WqoSrgH12NKvBHWr0kKUm3YYPYadt1mvuo=; b=OzS9dbLAwTuFb5xB+vvf1M+m9tkzAVfvOufYcFkrLj45Y7xrNG+T9s96i1m4kHWihn F2TjczOcHrWa33TUbu9E79N2N26SMwKoMkxik/T3COjkvFZ/Rj+2fsbeEmPa/ouKiWy2 gVfG8cR3qCe2R5WwTgdMIF1NNLJxuJk+BcMLO1vWdE5b7BrGSKXR+XGat3xiZJKHNeTI aGU1yfrh/GHpUF1ORctkp7/pF3/glowXB8aTDLZHp38ivwPAO0SWUJrubssVsyRR0YWI MDcdbnJ8HUdKrVl0CKaX6irG1GrPD4zqI8GUmKIXf8OQ64o2gIXxAB0ctF7jjiN34gl+ UsYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3RDJ/ge38WqoSrgH12NKvBHWr0kKUm3YYPYadt1mvuo=; b=pNgsRs3ALPmQ8wY6Q/LWCFrjpq0efSSuXPgCDoLcehtl40FdTEpOVwmCEI4ydkYktQ dqGjwEveO1+AGiD4qouxaGKZDkO5PSCfNbXvSO5+wa+2yksNBc6iCTCNocPeuzFAGEjq SkxtmkK9zFFA2hTOVRd15CrAvJXzkqfy2DlSz6tJSMWAyg6Cvn4QnFbuEMpbQP9DXmto w0Ye5CPkBL4crZDe4Cxv7C47JR3f9+hoCcchDr1LmkUMjV9t1qTu1uFMeSCslff2h+cr fAR5aKUMftJFaWaFKDkSAkAv+BUas6DGZLKAKaRl64AC7uiKFTLX/7aE61/jzhviuhmP ItSA== X-Gm-Message-State: APjAAAXK5QFbleo+G42DqlwZJD8/rYE6zDU7aeTtT4gCXt+s5ELI7qY8 bHdTclybpzLWvoB/QX8cvcD1OboXGI8= X-Google-Smtp-Source: APXvYqzV3defvBwuj5gbOz7pzfZJQmAoyQOCFnhskPilg5ma75bDbE+28/1MdHAzndt2hY7g6cTWNA== X-Received: by 2002:a63:c40e:: with SMTP id h14mr2528531pgd.254.1573042340197; Wed, 06 Nov 2019 04:12:20 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:19 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:42 +1000 Message-Id: <20191106121047.14389-25-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 24/29] add little endian support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds support for building LE skiboot with LITTLE_ENDIAN=1. This is not complete, notably PHB3, NPU* and *CAPI*, but it is sufficient to build and boot on mambo and OpenPOWER POWER9 systems. LE/ELFv2 is a nicer calling convention, and results in smaller image and less stack usage. It also follows the rest of the Linux/OpenPOWER stack moving to LE. The OPALv3 call interface still requires an ugly transition through BE for compatibility, but that is all handled on the OPAL side. Signed-off-by: Nicholas Piggin --- Makefile.main | 38 ++++++++++++-- asm/head.S | 66 +++++++++++++++++------- core/cpu.c | 24 +++++++-- core/init.c | 1 + doc/stb.rst | 2 +- include/asm-utils.h | 22 ++++++-- include/cpu.h | 3 ++ libpore/p9_cpu_reg_restore_instruction.H | 23 +++++---- 8 files changed, 135 insertions(+), 44 deletions(-) diff --git a/Makefile.main b/Makefile.main index 2d60bbbf5..1d834e81b 100644 --- a/Makefile.main +++ b/Makefile.main @@ -65,21 +65,35 @@ CPPFLAGS += -I$(SRC)/libfdt -I$(SRC)/libflash -I$(SRC)/libxz -I$(SRC)/libc/inclu CPPFLAGS += -I$(SRC)/libpore CPPFLAGS += -D__SKIBOOT__ -nostdinc CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) -CPPFLAGS += -DBITS_PER_LONG=64 -DHAVE_BIG_ENDIAN +CPPFLAGS += -DBITS_PER_LONG=64 + # We might want to remove our copy of stdint.h # but that means uint64_t becomes an ulong instead of an ullong # causing all our printf's to warn CPPFLAGS += -ffreestanding +ifeq ($(LITTLE_ENDIAN),1) +CPPFLAGS += -DHAVE_LITTLE_ENDIAN +else +CPPFLAGS += -DHAVE_BIG_ENDIAN +endif + ifeq ($(DEBUG),1) CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG endif -CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -mbig-endian -m64 -fno-asynchronous-unwind-tables +CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables CFLAGS += -mcpu=power8 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb CFLAGS += $(call try-cflag,$(CC),-ffixed-r13) CFLAGS += $(call try-cflag,$(CC),-std=gnu11) + +ifeq ($(LITTLE_ENDIAN),1) +CFLAGS += -mlittle-endian +else +CFLAGS += -mbig-endian +endif + ifeq ($(ELF_ABI_v2),1) CFLAGS += $(call try-cflag,$(CC),-mabi=elfv2) else @@ -135,8 +149,8 @@ LDFLAGS := -m64 -static -nostdlib -pie LDFLAGS += -Wl,-pie LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none LDFLAGS += -Wl,--no-multi-toc -LDFLAGS += -mcpu=power8 -mbig-endian -Wl,--oformat,elf64-powerpc -LDFLAGS_FINAL = -EB -m elf64ppc --no-multi-toc -N --build-id=none --whole-archive +LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc +LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc LDFLAGS_FINAL += --orphan-handling=warn @@ -144,11 +158,25 @@ LDRFLAGS=-melf64ppc # Debug stuff #LDFLAGS += -Wl,-v -Wl,-Map,foomap +ifeq ($(LITTLE_ENDIAN),1) +LDFLAGS += -mlittle-endian +LDFLAGS_FINAL += -EL +else +LDFLAGS += -mbig-endian +LDFLAGS_FINAL += -EB +endif + ifeq ($(DEAD_CODE_ELIMINATION),1) LDFLAGS += -Wl,--gc-sections endif -AFLAGS := -D__ASSEMBLY__ -mbig-endian -m64 +AFLAGS := -D__ASSEMBLY__ -m64 +ifeq ($(LITTLE_ENDIAN),1) +AFLAGS += -mlittle-endian +else +AFLAGS += -mbig-endian +endif + ifeq ($(ELF_ABI_v2),1) AFLAGS += $(call try-cflag,$(CC),-mabi=elfv2) else diff --git a/asm/head.S b/asm/head.S index 7ce3c7c97..68f153b36 100644 --- a/asm/head.S +++ b/asm/head.S @@ -43,6 +43,7 @@ __head: . = 0x10 .global fdt_entry fdt_entry: + FIXUP_ENDIAN mr %r27,%r3 b boot_entry @@ -89,6 +90,7 @@ hir_trigger: . = 0x100 sreset_vector: /* BML entry, load up r3 with device tree location */ + FIXUP_ENDIAN li %r3, 0 oris %r3, %r3, 0xa b fdt_entry /* hack for lab boot */ @@ -96,6 +98,7 @@ sreset_vector: /* Entry point set by the FSP */ .= 0x180 hdat_entry: + FIXUP_ENDIAN li %r27,0 b boot_entry @@ -364,7 +367,11 @@ boot_entry: add %r2,%r2,%r29 /* Fixup our MSR (remove TA) */ +#if HAVE_BIG_ENDIAN LOAD_IMM64(%r3, (MSR_HV | MSR_SF)) +#else + LOAD_IMM64(%r3, (MSR_HV | MSR_SF | MSR_LE)) +#endif mtmsrd %r3,0 /* Check our PIR, avoid threads */ @@ -698,14 +705,18 @@ init_shared_sprs: mtspr SPR_TSCR, %r3 /* HID0: Clear bit 13 (enable core recovery) - * Clear bit 19 (HILE) + * Set/clear bit 19 (HILE) depending on skiboot endian */ mfspr %r3,SPR_HID0 li %r0,1 sldi %r4,%r0,(63-13) - sldi %r5,%r0,(63-19) - or %r0,%r4,%r5 - andc %r3,%r3,%r0 + andc %r3,%r3,%r4 + sldi %r4,%r0,(63-19) +#if HAVE_BIG_ENDIAN + andc %r3,%r3,%r4 +#else + or %r3,%r3,%r4 +#endif sync mtspr SPR_HID0,%r3 mfspr %r3,SPR_HID0 @@ -732,17 +743,21 @@ init_shared_sprs: LOAD_IMM32(%r3,0x80287880) mtspr SPR_TSCR, %r3 /* HID0: Clear bit 5 (enable core recovery) - * Clear bit 4 (HILE) + * Set/clear bit 4 (HILE) depending on skiboot endian * Set bit 8 (radix) */ mfspr %r3,SPR_HID0 li %r0,1 - sldi %r4,%r0,(63-8) + sldi %r4,%r0,(63-4) +#if HAVE_BIG_ENDIAN + andc %r3,%r3,%r4 +#else or %r3,%r3,%r4 +#endif sldi %r4,%r0,(63-5) - sldi %r5,%r0,(63-4) - or %r0,%r4,%r5 - andc %r3,%r3,%r0 + andc %r3,%r3,%r4 + sldi %r4,%r0,(63-8) + or %r3,%r3,%r4 sync mtspr SPR_HID0,%r3 isync @@ -822,6 +837,8 @@ enter_nap: .balign 0x10 .global opal_entry opal_entry: + OPAL_ENTRY_TO_SKIBOOT_ENDIAN + /* Get our per CPU pointer in r12 to check for quiesce */ mfspr %r12,SPR_PIR GET_STACK(%r12,%r12) @@ -967,20 +984,33 @@ opal_entry: lwz %r11,CPUTHREAD_IN_OPAL_CALL(%r12) subi %r11,%r11,1 stw %r11,CPUTHREAD_IN_OPAL_CALL(%r12) +#if HAVE_BIG_ENDIAN /* * blr with BH=01b means it's not a function return, OPAL was entered * via (h)rfid not bl, so we don't have a corresponding link stack * prediction to return to here. */ bclr 20,0,1 +#else + mflr %r12 + mtspr SPR_HSRR0,%r12 + mfmsr %r11 + li %r12,MSR_LE + andc %r11,%r11,%r12 + mtspr SPR_HSRR1,%r11 + hrfid +#endif .global start_kernel start_kernel: + LOAD_IMM64(%r10,MSR_HV|MSR_SF) +__start_kernel: sync icbi 0,%r3 sync isync - mtctr %r3 + mtspr SPR_HSRR0,%r3 + mtspr SPR_HSRR1,%r10 mr %r3,%r4 LOAD_IMM64(%r8,SKIBOOT_BASE); LOAD_IMM32(%r10, opal_entry - __head) @@ -989,21 +1019,19 @@ start_kernel: addi %r7,%r5,1 li %r4,0 li %r5,0 - bctr + hrfid .global start_kernel32 start_kernel32: - mfmsr %r10 - clrldi %r10,%r10,1 - mtmsrd %r10,0 - sync - isync - b start_kernel + LOAD_IMM64(%r10,MSR_HV) + b __start_kernel .global start_kernel_secondary start_kernel_secondary: sync isync - mtctr %r3 + LOAD_IMM64(%r10,MSR_HV|MSR_SF) + mtspr SPR_HSRR0,%r3 + mtspr SPR_HSRR1,%r10 mfspr %r3,SPR_PIR - bctr + hrfid diff --git a/core/cpu.c b/core/cpu.c index b3433aef5..3d6a59033 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -42,7 +42,7 @@ static unsigned long hid0_attn; static bool sreset_enabled; static bool ipi_enabled; static bool pm_enabled; -static bool current_hile_mode; +static bool current_hile_mode = HAVE_LITTLE_ENDIAN; static bool current_radix_mode = true; static bool tm_suspend_enabled; @@ -1415,6 +1415,24 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) return OPAL_SUCCESS; } +void cpu_set_hile_mode(bool hile) +{ + struct hid0_change_req req; + + if (hile == current_hile_mode) + return; + + if (hile) { + req.clr_bits = 0; + req.set_bits = hid0_hile; + } else { + req.clr_bits = hid0_hile; + req.set_bits = 0; + } + cpu_change_all_hid0(&req); + current_hile_mode = hile; +} + static void cpu_cleanup_one(void *param __unused) { mtspr(SPR_AMR, 0); @@ -1453,8 +1471,8 @@ static int64_t cpu_cleanup_all(void) void cpu_fast_reboot_complete(void) { - /* Fast reboot will have cleared HID0:HILE */ - current_hile_mode = false; + /* Fast reboot will have set HID0:HILE to skiboot endian */ + current_hile_mode = HAVE_LITTLE_ENDIAN; /* and set HID0:RADIX */ current_radix_mode = true; diff --git a/core/init.c b/core/init.c index 26d3e016f..1a4f9f939 100644 --- a/core/init.c +++ b/core/init.c @@ -632,6 +632,7 @@ void __noreturn load_and_boot_kernel(bool is_reboot) cpu_disable_ME_RI_all(); patch_traps(false); + cpu_set_hile_mode(false); /* Clear HILE on all CPUs */ checksum_romem(); diff --git a/doc/stb.rst b/doc/stb.rst index 6fc8f73da..84855ca55 100644 --- a/doc/stb.rst +++ b/doc/stb.rst @@ -92,7 +92,7 @@ CVC-verify Service .. code-block:: c int call_cvc_verify(void *buf, size_t size, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log) + size_t hw_key_hash_size, __be64 *log) This function wrapper calls into the *CVC-verify*, which verifies if the firmware code provided in ``@buf`` is properly signed with the keys trusted by diff --git a/include/asm-utils.h b/include/asm-utils.h index 2d26545e7..c3d8c09ea 100644 --- a/include/asm-utils.h +++ b/include/asm-utils.h @@ -28,17 +28,29 @@ /* Load an address via the TOC */ #define LOAD_ADDR_FROM_TOC(r, e) ld r,e@got(%r2) -#define FIXUP_ENDIAN \ - tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ - b 191f; /* Skip trampoline if endian is good */ \ +/* This must preserve LR, so can't use Linux kernel's FIXUP_ENDIAN */ +#define SWITCH_ENDIAN \ .long 0xa600607d; /* mfmsr r11 */ \ .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0xa64b7b7d; /* mthsrr1 r11 */ \ + .long 0xa602687d; /* mflr r11 */ \ .long 0x05009f42; /* bcl 20,31,$+4 */ \ .long 0xa602487d; /* mflr r10 */ \ .long 0x14004a39; /* addi r10,r10,20 */ \ .long 0xa64b5a7d; /* mthsrr0 r10 */ \ - .long 0xa64b7b7d; /* mthsrr1 r11 */ \ - .long 0x2402004c; /* hrfid */ \ + .long 0xa603687d; /* mtlr r11 */ \ + .long 0x2402004c /* hrfid */ + +#define FIXUP_ENDIAN \ + tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ + b 191f; /* Skip trampoline if endian is good */ \ + SWITCH_ENDIAN; /* Do the switch */ \ 191: +#if HAVE_BIG_ENDIAN +#define OPAL_ENTRY_TO_SKIBOOT_ENDIAN +#else +#define OPAL_ENTRY_TO_SKIBOOT_ENDIAN SWITCH_ENDIAN +#endif + #endif /* __ASM_UTILS_H */ diff --git a/include/cpu.h b/include/cpu.h index cda78644d..008f08a68 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -282,6 +282,9 @@ extern void cpu_process_local_jobs(void); /* Check if there's any job pending */ bool cpu_check_jobs(struct cpu_thread *cpu); +/* Set/clear HILE on all CPUs */ +void cpu_set_hile_mode(bool hile); + /* OPAL sreset vector in place at 0x100 */ void cpu_set_sreset_enable(bool sreset_enabled); diff --git a/libpore/p9_cpu_reg_restore_instruction.H b/libpore/p9_cpu_reg_restore_instruction.H index dd4358a82..cf00ff5e5 100644 --- a/libpore/p9_cpu_reg_restore_instruction.H +++ b/libpore/p9_cpu_reg_restore_instruction.H @@ -61,23 +61,24 @@ enum RLDICR_CONST = 1, MTSPR_CONST1 = 467, MTMSRD_CONST1 = 178, - MR_R0_TO_R10 = 0x7c0a0378, //mr r10, r0 - MR_R0_TO_R21 = 0x7c150378, //mr r21, r0 - MR_R0_TO_R9 = 0x7c090378, //mr r9, r0 - URMOR_CORRECTION = 0x7d397ba6, MFSPR_CONST = 339, - BLR_INST = 0x4e800020, - MTSPR_BASE_OPCODE = 0x7c0003a6, - ATTN_OPCODE = 0x00000200, OPCODE_18 = 18, SELF_SAVE_FUNC_ADD = 0x2300, SELF_SAVE_OFFSET = 0x180, - SKIP_SPR_REST_INST = 0x4800001c, //b . +0x01c - MFLR_R30 = 0x7fc802a6, - SKIP_SPR_SELF_SAVE = 0x3bff0020, //addi r31 r31, 0x20 - MTLR_INST = 0x7fc803a6 //mtlr r30 }; +#define MR_R0_TO_R10 0x7c0a0378UL //mr r10 r0 +#define MR_R0_TO_R21 0x7c150378UL //mr r21 r0 +#define MR_R0_TO_R9 0x7c090378UL //mr r9 r0 +#define URMOR_CORRECTION 0x7d397ba6UL +#define BLR_INST 0x4e800020UL +#define MTSPR_BASE_OPCODE 0x7c0003a6UL +#define ATTN_OPCODE 0x00000200UL +#define SKIP_SPR_REST_INST 0x4800001cUL //b . +0x01c +#define MFLR_R30 0x7fc802a6UL +#define SKIP_SPR_SELF_SAVE 0x3bff0020UL //addi r31 r31 0x20 +#define MTLR_INST 0x7fc803a6UL //mtlr r30 + #ifdef __cplusplus } // namespace stopImageSection ends From patchwork Wed Nov 6 12:10:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qdv1PlSz9sP3 for ; Wed, 6 Nov 2019 23:22:27 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LhGde5EN"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477Qdt6ZlmzF3r2 for ; Wed, 6 Nov 2019 23:22:26 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LhGde5EN"; dkim-atps=neutral Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QQJ3yGbzF5ry for ; Wed, 6 Nov 2019 23:12:24 +1100 (AEDT) Received: by mail-pl1-x641.google.com with SMTP id ay6so4337255plb.0 for ; Wed, 06 Nov 2019 04:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lK105S8Fq83UWgu0k1Hi+KLb21gU6Kmqx8giP/Smols=; b=LhGde5ENK3VuX0/gW8s2v2JsWIi73awO0JKqVFjKpgv7SyUQJkXErkwNZHlxkS2GJi f7CaKvdg3Mesekz7aI7CT86BDYuJcW7n61qNRp0e21B3YzATYr1jmLSEH2QUvkUsG03r xLVwBD596Eh9kogXtJbdOsfyknwCDm4Pwq9iQHZQGhiP6BbZoj2yfnMXRzVmz5Esy9rB p0+m0Op+2R0GxFUuJA4UxrB1lOHwR6jDc77P9FiqiUUgT39tBpCVE7mST4SQ8CI8ftmr 76TRZWtQoPen7sViF5i/nPhVDp5+YABYQ7gHtCnf8sWXHI15zfn5jsYVUsoAXo6NMFqm u02g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lK105S8Fq83UWgu0k1Hi+KLb21gU6Kmqx8giP/Smols=; b=JuvX9dY2qdAqqq0ZD2NEtGYQhc6RjLoGk2Kp7Z5+x5HFIzqdRL/vLTevwt0zB3r1aR QqWeTjibGMJu5hjTLaZscJ3uyjj9ccDLQYpj+dLboOmwWJxUBeQZZq6NyAuf4UYCci1N WmTbOII9H8lQz7KcyMJ3oaQi3DiziotqeSZHvFvUF+j8RNlM1W7lQZIaW3jdjsPbpuTn yS8dsYZMSdx9K+n7E0I97ghW1xqOsvh/RDuHV8tNTyzuLIVgU0kNerhP1Xz5rOcDBZGr Oe8BjoWlhRcSZMUOo3/2JfSOPxqLdJ6o3RtEUOC8GeTKmv+aCy0kxoGf29zkN3DYjIFm uasA== X-Gm-Message-State: APjAAAVNfLbR0YcQlNN22fZ7lbW84iOhnExWed8rK0R6scBVPfOI7fnf NEp4U1j4mUaWZiMsP3jgBOENQYmFmhg= X-Google-Smtp-Source: APXvYqyTxHoojLWDT7eDmJWhII1XpZeax2OPCaeDLmGr13cNgYuyi7GQc48mPa04+fXeOZ3/8iNi5Q== X-Received: by 2002:a17:902:b7cb:: with SMTP id v11mr224522plz.176.1573042342436; Wed, 06 Nov 2019 04:12:22 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:22 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:43 +1000 Message-Id: <20191106121047.14389-26-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 25/29] dt: assorted cleanups X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This replaces several instances dt accesses with higher level primitives throughout the tree. Signed-off-by: Nicholas Piggin --- core/device.c | 9 ++++++++- core/pci.c | 20 ++++++++------------ hdata/iohub.c | 21 +++++++-------------- hdata/memory.c | 7 ++----- hdata/paca.c | 2 +- hw/fsp/fsp.c | 2 +- hw/phb4.c | 28 ++++++++++++---------------- include/device.h | 1 + 8 files changed, 40 insertions(+), 50 deletions(-) diff --git a/core/device.c b/core/device.c index 0118d485f..f48a80159 100644 --- a/core/device.c +++ b/core/device.c @@ -593,11 +593,18 @@ u32 dt_property_get_cell(const struct dt_property *prop, u32 index) return fdt32_to_cpu(((const u32 *)prop->prop)[index]); } +u64 dt_property_get_u64(const struct dt_property *prop, u32 index) +{ + assert(prop->len >= (index+1)*sizeof(u64)); + /* Always aligned, so this works. */ + return fdt64_to_cpu(((const fdt64_t *)prop->prop)[index]); +} + void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val) { assert(prop->len >= (index+1)*sizeof(u32)); /* Always aligned, so this works. */ - ((u32 *)prop->prop)[index] = cpu_to_fdt32(val); + ((fdt32_t *)prop->prop)[index] = cpu_to_fdt32(val); } /* First child of this node. */ diff --git a/core/pci.c b/core/pci.c index 6c5c83bea..718569d64 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1547,16 +1547,8 @@ static void __noinline pci_add_one_device_node(struct phb *phb, char name[MAX_NAME]; char compat[MAX_NAME]; uint32_t rev_class, vdid; - __be32 reg[5]; uint8_t intpin; bool is_pcie; - const __be32 ranges_direct[] = { - /* 64-bit direct mapping. We know the bridges - * don't cover the entire address space so - * use 0xf00... as a good compromise. */ - cpu_to_be32(0x02000000), 0x0, 0x0, - cpu_to_be32(0x02000000), 0x0, 0x0, - cpu_to_be32(0xf0000000), 0x0}; pci_cfg_read32(phb, pd->bdfn, 0, &vdid); pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class); @@ -1633,9 +1625,7 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * entry in the "reg" property. That's enough for Linux and we might * even want to make this legit in future ePAPR */ - reg[0] = cpu_to_be32(pd->bdfn << 8); - reg[1] = reg[2] = reg[3] = reg[4] = 0; - dt_add_property(np, "reg", reg, sizeof(reg)); + dt_add_property_cells(np, "reg", pd->bdfn << 8, 0, 0, 0, 0); /* Print summary info about the device */ pci_print_summary_line(phb, pd, np, rev_class, cname); @@ -1670,7 +1660,13 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * (ie. an empty ranges property). * Instead add a ranges property that explicitly translates 1:1. */ - dt_add_property(np, "ranges", ranges_direct, sizeof(ranges_direct)); + dt_add_property_cells(np, "ranges", + /* 64-bit direct mapping. We know the bridges + * don't cover the entire address space so + * use 0xf00... as a good compromise. */ + 0x02000000, 0x0, 0x0, + 0x02000000, 0x0, 0x0, + 0xf0000000, 0x0); } void __noinline pci_add_device_nodes(struct phb *phb, diff --git a/hdata/iohub.c b/hdata/iohub.c index 2af040a2f..ef763a0ee 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -95,7 +95,6 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, unsigned int spci_xscom) { struct dt_node *pbcq; - uint32_t reg[6]; unsigned int hdif_vers; /* Get HDIF version */ @@ -109,13 +108,10 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, /* "reg" property contains in order the PE, PCI and SPCI XSCOM * addresses */ - reg[0] = cpu_to_be32(pe_xscom); - reg[1] = cpu_to_be32(0x20); - reg[2] = cpu_to_be32(pci_xscom); - reg[3] = cpu_to_be32(0x05); - reg[4] = cpu_to_be32(spci_xscom); - reg[5] = cpu_to_be32(0x15); - dt_add_property(pbcq, "reg", reg, sizeof(reg)); + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x20, + pci_xscom, 0x05, + spci_xscom, 0x15); /* A couple more things ... */ dt_add_property_strings(pbcq, "compatible", "ibm,power8-pbcq"); @@ -202,7 +198,6 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, int phb_base) { struct dt_node *pbcq; - uint32_t reg[4]; uint8_t active_phb_mask = hub->fab_br0_pdt; uint32_t pe_xscom = 0x4010c00 + (pec_index * 0x0000400); uint32_t pci_xscom = 0xd010800 + (pec_index * 0x1000000); @@ -214,11 +209,9 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, return NULL; /* "reg" property contains (in order) the PE and PCI XSCOM addresses */ - reg[0] = cpu_to_be32(pe_xscom); - reg[1] = cpu_to_be32(0x100); - reg[2] = cpu_to_be32(pci_xscom); - reg[3] = cpu_to_be32(0x200); - dt_add_property(pbcq, "reg", reg, sizeof(reg)); + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x100, + pci_xscom, 0x200); /* The hubs themselves go under the stacks */ dt_add_property_strings(pbcq, "compatible", "ibm,power9-pbcq"); diff --git a/hdata/memory.c b/hdata/memory.c index 9e5e99b9c..7839dea3f 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -77,24 +77,21 @@ static void append_chip_id(struct dt_node *mem, u32 id) { struct dt_property *prop; size_t len, i; - be32 *p; prop = __dt_find_property(mem, "ibm,chip-id"); if (!prop) return; len = prop->len >> 2; - p = (be32*)prop->prop; /* Check if it exists already */ for (i = 0; i < len; i++) { - if (be32_to_cpu(p[i]) == id) + if (dt_property_get_cell(prop, i) == id) return; } /* Add it to the list */ dt_resize_property(&prop, (len + 1) << 2); - p = (be32 *)prop->prop; - p[len] = cpu_to_be32(id); + dt_property_set_cell(prop, len, id); } static void update_status(struct dt_node *mem, uint32_t status) diff --git a/hdata/paca.c b/hdata/paca.c index 3e8d89856..7f6c5e7b7 100644 --- a/hdata/paca.c +++ b/hdata/paca.c @@ -97,7 +97,7 @@ static struct dt_node *find_cpu_by_hardware_proc_id(struct dt_node *root, if (!prop) return NULL; - if (be32_to_cpu(*(be32 *)prop->prop) == hw_proc_id) + if (dt_property_get_cell(prop, 0) == hw_proc_id) return i; } return NULL; diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index c11beb00e..73a995e64 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -1915,7 +1915,7 @@ static void fsp_init_links(struct dt_node *fsp_node) u64 reg; u32 link; - link = be32_to_cpu(((const __be32 *)linksprop->prop)[i]); + link = dt_property_get_cell(linksprop, i); fiop = &fsp->iopath[i]; fiop->psi = psi_find_link(link); if (fiop->psi == NULL) { diff --git a/hw/phb4.c b/hw/phb4.c index 5f8295192..04b6a2a2d 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5496,11 +5496,11 @@ static bool phb4_calculate_windows(struct phb4 *p) "ibm,mmio-windows", -1); assert(prop->len >= (2 * sizeof(uint64_t))); - p->mm0_base = be64_to_cpu(((__be64 *)prop->prop)[0]); - p->mm0_size = be64_to_cpu(((__be64 *)prop->prop)[1]); + p->mm0_base = dt_property_get_u64(prop, 0); + p->mm0_size = dt_property_get_u64(prop, 1); if (prop->len > 16) { - p->mm1_base = be64_to_cpu(((__be64 *)prop->prop)[2]); - p->mm1_size = be64_to_cpu(((__be64 *)prop->prop)[3]); + p->mm1_base = dt_property_get_u64(prop, 2); + p->mm1_size = dt_property_get_u64(prop, 3); } /* Sort them so that 0 is big and 1 is small */ @@ -5612,11 +5612,11 @@ static void phb4_create(struct dt_node *np) /* Get the various XSCOM register bases from the device-tree */ prop = dt_require_property(np, "ibm,xscom-bases", 5 * sizeof(uint32_t)); - p->pe_xscom = be32_to_cpu(((__be32 *)prop->prop)[0]); - p->pe_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[1]); - p->pci_xscom = be32_to_cpu(((__be32 *)prop->prop)[2]); - p->pci_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[3]); - p->etu_xscom = be32_to_cpu(((__be32 *)prop->prop)[4]); + p->pe_xscom = dt_property_get_cell(prop, 0); + p->pe_stk_xscom = dt_property_get_cell(prop, 1); + p->pci_xscom = dt_property_get_cell(prop, 2); + p->pci_stk_xscom = dt_property_get_cell(prop, 3); + p->etu_xscom = dt_property_get_cell(prop, 4); /* * We skip the initial PERST assertion requested by the generic code @@ -5777,7 +5777,6 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint64_t val, phb_bar = 0, irq_bar = 0, bar_en; uint64_t mmio0_bar = 0, mmio0_bmask, mmio0_sz; uint64_t mmio1_bar = 0, mmio1_bmask, mmio1_sz; - uint64_t reg[4]; void *foo; __be64 mmio_win[4]; unsigned int mmio_win_sz; @@ -5875,18 +5874,15 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, prlog_once(PR_DEBUG, "Version reg: 0x%016llx\n", in_be64(foo)); /* Create PHB node */ - reg[0] = cpu_to_be64(phb_bar); - reg[1] = cpu_to_be64(0x1000); - reg[2] = cpu_to_be64(irq_bar); - reg[3] = cpu_to_be64(0x10000000); - np = dt_new_addr(dt_root, "pciex", phb_bar); if (!np) return; dt_add_property_strings(np, "compatible", "ibm,power9-pciex", "ibm,ioda3-phb"); dt_add_property_strings(np, "device_type", "pciex"); - dt_add_property(np, "reg", reg, sizeof(reg)); + dt_add_property_u64s(np, "reg", + phb_bar, 0x1000, + irq_bar, 0x10000000); /* Everything else is handled later by skiboot, we just * stick a few hints here diff --git a/include/device.h b/include/device.h index 25325ec07..4f7a0983f 100644 --- a/include/device.h +++ b/include/device.h @@ -130,6 +130,7 @@ void dt_resize_property(struct dt_property **prop, size_t len); void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val); u32 dt_property_get_cell(const struct dt_property *prop, u32 index); +u64 dt_property_get_u64(const struct dt_property *prop, u32 index); /* First child of this node. */ struct dt_node *dt_first(const struct dt_node *root); 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:24 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:44 +1000 Message-Id: <20191106121047.14389-27-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 26/29] Add more sparse endian annotations X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This fixes quite a few sparse endian annotations across the tree. Signed-off-by: Nicholas Piggin --- core/device.c | 17 +++++++++-------- core/fdt.c | 2 +- core/interrupts.c | 3 ++- core/mem_region.c | 2 +- core/pci.c | 2 +- core/trace.c | 3 ++- hdata/fsp.c | 2 +- hdata/memory.c | 8 ++++---- hdata/spira.c | 2 +- hw/ast-bmc/ast-sf-ctrl.c | 5 +++-- hw/imc.c | 4 ++-- hw/psi.c | 2 +- hw/slw.c | 10 +++++----- include/ipmi.h | 2 +- include/opal-internal.h | 4 ++-- libflash/mbox-flash.c | 8 ++++---- libstb/secureboot.c | 2 +- platforms/astbmc/vesnin.c | 8 ++++---- 18 files changed, 45 insertions(+), 41 deletions(-) diff --git a/core/device.c b/core/device.c index f48a80159..6c7794677 100644 --- a/core/device.c +++ b/core/device.c @@ -514,12 +514,12 @@ struct dt_property *__dt_add_property_cells(struct dt_node *node, int count, ...) { struct dt_property *p; - u32 *val; + fdt32_t *val; unsigned int i; va_list args; p = new_property(node, name, count * sizeof(u32)); - val = (u32 *)p->prop; + val = (fdt32_t *)p->prop; va_start(args, count); for (i = 0; i < count; i++) val[i] = cpu_to_fdt32(va_arg(args, u32)); @@ -532,12 +532,12 @@ struct dt_property *__dt_add_property_u64s(struct dt_node *node, int count, ...) { struct dt_property *p; - u64 *val; + fdt64_t *val; unsigned int i; va_list args; p = new_property(node, name, count * sizeof(u64)); - val = (u64 *)p->prop; + val = (fdt64_t *)p->prop; va_start(args, count); for (i = 0; i < count; i++) val[i] = cpu_to_fdt64(va_arg(args, u64)); @@ -590,7 +590,7 @@ u32 dt_property_get_cell(const struct dt_property *prop, u32 index) { assert(prop->len >= (index+1)*sizeof(u32)); /* Always aligned, so this works. */ - return fdt32_to_cpu(((const u32 *)prop->prop)[index]); + return fdt32_to_cpu(((const fdt32_t *)prop->prop)[index]); } u64 dt_property_get_u64(const struct dt_property *prop, u32 index) @@ -918,7 +918,7 @@ void dt_expand(const void *fdt) u64 dt_get_number(const void *pdata, unsigned int cells) { - const u32 *p = pdata; + const __be32 *p = pdata; u64 ret = 0; while(cells--) @@ -1095,6 +1095,7 @@ void dt_adjust_subtree_phandle(struct dt_node *dev, struct dt_node *node; struct dt_property *prop; u32 phandle, max_phandle = 0, import_phandle = new_phandle(); + __be32 p; const char **name; dt_for_each_node(dev, node) { @@ -1117,8 +1118,8 @@ void dt_adjust_subtree_phandle(struct dt_node *dev, continue; phandle = dt_prop_get_u32(node, *name); phandle += import_phandle; - phandle = cpu_to_be32(phandle); - memcpy((char *)&prop->prop, &phandle, prop->len); + p = cpu_to_be32(phandle); + memcpy((char *)&prop->prop, &p, prop->len); } } diff --git a/core/fdt.c b/core/fdt.c index e093e8b54..92fdc5b03 100644 --- a/core/fdt.c +++ b/core/fdt.c @@ -136,7 +136,7 @@ static void flatten_dt_node(void *fdt, const struct dt_node *root, static void create_dtb_reservemap(void *fdt, const struct dt_node *root) { uint64_t base, size; - const uint64_t *ranges; + const __be64 *ranges; const struct dt_property *prop; int i; diff --git a/core/interrupts.c b/core/interrupts.c index d4a2c3124..681483209 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -194,7 +194,8 @@ void add_opal_interrupts(void) { struct irq_source *is; unsigned int i, ns, tns = 0, count = 0; - uint32_t *irqs = NULL, isn; + uint32_t isn; + __be32 *irqs = NULL; char *names = NULL; lock(&irq_lock); diff --git a/core/mem_region.c b/core/mem_region.c index 06cef1b2b..3ab039aba 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -1448,7 +1448,7 @@ void mem_region_add_dt_reserved(void) struct mem_region *region; void *names, *ranges; struct dt_node *node; - uint64_t *range; + fdt64_t *range; char *name; names_len = 0; diff --git a/core/pci.c b/core/pci.c index 718569d64..4d0671661 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1332,7 +1332,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np, struct pci_lsi_state *lstate, uint8_t swizzle) { - uint32_t *map, *p; + __be32 *p, *map; int dev, irq, esize, edevcount; size_t map_size; diff --git a/core/trace.c b/core/trace.c index 614be08d7..dc746b833 100644 --- a/core/trace.c +++ b/core/trace.c @@ -158,7 +158,8 @@ void trace_add(union trace *trace, u8 type, u16 len) static void trace_add_dt_props(void) { unsigned int i; - u64 *prop, tmask; + fdt64_t *prop; + u64 tmask; struct dt_node *exports; char tname[256]; diff --git a/hdata/fsp.c b/hdata/fsp.c index fe36eef18..d351f5ac5 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -174,7 +174,7 @@ static uint32_t fsp_create_link(const struct spss_iopath *iopath, int index, static void fsp_create_links(const void *spss, int index, struct dt_node *fsp_node) { - uint32_t *links = NULL; + __be32 *links = NULL; unsigned int i, lp, lcount = 0; int count; diff --git a/hdata/memory.c b/hdata/memory.c index 7839dea3f..9c588ff61 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -329,8 +329,8 @@ static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea) static void vpd_parse_spd(struct dt_node *dimm, const char *spd, u32 size) { - u16 *vendor; - u32 *sn; + __be16 *vendor; + __be32 *sn; /* SPD is too small */ if (size < 512) { @@ -355,14 +355,14 @@ static void vpd_parse_spd(struct dt_node *dimm, const char *spd, u32 size) dt_add_property_cells(dimm, "product-version", spd[0x15d]); /* Serial number */ - sn = (u32 *)&spd[0x145]; + sn = (__be32 *)&spd[0x145]; dt_add_property_cells(dimm, "serial-number", be32_to_cpu(*sn)); /* Part number */ dt_add_property_nstr(dimm, "part-number", &spd[0x149], 20); /* Module manufacturer ID */ - vendor = (u16 *)&spd[0x140]; + vendor = (__be16 *)&spd[0x140]; dt_add_property_cells(dimm, "manufacturer-id", be16_to_cpu(*vendor)); } diff --git a/hdata/spira.c b/hdata/spira.c index 6900b71e8..cde81cd9f 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -993,7 +993,7 @@ static void opal_dump_add_mpipl_boot(const struct iplparams_iplparams *p) static void add_opal_dump_node(void) { - u64 fw_load_area[4]; + __be64 fw_load_area[4]; struct dt_node *node; opal_node = dt_new_check(dt_root, "ibm,opal"); diff --git a/hw/ast-bmc/ast-sf-ctrl.c b/hw/ast-bmc/ast-sf-ctrl.c index ece847d6b..e97315067 100644 --- a/hw/ast-bmc/ast-sf-ctrl.c +++ b/hw/ast-bmc/ast-sf-ctrl.c @@ -169,12 +169,13 @@ static void ast_sf_end_cmd(struct ast_sf_ctrl *ct) static int ast_sf_send_addr(struct ast_sf_ctrl *ct, uint32_t addr) { const void *ap; + __be32 tmp; /* Layout address MSB first in memory */ - addr = cpu_to_be32(addr); + tmp = cpu_to_be32(addr); /* Send the right amount of bytes */ - ap = (char *)&addr; + ap = (char *)&tmp; if (ct->mode_4b) return ast_copy_to_ahb(ct->flash, ap, 4); diff --git a/hw/imc.c b/hw/imc.c index 16b060d39..36c2cf3a5 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -448,8 +448,8 @@ void imc_catalog_preload(void) static void imc_dt_update_nest_node(struct dt_node *dev) { struct proc_chip *chip; - uint64_t *base_addr = NULL; - uint32_t *chipids = NULL; + __be64 *base_addr = NULL; + __be32 *chipids = NULL; int i=0, nr_chip = nr_chips(); struct dt_node *node; const struct dt_property *type; diff --git a/hw/psi.c b/hw/psi.c index 3b497a092..381b35eda 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -782,7 +782,7 @@ static void psi_activate_phb(struct psi *psi) static void psi_create_p9_int_map(struct psi *psi, struct dt_node *np) { - uint32_t map[P9_PSI_NUM_IRQS][4]; + __be32 map[P9_PSI_NUM_IRQS][4]; int i; for (i = 0; i < P9_PSI_NUM_IRQS; i++) { diff --git a/hw/slw.c b/hw/slw.c index f1d0298b3..e058232ff 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -730,8 +730,8 @@ void add_cpu_idle_state_properties(void) bool has_stop_inst = false; u8 i; - u64 *pm_ctrl_reg_val_buf; - u64 *pm_ctrl_reg_mask_buf; + fdt64_t *pm_ctrl_reg_val_buf; + fdt64_t *pm_ctrl_reg_mask_buf; u32 supported_states_mask; u32 opal_disabled_states_mask = ~0xEC000000; /* all but stop11 */ const char* nvram_disable_str; @@ -744,9 +744,9 @@ void add_cpu_idle_state_properties(void) /* Buffers to hold idle state properties */ char *name_buf, *alloced_name_buf; - u32 *latency_ns_buf; - u32 *residency_ns_buf; - u32 *flags_buf; + fdt32_t *latency_ns_buf; + fdt32_t *residency_ns_buf; + fdt32_t *flags_buf; prlog(PR_DEBUG, "CPU idle state device tree init\n"); diff --git a/include/ipmi.h b/include/ipmi.h index 4f5134745..50deec01a 100644 --- a/include/ipmi.h +++ b/include/ipmi.h @@ -164,7 +164,7 @@ struct ipmi_msg { }; struct ipmi_backend { - __be64 opal_event_ipmi_recv; + uint64_t opal_event_ipmi_recv; struct ipmi_msg *(*alloc_msg)(size_t, size_t); void (*free_msg)(struct ipmi_msg *); int (*queue_msg)(struct ipmi_msg *); diff --git a/include/opal-internal.h b/include/opal-internal.h index fd2187f09..83bf77084 100644 --- a/include/opal-internal.h +++ b/include/opal-internal.h @@ -49,8 +49,8 @@ extern struct dt_node *opal_node; extern void opal_table_init(void); extern void opal_update_pending_evt(uint64_t evt_mask, uint64_t evt_values); -__be64 opal_dynamic_event_alloc(void); -void opal_dynamic_event_free(__be64 event); +uint64_t opal_dynamic_event_alloc(void); +void opal_dynamic_event_free(uint64_t event); extern void add_opal_node(void); #define opal_register(token, func, nargs) \ diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 5df020f55..3fd2c057a 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -239,23 +239,23 @@ static void msg_put_u8(struct bmc_mbox_msg *msg, int i, uint8_t val) static uint16_t msg_get_u16(struct bmc_mbox_msg *msg, int i) { - return le16_to_cpu(*(uint16_t *)(&msg->args[i])); + return le16_to_cpu(*(__le16 *)(&msg->args[i])); } static void msg_put_u16(struct bmc_mbox_msg *msg, int i, uint16_t val) { - uint16_t tmp = cpu_to_le16(val); + __le16 tmp = cpu_to_le16(val); memcpy(&msg->args[i], &tmp, sizeof(val)); } static uint32_t msg_get_u32(struct bmc_mbox_msg *msg, int i) { - return le32_to_cpu(*(uint32_t *)(&msg->args[i])); + return le32_to_cpu(*(__le32 *)(&msg->args[i])); } static void msg_put_u32(struct bmc_mbox_msg *msg, int i, uint32_t val) { - uint32_t tmp = cpu_to_le32(val); + __le32 tmp = cpu_to_le32(val); memcpy(&msg->args[i], &tmp, sizeof(val)); } diff --git a/libstb/secureboot.c b/libstb/secureboot.c index bfc98f2ae..022e2aa09 100644 --- a/libstb/secureboot.c +++ b/libstb/secureboot.c @@ -163,7 +163,7 @@ void secureboot_init(void) int secureboot_verify(enum resource_id id, void *buf, size_t len) { const char *name; - uint64_t log; + __be64 log; int rc = -1; name = flash_map_resource_name(id); diff --git a/platforms/astbmc/vesnin.c b/platforms/astbmc/vesnin.c index bd412aa8d..b1d909e29 100644 --- a/platforms/astbmc/vesnin.c +++ b/platforms/astbmc/vesnin.c @@ -38,13 +38,13 @@ * All fields have Big Endian byte order. */ struct pciinv_device { - uint16_t domain_num; + beint16_t domain_num; uint8_t bus_num; uint8_t device_num; uint8_t func_num; - uint16_t vendor_id; - uint16_t device_id; - uint32_t class_code; + beint16_t vendor_id; + beint16_t device_id; + beint32_t class_code; uint8_t revision; } __packed; From patchwork Wed Nov 6 12:10:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477Qfn5MR4z9sNx for ; Wed, 6 Nov 2019 23:23:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:26 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:45 +1000 Message-Id: <20191106121047.14389-28-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 27/29] Fix simple sparse warnings X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Should be no real code change, these mostly update type declarations that sparse complains about. Signed-off-by: Nicholas Piggin --- core/init.c | 4 ++-- core/pci.c | 2 +- core/platform.c | 2 +- hdata/tpmrel.c | 2 +- hw/fsp/fsp-dpo.c | 2 +- hw/imc.c | 4 ++-- hw/vas.c | 2 +- include/device.h | 3 ++- include/skiboot.h | 2 +- libc/stdlib/labs.c | 2 +- platforms/astbmc/common.c | 4 ++-- platforms/astbmc/p8dtu.c | 2 +- platforms/astbmc/p9dsu.c | 2 +- platforms/astbmc/witherspoon.c | 6 +++--- 14 files changed, 20 insertions(+), 19 deletions(-) diff --git a/core/init.c b/core/init.c index 1a4f9f939..341b148bb 100644 --- a/core/init.c +++ b/core/init.c @@ -531,7 +531,7 @@ static int64_t cpu_disable_ME_RI_all(void) return OPAL_SUCCESS; } -void *fdt; +static void *fdt; void __noreturn load_and_boot_kernel(bool is_reboot) { @@ -801,7 +801,7 @@ static void setup_branch_null_catcher(void) * ABI v1 (ie. big endian). This will be broken if we ever * move to ABI v2 (ie little endian) */ - memcpy_null(0, bn, 16); + memcpy_null((void *)0, bn, 16); } #endif diff --git a/core/pci.c b/core/pci.c index 4d0671661..59b395919 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1371,7 +1371,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np, dt_add_property_cells(np, "interrupt-map-mask", 0xf800, 0, 0, 7); } - map_size = esize * edevcount * 4 * sizeof(uint32_t); + map_size = esize * edevcount * 4 * sizeof(u32); map = p = zalloc(map_size); if (!map) { prerror("Failed to allocate interrupt-map-mask !\n"); diff --git a/core/platform.c b/core/platform.c index 9f1873c90..2544f0ccf 100644 --- a/core/platform.c +++ b/core/platform.c @@ -184,7 +184,7 @@ static int generic_start_preload_resource(enum resource_id id, uint32_t subid, } /* These values will work for a ZZ booted using BML */ -const struct platform_ocapi generic_ocapi = { +static const struct platform_ocapi generic_ocapi = { .i2c_engine = 1, .i2c_port = 4, .i2c_reset_addr = 0x20, diff --git a/hdata/tpmrel.c b/hdata/tpmrel.c index 1fe14c75e..9796fc732 100644 --- a/hdata/tpmrel.c +++ b/hdata/tpmrel.c @@ -118,7 +118,7 @@ static struct dt_node *get_hb_reserved_memory(const char *label) return NULL; } -struct { +static struct { uint32_t type; const char *compat; } cvc_services[] = { diff --git a/hw/fsp/fsp-dpo.c b/hw/fsp/fsp-dpo.c index 0796d9ae9..1f7bacf04 100644 --- a/hw/fsp/fsp-dpo.c +++ b/hw/fsp/fsp-dpo.c @@ -18,7 +18,7 @@ #define DPO_CMD_SGN_BYTE1 0x20 /* Byte[1] signature */ #define DPO_TIMEOUT 2700 /* 45 minutes in seconds */ -bool fsp_dpo_pending; +static bool fsp_dpo_pending; static unsigned long fsp_dpo_init_tb; /* diff --git a/hw/imc.c b/hw/imc.c index 36c2cf3a5..3a5382c0c 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -455,8 +455,8 @@ static void imc_dt_update_nest_node(struct dt_node *dev) const struct dt_property *type; /* Add the base_addr and chip-id properties for the nest node */ - base_addr = malloc(sizeof(uint64_t) * nr_chip); - chipids = malloc(sizeof(uint32_t) * nr_chip); + base_addr = malloc(sizeof(u64) * nr_chip); + chipids = malloc(sizeof(u32) * nr_chip); for_each_chip(chip) { base_addr[i] = cpu_to_be64(chip->homer_base); chipids[i] = cpu_to_be32(chip->id); diff --git a/hw/vas.c b/hw/vas.c index 82a07904c..3303a12fe 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -457,7 +457,7 @@ static int init_vas_inst(struct dt_node *np, bool enable) } -void vas_init() +void vas_init(void) { bool enabled; struct dt_node *np; diff --git a/include/device.h b/include/device.h index 4f7a0983f..f17b089d8 100644 --- a/include/device.h +++ b/include/device.h @@ -118,7 +118,8 @@ struct dt_property *__dt_add_property_u64s(struct dt_node *node, static inline struct dt_property *dt_add_property_u64(struct dt_node *node, const char *name, u64 val) { - return dt_add_property_cells(node, name, (u32)(val >> 32), (u32)val); + return dt_add_property_cells(node, name, (u32)(val >> 32), + (u32)(val & 0xffffffffUL)); } void dt_del_property(struct dt_node *node, struct dt_property *prop); diff --git a/include/skiboot.h b/include/skiboot.h index e9d57decd..6946b8056 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -318,7 +318,7 @@ extern void fake_rtc_init(void); struct stack_frame; extern void exception_entry(struct stack_frame *stack); extern void exception_entry_pm_sreset(void); -extern void exception_entry_pm_mce(void); +extern void __noreturn exception_entry_pm_mce(void); /* Assembly in head.S */ extern void disable_machine_check(void); diff --git a/libc/stdlib/labs.c b/libc/stdlib/labs.c index 9b68bb275..8bd15eab9 100644 --- a/libc/stdlib/labs.c +++ b/libc/stdlib/labs.c @@ -19,7 +19,7 @@ * Returns the absolute value of the long integer argument */ -long int labs(long int n) +long int __attribute__((const)) labs(long int n) { return (n > 0) ? n : -n; } diff --git a/platforms/astbmc/common.c b/platforms/astbmc/common.c index 15ac231fb..de837f326 100644 --- a/platforms/astbmc/common.c +++ b/platforms/astbmc/common.c @@ -503,13 +503,13 @@ void astbmc_exit(void) ipmi_wdt_final_reset(); } -const struct bmc_sw_config bmc_sw_ami = { +static const struct bmc_sw_config bmc_sw_ami = { .ipmi_oem_partial_add_esel = IPMI_CODE(0x3a, 0xf0), .ipmi_oem_pnor_access_status = IPMI_CODE(0x3a, 0x07), .ipmi_oem_hiomap_cmd = IPMI_CODE(0x3a, 0x5a), }; -const struct bmc_sw_config bmc_sw_openbmc = { +static const struct bmc_sw_config bmc_sw_openbmc = { .ipmi_oem_partial_add_esel = IPMI_CODE(0x3a, 0xf0), .ipmi_oem_hiomap_cmd = IPMI_CODE(0x3a, 0x5a), }; diff --git a/platforms/astbmc/p8dtu.c b/platforms/astbmc/p8dtu.c index c62223b24..a9d8dc068 100644 --- a/platforms/astbmc/p8dtu.c +++ b/platforms/astbmc/p8dtu.c @@ -223,7 +223,7 @@ static const struct bmc_sw_config bmc_sw_smc = { }; /* Provided by Eric Chen (SMC) */ -const struct bmc_hw_config p8dtu_bmc_hw = { +static const struct bmc_hw_config p8dtu_bmc_hw = { .scu_revision_id = 0x02010303, .mcr_configuration = 0x00000577, .mcr_scu_mpll = 0x000050c0, diff --git a/platforms/astbmc/p9dsu.c b/platforms/astbmc/p9dsu.c index d49f7fe07..5c9756ec6 100644 --- a/platforms/astbmc/p9dsu.c +++ b/platforms/astbmc/p9dsu.c @@ -695,7 +695,7 @@ static const struct bmc_sw_config bmc_sw_smc = { }; /* Provided by Eric Chen (SMC) */ -const struct bmc_hw_config p9dsu_bmc_hw = { +static const struct bmc_hw_config p9dsu_bmc_hw = { .scu_revision_id = 0x04030303, .mcr_configuration = 0x11000756, .mcr_scu_mpll = 0x000071c1, diff --git a/platforms/astbmc/witherspoon.c b/platforms/astbmc/witherspoon.c index 8aaed975f..edf84fb89 100644 --- a/platforms/astbmc/witherspoon.c +++ b/platforms/astbmc/witherspoon.c @@ -325,7 +325,7 @@ i2c_failed: return; } -const struct platform_ocapi witherspoon_ocapi = { +static const struct platform_ocapi witherspoon_ocapi = { .i2c_engine = 1, .i2c_port = 4, .odl_phy_swap = false, @@ -370,8 +370,8 @@ static int gpu_slot_to_num(const char *slot) static void npu2_phb_nvlink_dt(struct phb *npuphb) { - struct dt_node *g[3] = { 0 }; /* Current maximum is 3 GPUs per 1 NPU */ - struct dt_node *n[6] = { 0 }; + struct dt_node *g[3] = { NULL }; /* Current maximum 3 GPUs per 1 NPU */ + struct dt_node *n[6] = { NULL }; int max_gpus, i, gpuid, first, last; struct npu2 *npu2_phb = phb_to_npu2_nvlink(npuphb); struct pci_device *npd; From patchwork Wed Nov 6 12:10:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QgB5j8Cz9sNx for ; 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[203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:29 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:46 +1000 Message-Id: <20191106121047.14389-29-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 28/29] slw: slw_reinit fix array overrun X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The slw patch saving array is too small, which results in slw_reinit overwriting 32 bytes beyond the end of it. The size is increased to 0x100, which is the architecture interrupt vector size. Signed-off-by: Nicholas Piggin --- hw/slw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/slw.c b/hw/slw.c index e058232ff..5a7e24e58 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -28,7 +28,7 @@ #include #include -#define MAX_RESET_PATCH_SIZE 64 +#define MAX_RESET_PATCH_SIZE 0x100 static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; From patchwork Wed Nov 6 12:10:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1190372 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 477QgY2mpcz9sNx for ; Wed, 6 Nov 2019 23:23:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZimJ9pUa"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 477QgY1JxlzF5HK for ; Wed, 6 Nov 2019 23:23:53 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::644; helo=mail-pl1-x644.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZimJ9pUa"; dkim-atps=neutral Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 477QQV2rG2zF5vv for ; Wed, 6 Nov 2019 23:12:34 +1100 (AEDT) Received: by mail-pl1-x644.google.com with SMTP id p13so11335689pll.4 for ; Wed, 06 Nov 2019 04:12:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wx7F5Xn3ltchhB6Szpvsw5dsFCqNb1nbH62LDDO6CmI=; b=ZimJ9pUau/sUf6+uIq07aZHCTo4J5cPI/dSrKemZTNs7+/tcxyXNR7R7EGFgOBw/eV RzvrNnMw5N4djA9YJjsM9evQK4MdF+9swFgYSqxEPH8XTU5luwceERObLKpPie2WceEZ NqUAfknDYB+qvlLpgdzDQ7dh6aoDqUcWN8LP7BuC6xC567tqxItZNBChtBO6bKpWtIXn S3xxw1S/jb3VGtv+fEHixjtnsAbOXvL8ZyAcPeYn65iUXPZxWkTFbWGGE75XXQSIwDgp 5JPKbrRLdmJqQo2x54dRw6kjcibB1X2aI/xYHdrCcdXgBOy4lOdPtiiwnHLGkeuQHvOj 25FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wx7F5Xn3ltchhB6Szpvsw5dsFCqNb1nbH62LDDO6CmI=; b=DFfEWleD6qcYLtwQffJcL0dvV2Q5nYiXuXmkXPRAnYIUIwHH3BJ2hPEy6BtMgHlztf JdYp9Wy0IWI7Ruh3LiKTQK1nxxZWku4ipD2VO5sYnFY60kgJnxFl0omb3OdFLUGittb9 DZDSV0sb3NG8UFkongIABSwSV8sRgLiEDZJqwVXe062b60N+Pun/uIF71aewVUraT2BP dwq+0sN3ZTsGOjvY3cn4w8rMlrhpR4NIkcwTxMq5JmO3h1/uEk2hVx/ThgzJLTMocJqV orz7wz19oyfnlEmhtitlGOhFNm9Oca0EC6b/qQ+fmzXIY7ANimowae6Lh/SyNFBVR6sx Pm5A== X-Gm-Message-State: APjAAAX659WP4jMZ3SAm3RbdmXH70Jy6nHCCJw6KTCknombEEcn6+4BM 8vVb+XwkwXcLXPzmghPkT2w/WZU7ScA= X-Google-Smtp-Source: APXvYqxxq8xBSmlm26EUGu2e3ml7xImDpSt96cT/RnvoPDSalXl3o6FGeU89QzAhgfXs56CDqd6FeQ== X-Received: by 2002:a17:902:a508:: with SMTP id s8mr2280473plq.26.1573042351929; Wed, 06 Nov 2019 04:12:31 -0800 (PST) Received: from bobo.local0.net (208.157.221.203.dial.dynamic.acc50-nort-cbr.comindico.com.au. [203.221.157.208]) by smtp.gmail.com with ESMTPSA id y8sm13870329pfl.8.2019.11.06.04.12.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2019 04:12:31 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 6 Nov 2019 22:10:47 +1000 Message-Id: <20191106121047.14389-30-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106121047.14389-1-npiggin@gmail.com> References: <20191106121047.14389-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v6 29/29] build: fix non-constant build asserts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" BUILD_ASSERT can not be used for constants generated by the assembler or linker. This results in variable length arrays that do not catch the failure condition. This was caught by sparse. Remove these and add some as/ld alternatives. Signed-off-by: Nicholas Piggin --- asm/head.S | 4 ++++ core/init.c | 2 -- core/mem_region.c | 4 ---- hw/slw.c | 7 +------ skiboot.lds.S | 2 ++ 5 files changed, 7 insertions(+), 12 deletions(-) diff --git a/asm/head.S b/asm/head.S index 68f153b36..b565f6c9c 100644 --- a/asm/head.S +++ b/asm/head.S @@ -582,6 +582,10 @@ reset_patch_start: .global reset_patch_end reset_patch_end: +.if reset_patch_end - reset_patch_start > 0x100 + .error "Reset patch overflow" +.endif + /* Wakeup vector in r3 */ .global reset_wakeup reset_wakeup: diff --git a/core/init.c b/core/init.c index 341b148bb..d32791be9 100644 --- a/core/init.c +++ b/core/init.c @@ -840,8 +840,6 @@ void copy_exception_vectors(void) * this is the boot flag used by CPUs still potentially entering * skiboot. */ - BUILD_ASSERT((&reset_patch_end - &reset_patch_start) < - EXCEPTION_VECTORS_END - 0x100); memcpy((void *)0x100, (void *)(SKIBOOT_BASE + 0x100), EXCEPTION_VECTORS_END - 0x100); sync_icache(); diff --git a/core/mem_region.c b/core/mem_region.c index 3ab039aba..eb48a1a11 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -1058,10 +1058,6 @@ void mem_region_init(void) struct dt_node *i; bool rc; - /* Ensure we have no collision between skiboot core and our heap */ - extern char _end[]; - BUILD_ASSERT(HEAP_BASE >= (uint64_t)_end); - /* * Add associativity properties outside of the lock * to avoid recursive locking caused by allocations diff --git a/hw/slw.c b/hw/slw.c index 5a7e24e58..97df81f1c 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -28,9 +28,7 @@ #include #include -#define MAX_RESET_PATCH_SIZE 0x100 - -static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; +static uint32_t slw_saved_reset[0x100]; static bool slw_current_le = false; @@ -146,9 +144,6 @@ static void slw_patch_reset(void) { uint32_t *src, *dst, *sav; - BUILD_ASSERT((&reset_patch_end - &reset_patch_start) <= - MAX_RESET_PATCH_SIZE); - src = &reset_patch_start; dst = (uint32_t *)0x100; sav = slw_saved_reset; diff --git a/skiboot.lds.S b/skiboot.lds.S index 12981f3c8..1822334b2 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -233,6 +233,8 @@ SECTIONS _ebss = .; _end = .; + ASSERT(HEAP_BASE >= _end, "Heap collision with image") + DEBUG_SECTIONS /* Optional kernel image */