From patchwork Tue Nov 5 13:14:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mkazB2Pd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsR0dPmz9sPv for ; Wed, 6 Nov 2019 00:15:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389044AbfKENPF (ORCPT ); Tue, 5 Nov 2019 08:15:05 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:56297 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388711AbfKENPE (ORCPT ); Tue, 5 Nov 2019 08:15:04 -0500 Received: by mail-wm1-f67.google.com with SMTP id m17so11588612wmi.5; Tue, 05 Nov 2019 05:15:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GcH9L4v6hLjTb03WVEbtc4W0wjAfbHPhhP9UPT/iBJg=; b=mkazB2Pdvg74n1/2dtJ33b6WxUCwe3pb6cl8egWK2Fb8IbtMhU1cuF8jUjvQP8lZu3 yY7SPxRbayA9XWOkRweEjKT9BO2dyBqR+cZNDafVBQFcoHH9MLpS1XeiN6xFbJ4PGtM3 cr2gI7khpQQnPxCeUSA2YgjcW2gIr0h8H4laylTS6z5488b69YQ+eUG9QCvnFQq2hl/N k8wJoFpVRdFQu/hoj11/yxhvJCves7Ls71xjQoxN6KKOHWaCDACgiJWUtMnuCyiP4zPT zqWIo+EDoJr3t7pW8fkkYhXZbSz54+IPmXYM1QT4B5dFumns64p2/R2fGRjF2xdoOtFP Hq5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GcH9L4v6hLjTb03WVEbtc4W0wjAfbHPhhP9UPT/iBJg=; b=Gl0QJiVAVN/j+XBZrOs3tNh5o0f4bvgtMlgL2gwixoNKDgRhQdUl2qA0HtiB9/gEhS YF8g9yFiJ4bYfjuM6UVZAIPBOd4wxXX6tlUGSmXQcMc4fLSHwI6zg82G+rj31LcyTXZf DA9hirF34DPMlOM5WJf9pjEeN21rh8wdG3BE347Le/ttsV5o8OMcGEXbbWmKMr7mcQ/Y mhENOPusT+A0Cl1aE8Zgy9ufk3SIBLv1wBn4hkORN4MYJrcXGzjnCHYRU7DHD8wjo7vI CdsjYlgX7muMP1gYTlfeBkoJ2A5pDnA74zgLDUuSiDy9painTTxqIL4fA2QCLN/OSs+T kDNA== X-Gm-Message-State: APjAAAXzOzMVCXv8mngnmLWvVTd4O51Odq+R00tDhHNS/CnJJJgpoINe WnkKEtmoMsTe+IFFlE1nE1U= X-Google-Smtp-Source: APXvYqwZaocVvRMmSfJBgecb0AwHpmFVmxqomctE7z4EdhbBlsnv7DVhdCkYdM3JjAQLpKZcglC+Dw== X-Received: by 2002:a1c:3c42:: with SMTP id j63mr4273646wma.90.1572959701957; Tue, 05 Nov 2019 05:15:01 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:01 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Tue, 5 Nov 2019 14:14:50 +0100 Message-Id: <20191105131456.32400-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..9fc32c1d94b4 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,50 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + items: + - description: Bus Clock + - description: Module Clock + + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clock-names: true + resets: maxItems: 1 + if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + + else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +91,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Tue Nov 5 13:14:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f3YD4Ug7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsT1dxPz9sPZ for ; Wed, 6 Nov 2019 00:15:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388987AbfKENPW (ORCPT ); Tue, 5 Nov 2019 08:15:22 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52333 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388945AbfKENPF (ORCPT ); Tue, 5 Nov 2019 08:15:05 -0500 Received: by mail-wm1-f67.google.com with SMTP id c17so13507734wmk.2; Tue, 05 Nov 2019 05:15:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DFpznEDpNoqbmapZynyzmsx8KHYXXRH6cqD0i8XMxAs=; b=f3YD4Ug76oHoUiN2crsPXDr3EPqby4+c3lsOUMycDhYNq/6o4SNBSto4xo+qsJAwx3 Zol/D6WTEF5MjdbCemPv4t29kj/WxcDBW7dtegaY7sCh7B2DYPqbQmm2uAAdA9PolHl3 IgiUuJwwNkd8xpU9S2QQxN3hvuI3AbpYvrvZuZ7c6Aa8wedCqkA+lC+CfUeGCSNw4e17 y69oRLohtZEtA5pIeBk/9WtzIaf2S0VMULc9fc+xCancs6LArLYHor6ZihYeQ3JfzkOr U6j3UZE8HlOxHVyMNtm8UqiUgLWd6k6oMeiy7UtLOlcSaPVbWB+ijzW8qfAAh5aIrImD rCng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DFpznEDpNoqbmapZynyzmsx8KHYXXRH6cqD0i8XMxAs=; b=aprZpJzAmyHRv3uPHdIAX6YdhWp0FwutXdzkiXjzYPM9HmYRM7noyIL7vUP9PxoXd7 b4Oy1BKKNQuCLsH4LFtnr4fVSuauhmruZUQuKrdM1cTEDK7kr8Fm/y9fUXSijdlSP/5O 8hxCXasGfYQZQPU1iD+YN+8CjyEHnV4pKOHbItNNF5En4RZbvAtygBwMDo1axdUbnkM3 kCh78cr8090eKyMX94Zhug/tySAuj/xTF7CAKZfRkiuEgFbv3EjmK6gSWfy88Jy2ol4F gEu2Wc1NT5VfQfN9qSUsQI57+PIZIuqm1y6ZRBmt47m9x6wFZCV3jO1kx1lRE3CfUxPJ oGuA== X-Gm-Message-State: APjAAAVbXOq/XjR77X2O+Ao947tjHP9dnaxmhOt4fcOSQMuPNrJ2juI6 BC6utZv4G6JkX5h+qSGmo1FCUxlW6/3dUw== X-Google-Smtp-Source: APXvYqyytLo0hQuO6sVxwOrnNs0IMG5xvWjRMfkyUlPHv/0jVyEk1u++gI1pakSzxaECVGMTFnJaFA== X-Received: by 2002:a7b:c632:: with SMTP id p18mr4219706wmk.73.1572959702668; Tue, 05 Nov 2019 05:15:02 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:02 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 2/7] pwm: sun4i: Add an optional probe for reset line Date: Tue, 5 Nov 2019 14:14:51 +0100 Message-Id: <20191105131456.32400-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Reviewed-by: Philipp Zabel Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6f5840a1a82d..9ba83769a478 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -365,6 +367,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "get reset failed %ld\n", + PTR_ERR(pwm->rst)); + return PTR_ERR(pwm->rst); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -377,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Tue Nov 5 13:14:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="czvQULze"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsM0Y72z9sPZ for ; Wed, 6 Nov 2019 00:15:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389070AbfKENPG (ORCPT ); Tue, 5 Nov 2019 08:15:06 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:52338 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388710AbfKENPG (ORCPT ); Tue, 5 Nov 2019 08:15:06 -0500 Received: by mail-wm1-f65.google.com with SMTP id c17so13507806wmk.2; Tue, 05 Nov 2019 05:15:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rylm49vbwAP0jTLqPJTMvxfUjjjnX0b1bndG2Prv3MM=; b=czvQULzeZnU/hHelxIDEbrHjoHdaiPYQD8gnbGsKhOEh19ZBw8jd8B0nls9dBjk0SH Tb6wvy6h9Nkzy5j/9X8SLNn166nTOTPmABsrBk0ocCLCrF+510qtKrT++c2NbY4RRtLo mNH5VaXaXyU5Yjdic9cvMEqDR4x8pUvL92nVY9+oGXcDYx9Du1LePiojZOnup3C5/LpZ s7yf7fp4OG0BqmTFjkJZ6UOrhb0LQ8W4KZ3GIiZQ5SWe8pHvaTP8aZh4ren+mwRLy2lb lRLVpRh92D7yC1H8DLTUShi6GLwke4L37aSDDeMQrxLwvdFhgXuefoaU/+5sYoP2znqG G05w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rylm49vbwAP0jTLqPJTMvxfUjjjnX0b1bndG2Prv3MM=; b=GZGL/k0fNb7zWzlJjcsN2F95B220PudK4uHpnwjw+YOfeabFZZY3C2eWCaAetaxBIW XaHWofBej+zu5cimFgmNipzqaqPNa6KQsXs8y/Gb1J6d8+i1/1ibyOWH2611coY3xCbo WaVUO2+8u2J2hkk18TcNT7I1wEH4kLkKXhUCfd16WhQfCfJ6YvJkziWKZOddytiQ1n7m yqjH2medrhUCIQCKK9WZljCM6/vu0iLi5JRJv8d5c8/KTRvgIfZeQLDxTA59ZGJxISQ4 sTd9G949wDpyF4kglRCkmurpsUHzIwaqela479aAB4wK6+mjcXmo1UHg+r+HJ2WuIdmr It5g== X-Gm-Message-State: APjAAAXQUAOd2Ea4HdGifF73Dh/24chmWZGsgATu6pQ8mK7byT43LODl ZxaiB5KUxDZbMbr25/MvisY= X-Google-Smtp-Source: APXvYqznbNCR4gLMX1epuZh7z03kgXnDOQWlHW6f0JH8v91E8iiEzK9mKwb3zm4PfWZeD9g5ak73aw== X-Received: by 2002:a1c:2706:: with SMTP id n6mr4432965wmn.154.1572959703335; Tue, 05 Nov 2019 05:15:03 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:02 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 3/7] pwm: sun4i: Add an optional probe for bus clock Date: Tue, 5 Nov 2019 14:14:52 +0100 Message-Id: <20191105131456.32400-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it and a fallback for previous bindings without name on module clock. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 45 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 9ba83769a478..54e19fa56a4e 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -363,9 +364,35 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->base)) return PTR_ERR(pwm->base); - pwm->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(pwm->clk)) + /* Get all clocks and reset line */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + dev_err(&pdev->dev, "get clock failed %ld\n", + PTR_ERR(pwm->clk)); return PTR_ERR(pwm->clk); + } + + /* + * Fallback for old dtbs with a single clock and no name. + * If a parent has a clock-name called "mod" whereas the + * current node is unnamed the clock reference will be + * incorrectly obtained and will not go into this fallback. + */ + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + dev_err(&pdev->dev, "get clock failed %ld\n", + PTR_ERR(pwm->clk)); + return PTR_ERR(pwm->clk); + } + } + + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + dev_err(&pdev->dev, "get bus_clock failed %ld\n", + PTR_ERR(pwm->bus_clk)); + return PTR_ERR(pwm->bus_clk); + } pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { @@ -382,6 +409,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* + * We're keeping the bus clock on for the sake of simplicity. + * Actually it only needs to be on for hardware register + * accesses. + */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -402,6 +440,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -416,6 +456,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Tue Nov 5 13:14:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="b82PUhZd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsM4xhdz9sPv for ; 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[82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:03 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 4/7] pwm: sun4i: Add support to output source clock directly Date: Tue, 5 Nov 2019 14:14:53 +0100 Message-Id: <20191105131456.32400-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 54e19fa56a4e..810abf47c261 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = state->period / 2; + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, clk_rate; + bool bypass; int ret; unsigned int delay_us; unsigned long now; @@ -218,6 +238,15 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, } } + /* + * Although it would make much more sense to check for bypass in + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". + */ + clk_rate = clk_get_rate(sun4i_pwm->clk); + bypass = state->enabled && + (state->period * clk_rate >= NSEC_PER_SEC) && + (state->duty_cycle * 2 == state->period); + spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); @@ -265,6 +294,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + else + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); + } + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Tue Nov 5 13:14:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fFmrMG6z"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsK1JRXz9sPZ for ; Wed, 6 Nov 2019 00:15:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389086AbfKENPH (ORCPT ); Tue, 5 Nov 2019 08:15:07 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:56312 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389058AbfKENPG (ORCPT ); Tue, 5 Nov 2019 08:15:06 -0500 Received: by mail-wm1-f68.google.com with SMTP id m17so11588830wmi.5; Tue, 05 Nov 2019 05:15:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Vnt9sMCBMLu8w8+z/tM0UPoRwgCIImfZjdha8S2Hvo=; b=fFmrMG6z+heryOiIoZe22e7Ay6QaIMDoQ0lyGyLwxhXc2kC2+1LNe9PDmqLmvWhL38 DImcPUDlCRtykfFdC7ZOrE4liyy2pa8B8Zs6gg/W2bPebCmf9hgzKKbScLOKbC/umovX ItceCkYzR5FHLb8XFoMdOb5kcUbARO0Wd04P9JPQ7JLTGeYg6H4VBWdYpA9m95DupPVn Dgt8QMRqQfADfjUxcZu+HjCw4zCl0aBRBeGIcKx1uJ/K6jSj7RayNOXCqFAy7U8SjsgE qmHffAidfGrypuhcF2qK0dut6UyFyrwDX6ekEBIH9pg0D/PLFSssRbtWvtHH7Juy2ROT ypIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Vnt9sMCBMLu8w8+z/tM0UPoRwgCIImfZjdha8S2Hvo=; b=KC30Ew2ux0Huoavj976/+UZ2KHMqK5vXTaYYksYduvUuxKDia2YXmu8//gg1L3IvxQ WbqbNob3aZjKnTS1chonYf2LLr7CTFuYONRuYnN3E3iBwvRQAUdxHYfTDCm+R53DDjMt zopjXdBgh08GmbJPtYMJmosvuqlze/bg++0Ik4pFUwwcrx0Iyt3uFZHNSbOkkmgOrtZY i/3r+Ml0UlVIg/6MMtFzFg0uoKBb/gVD69zHyXJItF6WxN8vMH7G6AWiNXxJuGY0K4HA rCKtTRRq3pu42mOAx3o4tTnt4P7krZGskzr6litmaZeVkbZ6ragYDBlnFhfHXAIoKMUb Dk2A== X-Gm-Message-State: APjAAAWrJKhq62jB7TohahhwPug0mDN0vXHbGMx//e39fIZocpGNB01l gvkRqefSk1AN9HkMVfX99kc= X-Google-Smtp-Source: APXvYqy7cIzX7d3Z3MnPrxaP5dgDyUpjHytLsGWwqekG/5Gcc7AIElqdEyNi7FWNrf9kuBGftMxF7A== X-Received: by 2002:a1c:453:: with SMTP id 80mr4274482wme.5.1572959704769; Tue, 05 Nov 2019 05:15:04 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:04 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 5/7] pwm: sun4i: Add support for H6 PWM Date: Tue, 5 Nov 2019 14:14:54 +0100 Message-Id: <20191105131456.32400-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 810abf47c261..e257c1b1fc67 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -359,6 +359,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -375,6 +381,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Tue Nov 5 13:14:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nE6YVB8/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsG4ZBvz9sPk for ; Wed, 6 Nov 2019 00:15:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389125AbfKENPN (ORCPT ); Tue, 5 Nov 2019 08:15:13 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35071 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389071AbfKENPH (ORCPT ); Tue, 5 Nov 2019 08:15:07 -0500 Received: by mail-wr1-f68.google.com with SMTP id l10so21313494wrb.2; Tue, 05 Nov 2019 05:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=nE6YVB8/dRlU2b3fHPmJ2QWHV0BQW340fAH+uA5LHsNv3jb6e/FKJTcJXzPlO7+ioU RNNPdn41M5dPxZMGxbnfPewuo/6zUyxgLQReHbeqBA6z2fIwxoVFagoab0i6Irbi4XDH Yc1LF0UfhEFlmoSKZNTZez+2H1Z7hE+bxkYwzTb6Rnzdev0pwqyN+nZYO2BjH+ZT8+iE g9WxNeAW4ZzQFVleSiSoL4eerfT36Zg6FA4T5dw6xQ+GKJ/pU/O4Uwd6AG99Mn1/zjGH 6uAhBmknvt0h5wga6lJaNgb3ea1y3gfv8a/tvkRGDj6V/8j+K9BV1sr4HwD/eAd9uUiY mfrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=HPwhbohCKefDo/5o9zz8SHQbCgJ8jYTMxSqcQYvIrTeBSFCN3IDVjwuLGUP9SkbR2t 3iDtc/SVjWdDtdrHmprMQwJoHe0XCQGMqbsUZjN0RCqhmWHsSPMFeuigWuAp/IRHuKZW CHSYVwzbnYc7eS7bBdWshw3vHntn3WSjDjx8l5JNvt26Ux0QusmwsamgI6b1jCFmNtAl 0cXl0qVT8jBrgd7NA1E6E2z1GYqHbuLfq5LEfI5grY/iBe0RrXOQ6TR++BfqW5tIH4Tw DQLUKeW8/NKgq5kDWMj2BMg46IMm0ZOIVN7ReqBSw/ef5qU+IB0W4rhRX14gOjUclo1g 2ILg== X-Gm-Message-State: APjAAAVx0+G3E9Fr6Gm7NjF+yLYLcWYstsl41RKJUGxCMxcfmvRcsQ7Z NRlTNgz0jL5n0wOAvj/WNws= X-Google-Smtp-Source: APXvYqwDhiEdJsPCcbhoaUwHdt2VPbYYzr78z9ZpGF4u1c+27BE7Axc5XPOsR2n+RkKWXf8PUlPbIA== X-Received: by 2002:a5d:404d:: with SMTP id w13mr29418841wrp.185.1572959705408; Tue, 05 Nov 2019 05:15:05 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:04 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v3 6/7] arm64: dts: allwinner: h6: Add PWM node Date: Tue, 5 Nov 2019 14:14:55 +0100 Message-Id: <20191105131456.32400-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 0d5ea19336a1..b0d9ee1ead13 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -222,6 +222,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Tue Nov 5 13:14:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1189689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WkHd/djk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476qsG0P38z9sPZ for ; Wed, 6 Nov 2019 00:15:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389106AbfKENPJ (ORCPT ); Tue, 5 Nov 2019 08:15:09 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:52351 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388710AbfKENPI (ORCPT ); Tue, 5 Nov 2019 08:15:08 -0500 Received: by mail-wm1-f68.google.com with SMTP id c17so13508018wmk.2; Tue, 05 Nov 2019 05:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aSxRdpuFtWHR4fiaYF0NucipXPgTqmHceHSDmByEc8=; b=WkHd/djk0ORgHMR2yAYNS+7CN1X0l1n8DgXtwwIvVzlhEHMkHD/NTxTZpWptYTlZoB RhCVfRsBADwmaNlswVb33scnynJbmb3xJwdaa2RmMSYOTJL/KvYY+fi6hEB+ZMpsriaJ fNircKP4McRAi3tzSUZPeKuw2GeN+pkjXNeR1+7THv8EFuyl5Fv4hvOoODBd36JgTVxl 8F4f6KkDHX+4xxxWx/BPKC753KJbfk/ObcxfGrjTf4OeQx4yMkSFMeRTLxHjuTXbBrnF gG8RzslXj+BvVVPL0ERWMv9W8lszVwUwJ1GZW7zgiJdhRdF6XLw8RIGlkZnBUs2G4UFn KSBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9aSxRdpuFtWHR4fiaYF0NucipXPgTqmHceHSDmByEc8=; b=ogm7D0KD9Vy4skTS95auU2C/gphlJT1I65AL7Zpi0t7tW2rzCKdbZg0ScHihDXEQP/ ztteisc3fUX2TilO2CT9mMNhjcmruTyK/5zBy0s5abHoIOzVpKCLAhygkciR0A7j9apd 41mX5kHtSEVxNTOL1Rznsue8VnAl/ZxLOAHo8cCMZwzs4bDiOq20dOb7XUjxLRLbP4uN Qy9XsQ5zRL5fHsK4kbcHaFOLnAgSFud8GmRBJNtb5Uy7dXJkHTxKJ6XwohFhvrqbEKG7 BDxUUZ4kUwuKAAntwdBjd3yuH9sZpKwZxBRbh8G5nFpZHbTKJd5McVk5Rx+NayxaYQqc abMA== X-Gm-Message-State: APjAAAX7mPQ7LYqe2I7B7v/IqeUFNxy5qCDU4zdguQf/blGQtRIuQhBV O6KCS9FZ0vzNcB3+5HanR+c= X-Google-Smtp-Source: APXvYqw6UFPNrurMZG2uJGWFoKHNaQqgij6b0hb605Rot6sbahLBVS34Xu72r3LgwNTT0W2EYgOUNg== X-Received: by 2002:a7b:c747:: with SMTP id w7mr4417876wmk.62.1572959706136; Tue, 05 Nov 2019 05:15:06 -0800 (PST) Received: from clement-Latitude-7490.outsight.local (lputeaux-656-1-11-33.w82-127.abo.wanadoo.fr. [82.127.142.33]) by smtp.gmail.com with ESMTPSA id a6sm13549920wmj.1.2019.11.05.05.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 05:15:05 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Philipp Zabel Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v3 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Tue, 5 Nov 2019 14:14:56 +0100 Message-Id: <20191105131456.32400-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191105131456.32400-1-peron.clem@gmail.com> References: <20191105131456.32400-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 1d05d570142f..38aba7e5bbd9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -131,6 +131,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";