From patchwork Wed Oct 30 22:42:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1187031 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="r3e8NuIr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 473Nlj2g7Mz9sPk for ; Thu, 31 Oct 2019 09:43:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727287AbfJ3WnF (ORCPT ); Wed, 30 Oct 2019 18:43:05 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:53741 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726765AbfJ3WnF (ORCPT ); Wed, 30 Oct 2019 18:43:05 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 41C4422EE3; Wed, 30 Oct 2019 23:43:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572475383; bh=LVpFkrvneLlxSnx5RW94rXimjPkbIlgIYaVp+0K1aq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r3e8NuIrMos30upFUridXoHzXwkLovyG8VyOa/KmBKF2LWijvK6RuRvB0KqLCG+6a vcPgZ6g+WEy8oICrrjGkmMWINbd+m4s6v5J46rbHHSJ77K9SltVyLuUdYGnLeVxZC7 yXkY1PcbguCCprKNVLM4TCxLKgGRRE14IVK6Tufc= From: Michael Walle To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Michael Walle Subject: [RFC PATCH 1/3] net: phy: at803x: fix Kconfig description Date: Wed, 30 Oct 2019 23:42:49 +0100 Message-Id: <20191030224251.21578-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191030224251.21578-1-michael@walle.cc> References: <20191030224251.21578-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The name of the PHY is actually AR803x not AT803x. Additionally, add the name of the vendor and mention the AR8031 support. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index fe602648b99f..38f180f9ca42 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -283,9 +283,9 @@ config AX88796B_PHY AX88796B package. config AT803X_PHY - tristate "AT803X PHYs" + tristate "Atheros AR803X PHYs" ---help--- - Currently supports the AT8030 and AT8035 model + Currently supports the AR8030, AR8031 and AR8035 model config BCM63XX_PHY tristate "Broadcom 63xx SOCs internal PHY" From patchwork Wed Oct 30 22:42:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1187026 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="eLeq02PK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 473NlQ2mBmz9sPn for ; Thu, 31 Oct 2019 09:43:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727478AbfJ3WnH (ORCPT ); Wed, 30 Oct 2019 18:43:07 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:52165 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727064AbfJ3WnG (ORCPT ); Wed, 30 Oct 2019 18:43:06 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 834D622EE4; Wed, 30 Oct 2019 23:43:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572475383; bh=2nqBdwy/goa8bNtLuPpQtky+yG6Rfoal/1lI2pumSNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eLeq02PKY8brujBPsziiI5NjHTblaCm4jqgLH0SoMxDX8AG2FjQVDFFE5qa1+Zp14 RYf2jCLTxz0qJlr5W87w+u2kdkh3VxuxzDyA+Fd3Dx2c8eNHfRZI793eko1MH3lLQf fe7ZWvmM91gYAuxn95UFQU8H58MNjkzds+DMfBoA= From: Michael Walle To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Michael Walle Subject: [RFC PATCH 2/3] dt-bindings: net: phy: Add support for AT803X Date: Wed, 30 Oct 2019 23:42:50 +0100 Message-Id: <20191030224251.21578-3-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191030224251.21578-1-michael@walle.cc> References: <20191030224251.21578-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document the Atheros AR803x PHY bindings. Signed-off-by: Michael Walle --- .../bindings/net/atheros,at803x.yaml | 58 +++++++++++++++++++ include/dt-bindings/net/atheros-at803x.h | 13 +++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/atheros,at803x.yaml create mode 100644 include/dt-bindings/net/atheros-at803x.h diff --git a/Documentation/devicetree/bindings/net/atheros,at803x.yaml b/Documentation/devicetree/bindings/net/atheros,at803x.yaml new file mode 100644 index 000000000000..60500fd90fd8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/atheros,at803x.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/atheros,at803x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atheros AR803x PHY + +maintainers: + - TBD + +description: | + Bindings for Atheros AR803x PHYs + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + atheros,clk-out-frequency: + description: Clock output frequency in Hertz. + enum: [ 25000000, 50000000, 62500000, 125000000 ] + + atheros,clk-out-strength: + description: Clock output driver strength. + enum: [ 0, 1, 2 ] + + atheros,keep-pll-enabled: + description: | + If set, keep the PLL enabled even if there is no link. Useful if you + want to use the clock output without an ethernet link. + type: boolean + + atheros,rgmii-io-1v8: + description: | + The PHY supports RGMII I/O voltages of 2.5V, 1.8V and 1.5V. By default, + the PHY uses a voltage of 1.5V. If this is set, the voltage will changed + to 1.8V. + The 2.5V voltage is only supported with an external supply voltage. + type: boolean + +examples: + - | + #include + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + phy-mode = "rgmii-id"; + + ethernet-phy@0 { + reg = <0>; + + atheros,clk-out-frequency = <125000000>; + atheros,clk-out-strength = ; + atheros,rgmii-io-1v8; + }; + }; diff --git a/include/dt-bindings/net/atheros-at803x.h b/include/dt-bindings/net/atheros-at803x.h new file mode 100644 index 000000000000..63b4fd10b2c6 --- /dev/null +++ b/include/dt-bindings/net/atheros-at803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_ATHEROS_AR803X_H +#define _DT_BINDINGS_ATHEROS_AR803X_H + +#define AT803X_STRENGTH_FULL 0 +#define AT803X_STRENGTH_HALF 1 +#define AT803X_STRENGTH_QUARTER 2 + +#endif From patchwork Wed Oct 30 22:42:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1187027 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="WQYCiXIq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 473NlT3yFFz9sPp for ; Thu, 31 Oct 2019 09:43:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727548AbfJ3WnN (ORCPT ); Wed, 30 Oct 2019 18:43:13 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:34885 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727106AbfJ3WnH (ORCPT ); Wed, 30 Oct 2019 18:43:07 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id BFD4822EE9; Wed, 30 Oct 2019 23:43:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572475383; bh=XFnpLVTbRIOcv1JIzgMCiJ0o/IuB8jUGvt9WomlOMmk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WQYCiXIqi++5FhEhgAeuFiPqNbek6Rkmh9YO82+pNsUhBv27AZv9oygpNLusWhej5 CYvnyfdZbU5uRmcIM6BZ2hDA/4lxIjqYgQkXA4CHYiJtVKY+UJ5Jt/kUeIslQuUZN3 I/BqZIfXqXkn3Pvvz4lLncWIMC17wX6JMU+C6slg= From: Michael Walle To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Michael Walle Subject: [RFC PATCH 3/3] net: phy: at803x: add device tree binding Date: Wed, 30 Oct 2019 23:42:51 +0100 Message-Id: <20191030224251.21578-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191030224251.21578-1-michael@walle.cc> References: <20191030224251.21578-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. Signed-off-by: Michael Walle Reviewed-by: Andrew Lunn --- drivers/net/phy/at803x.c | 156 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 1eb5d4fb8925..32be4c72cf4b 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #define AT803X_SPECIFIC_STATUS 0x11 #define AT803X_SS_SPEED_MASK (3 << 14) @@ -62,6 +64,37 @@ #define AT803X_DEBUG_REG_5 0x05 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) +#define AT803X_DEBUG_REG_1F 0x1F +#define AT803X_DEBUG_PLL_ON BIT(2) +#define AT803X_DEBUG_RGMII_1V8 BIT(3) + +/* AT803x supports either the XTAL input pad, an internal PLL or the + * DSP as clock reference for the clock output pad. The XTAL reference + * is only used for 25 MHz output, all other frequencies need the PLL. + * The DSP as a clock reference is used in synchronous ethernet + * applications. + * + * By default the PLL is only enabled if there is a link. Otherwise + * the PHY will go into low power state and disabled the PLL. You can + * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always + * enabled. + */ +#define AT803X_MMD7_CLK25M 0x8016 +#define AT803X_CLK_OUT_MASK GENMASK(4, 2) +#define AT803X_CLK_OUT_25MHZ_XTAL 0 +#define AT803X_CLK_OUT_25MHZ_DSP 1 +#define AT803X_CLK_OUT_50MHZ_PLL 2 +#define AT803X_CLK_OUT_50MHZ_DSP 3 +#define AT803X_CLK_OUT_62_5MHZ_PLL 4 +#define AT803X_CLK_OUT_62_5MHZ_DSP 5 +#define AT803X_CLK_OUT_125MHZ_PLL 6 +#define AT803X_CLK_OUT_125MHZ_DSP 7 + +#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) +#define AT803X_CLK_OUT_STRENGTH_FULL 0 +#define AT803X_CLK_OUT_STRENGTH_HALF 1 +#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 + #define ATH8030_PHY_ID 0x004dd076 #define ATH8031_PHY_ID 0x004dd074 #define ATH8035_PHY_ID 0x004dd072 @@ -73,6 +106,11 @@ MODULE_LICENSE("GPL"); struct at803x_priv { bool phy_reset:1; + int flags; +#define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ +#define AT803X_RGMII_1V8 BIT(1) /* use 1.8V RGMII voltage */ + u16 clk_25m_reg; + u16 clk_25m_mask; }; struct at803x_context { @@ -240,6 +278,74 @@ static int at803x_resume(struct phy_device *phydev) return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); } +static int at803x_parse_dt(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct at803x_priv *priv = phydev->priv; + u32 freq, strength; + unsigned int sel; + int ret; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + + if (!node) + return 0; + + if (of_property_read_bool(node, "atheros,keep-pll-enabled")) + priv->flags |= AT803X_KEEP_PLL_ENABLED; + + if (of_property_read_bool(node, "atheros,rgmii-io-1v8")) + priv->flags |= AT803X_RGMII_1V8; + + ret = of_property_read_u32(node, "atheros,clk-out-frequency", &freq); + if (!ret) { + switch (freq) { + case 25000000: + sel = AT803X_CLK_OUT_25MHZ_XTAL; + break; + case 50000000: + sel = AT803X_CLK_OUT_50MHZ_PLL; + break; + case 62500000: + sel = AT803X_CLK_OUT_62_5MHZ_PLL; + break; + case 125000000: + sel = AT803X_CLK_OUT_125MHZ_PLL; + break; + default: + phydev_err(phydev, + "invalid atheros,clk-out-frequency\n"); + return -EINVAL; + } + + priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); + priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; + } + + ret = of_property_read_u32(node, "atheros,clk-out-strength", &strength); + if (!ret) { + priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; + switch (strength) { + case AT803X_STRENGTH_FULL: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; + break; + case AT803X_STRENGTH_HALF: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; + break; + case AT803X_STRENGTH_QUARTER: + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; + break; + default: + phydev_err(phydev, + "invalid atheros,clk-out-strength\n"); + return -EINVAL; + } + } + + return 0; +} + static int at803x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -251,11 +357,31 @@ static int at803x_probe(struct phy_device *phydev) phydev->priv = priv; - return 0; + return at803x_parse_dt(phydev); +} + +static int at803x_clk_out_config(struct phy_device *phydev) +{ + struct at803x_priv *priv = phydev->priv; + int val; + + if (!priv->clk_25m_mask) + return 0; + + val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M); + if (val < 0) + return val; + + val &= ~priv->clk_25m_mask; + val |= priv->clk_25m_reg; + + return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val); } static int at803x_config_init(struct phy_device *phydev) { + struct at803x_priv *priv = phydev->priv; + u16 set = 0, clear = 0; int ret; /* The RX and TX delay default is: @@ -276,8 +402,34 @@ static int at803x_config_init(struct phy_device *phydev) ret = at803x_enable_tx_delay(phydev); else ret = at803x_disable_tx_delay(phydev); + if (ret < 0) + return ret; - return ret; + ret = at803x_clk_out_config(phydev); + if (ret < 0) + return ret; + + /* The default after hardware reset is: + * 1.5V RGMII I/O voltage + * PLL OFF (which means it is off if there is no link) + * + * After a soft reset, the values are retained. + */ + if (priv->flags & AT803X_KEEP_PLL_ENABLED) + set |= AT803X_DEBUG_PLL_ON; + else + clear |= AT803X_DEBUG_PLL_ON; + + if (priv->flags & AT803X_RGMII_1V8) + set |= AT803X_DEBUG_RGMII_1V8; + else + clear |= AT803X_DEBUG_RGMII_1V8; + + ret = at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, clear, set); + if (ret < 0) + return ret; + + return 0; } static int at803x_ack_interrupt(struct phy_device *phydev)