From patchwork Mon Oct 28 12:42:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anvesh Salveru X-Patchwork-Id: 1185369 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=samsung.com Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.b="IwNJ/hn2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 471vYm59mNz9sRV for ; Mon, 28 Oct 2019 23:44:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389233AbfJ1Mm6 (ORCPT ); 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Mon, 28 Oct 2019 12:42:51 +0000 (GMT) From: Anvesh Salveru To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Cc: pankaj.dubey@samsung.com, thierry.reding@gmail.com, jonathanh@nvidia.com, Anvesh Salveru , Lorenzo Pieralisi , Andrew Murray , Bjorn Helgaas , Vidya Sagar Subject: [PATCH 1/2] PCI: tegra: Remove support for ZRX-DC compliant PHY from platform driver Date: Mon, 28 Oct 2019 18:12:19 +0530 Message-Id: <1572266540-17626-2-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPIsWRmVeSWpSXmKPExsWy7bCmpq7fo22xBvtuq1g0/9/OanF210JW iyVNGRbzj5xjtWiZtYjF4vKuOWwWZ+cdZ7Po/DKLzeLN7xfsFou2fmG3+LlrHovFte28Djwe a+atYfTYOesuu8eCTaUevc3v2Dz6tqxi9Pi8SS6ALYrLJiU1J7MstUjfLoErY+7TFsaCddwV 9z5uZGpg/MzZxcjJISFgInGoaw1jFyMXh5DAbkaJpy8vM0M4nxgltl9cwAbhfGOU6Ow8wwbT 0vP8DFTLXkaJZyfPsEM4LUwSrw6dA6tiE9CW+Hl0LzuILSJQJjGr6QpYB7PAdCaJM5M3AhVx cAgLxEt0HpQEqWERUJVoWv4drJdXwEXi3VKQepBtchI3z3Uyg9icAq4S3VsfsYDMkRA4wiax vG8yM0SRi8Snj0uhbGGJV8e3sEPYUhIv+9ug7HyJ3rtLoewaiSl3O6AW2EscuDKHBeQeZgFN ifW79EHCzAJ8Er2/nzCBhCUEeCU62oQgTCWJtpnVEI0SEovn32SGCHtIXP+pDwmFGYwS7ZMO s01glJ2FMHMBI+MqRsnUguLc9NRi0wKjvNRyveLE3OLSvHS95PzcTYzgZKHltYNx2TmfQ4wC HIxKPLwTLm+LFWJNLCuuzD3EKMHBrCTCe/EMUIg3JbGyKrUoP76oNCe1+BCjNAeLkjjvJNar MUIC6YklqdmpqQWpRTBZJg5OqQbGkNrnjU3Hnr60euX3sY1bfu4UL0UhhU9pj85yFWzddKhK vCl6s8QVzliGvOA1u/4xip6OEGJcxX1yYUdKydaS+1ffz9ZYsjxwXv+DpccXKa/Wrvq8jr25 ZcflhV6CWyZ4u/Q79Cnu0fQJu6gbWvZc8RTnP1VGgz+f7pvn71O4o/i39KjAF8UtSizFGYmG WsxFxYkAcURQzBIDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPLMWRmVeSWpSXmKPExsWy7bCSvK7vo22xBmtPqlo0/9/OanF210JW iyVNGRbzj5xjtWiZtYjF4vKuOWwWZ+cdZ7Po/DKLzeLN7xfsFou2fmG3+LlrHovFte28Djwe a+atYfTYOesuu8eCTaUevc3v2Dz6tqxi9Pi8SS6ALYrLJiU1J7MstUjfLoErY+7TFsaCddwV 9z5uZGpg/MzZxcjJISFgItHz/AxjFyMXh5DAbkaJi9c+sUEkJCS+7P0KZQtLrPz3nB2iqIlJ YlHDd1aQBJuAtsTPo3vZQWwRgSqJAx19LCA2s8BcJonna1NAbGGBWIlDHXOZQWwWAVWJpuXf wYbyCrhIvFt6hRFigZzEzXOdYDWcAq4S3Vsfgc0RAqpp+vuKeQIj3wJGhlWMkqkFxbnpucWG BYZ5qeV6xYm5xaV56XrJ+bmbGMHBqqW5g/HykvhDjAIcjEo8vC+ubosVYk0sK67MPcQowcGs JMJ78QxQiDclsbIqtSg/vqg0J7X4EKM0B4uSOO/TvGORQgLpiSWp2ampBalFMFkmDk6pBsbp lzYmP+l3cGO4f6clLXNKLMveY5wbGSV8bpq3K8zNyJ33JmZ3xtx9y07vP2frVXj533nlI09X 8Uz5+S9Pb8a5x09cqgV8Y8Q0pl7vqH3881Zv4/Hdn9+rVqauW2n1iW/OzL2/DC5ECF7yV3q3 8x3nlC27z28rMnkxa//6nTvzuU9FnX/45sLBs0osxRmJhlrMRcWJAF8447dSAgAA X-CMS-MailID: 20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191028124253epcas5p3fd6b58e5ecd45bfd9c51dfdbd1a4ae40 References: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC specification are already handled based on "snps,phy-zrxdc-compliant" property in controller DT node. So, instead of handling ZRX-DC compliant settings in each platform driver, remove this driver specific code. CC: Lorenzo Pieralisi CC: Andrew Murray CC: Bjorn Helgaas CC: Vidya Sagar Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- Depends on the following patch: https://patchwork.kernel.org/patch/11215241/ https://patchwork.kernel.org/patch/11215239/ drivers/pci/controller/dwc/pcie-tegra194.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f89f5acee72d..f3a6ea89b8a8 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -782,10 +782,6 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) init_host_aspm(pcie); - val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - if (pcie->update_fc_fixup) { val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; From patchwork Mon Oct 28 12:42:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anvesh Salveru X-Patchwork-Id: 1185367 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=samsung.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 471vYY3B86z9sPK for ; Mon, 28 Oct 2019 23:44:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389553AbfJ1Mo1 (ORCPT ); Mon, 28 Oct 2019 08:44:27 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:55415 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389258AbfJ1MnD (ORCPT ); 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Mon, 28 Oct 2019 21:42:59 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5~R0B93U1UM3227132271epcas5p1W; Mon, 28 Oct 2019 12:42:58 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20191028124258epsmtrp14b635cca4841f1ace78daa7a9aabdf62~R0B92kGhc1231112311epsmtrp15; Mon, 28 Oct 2019 12:42:58 +0000 (GMT) X-AuditID: b6c32a4a-33fff7000001bcae-58-5db6e253847e Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 42.0A.24756.252E6BD5; Mon, 28 Oct 2019 21:42:58 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191028124256epsmtip2f768a74d043118782800f048892c4c13~R0B8Y8WqL1066510665epsmtip2r; Mon, 28 Oct 2019 12:42:56 +0000 (GMT) From: Anvesh Salveru To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Cc: pankaj.dubey@samsung.com, thierry.reding@gmail.com, jonathanh@nvidia.com, Anvesh Salveru , Rob Herring , Mark Rutland Subject: [PATCH 2/2] arm64: tegra: Add support for ZRX-DC phy property Date: Mon, 28 Oct 2019 18:12:20 +0530 Message-Id: <1572266540-17626-3-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFIsWRmVeSWpSXmKPExsWy7bCmhm7wo22xBl1XOCzO7lrIajH/yDlW i5ZZi1gsLu+aw2Zxdt5xNovOL7PYLJZev8hksWjrF3aL1r1H2C1+7prH4sDlsWbeGkaPnbPu sntsWtXJ5tHb/I7No2/LKkaPz5vkAtiiuGxSUnMyy1KL9O0SuDIO/drBWDBXsuLP/BeMDYw7 RboYOTkkBEwkvs58xNjFyMUhJLCbUaL7SRMzhPOJUeLa6x/sEM43RolnvxcwwbQ0LDvLBpHY yygx/eBvqKoWJokl1/8yglSxCWhL/Dy6lx3EFhEok5jVdAVsCbPAPkaJKTPOgSWEBdwkjve8 ZQWxWQRUJT70bWcDsXkFXCR2bb/LArFOTuLmuU5mEJtTwFWie+sjFpBBEgI72CT+959lhChy kVj88jUrhC0s8er4FnYIW0riZX8blJ0v0Xt3KZRdIzHlbgdUr73EgStzgIZyAF2nKbF+lz5I mFmAT6L39xMmkLCEAK9ER5sQhKkk0TazGqJRQmLx/JvMELaHROufTdBwmMEo0fXmKvMERtlZ CEMXMDKuYpRMLSjOTU8tNi0wykst1ytOzC0uzUvXS87P3cQIThFaXjsYl53zOcQowMGoxMM7 4fK2WCHWxLLiytxDjBIczEoivBfPAIV4UxIrq1KL8uOLSnNSiw8xSnOwKInzTmK9GiMkkJ5Y kpqdmlqQWgSTZeLglGpgVHx68OrGR5EiynccGJSDyl8Y/i64lKU90c3qn4xYusO3+3ccBWa/ Cl53oqY16PK8X1kXz4vmPGqJrfWYy3c9Vu7uwYW5wYHLsj+y+ljOKv259vae4AAGm23Sv/Mu 7Axx33et+vHVF5N2nty6YPFLfi/fLatMF2S2+Wds6ZAKycx7kxZu8dhHXImlOCPRUIu5qDgR AD7CnfYNAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJLMWRmVeSWpSXmKPExsWy7bCSvG7Qo22xBnf/iluc3bWQ1WL+kXOs Fi2zFrFYXN41h83i7LzjbBadX2axWSy9fpHJYtHWL+wWrXuPsFv83DWPxYHLY828NYweO2fd ZffYtKqTzaO3+R2bR9+WVYwenzfJBbBFcdmkpOZklqUW6dslcGUc+rWDsWCuZMWf+S8YGxh3 inQxcnJICJhINCw7y9bFyMUhJLCbUWLLrzMsEAkJiS97v7JB2MISK/89Z4coamKSWPN6HStI gk1AW+Ln0b3sILaIQJXEgY4+FpAiZoEjjBI/br0A6xYWcJM43vMWrIFFQFXiQ992sDivgIvE ru13obbJSdw818kMYnMKuEp0b30EFhcCqmn6+4p5AiPfAkaGVYySqQXFuem5xYYFhnmp5XrF ibnFpXnpesn5uZsYwQGqpbmD8fKS+EOMAhyMSjy8L65uixViTSwrrsw9xCjBwawkwnvxDFCI NyWxsiq1KD++qDQntfgQozQHi5I479O8Y5FCAumJJanZqakFqUUwWSYOTqkGxvaU/g3Rf6Xt Gy7tStB7ezp3zuQ7YVKvrpc/XLD0ZefXuIPuqcJr/HU0mE//6H787/V+J41DPZ8OlT8s8/58 SHyb0g6niZ7veO3/S8lObS/4fflMwrfL5ZYbNzQZSMuKCdyeecGn29p1l39/yFPVN76XWdyl +sq8FQ9xlbyZosG93udKziMWKyWW4oxEQy3mouJEANVhKEpMAgAA X-CMS-MailID: 20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5 References: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant" DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie controller DT nodes. CC: Rob Herring CC: Mark Rutland Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- Depends on the following patch: https://patchwork.kernel.org/patch/11215241/ https://patchwork.kernel.org/patch/11215239/ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3c0cf54f0aab..bf2dbf84c8c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1194,6 +1194,7 @@ ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14120000 { @@ -1240,6 +1241,7 @@ ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14140000 { @@ -1286,6 +1288,7 @@ ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14160000 { @@ -1332,6 +1335,7 @@ ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@14180000 { @@ -1378,6 +1382,7 @@ ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@141a0000 { @@ -1428,6 +1433,7 @@ ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; sysram@40000000 {