From patchwork Wed Oct 23 09:39:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1181977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-511557-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="A59qmgTB"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46ylhW2h2mz9sPV for ; Wed, 23 Oct 2019 20:39:37 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:references:date:mime-version:in-reply-to :content-type:message-id; q=dns; s=default; b=Uu01/0xpbo7HMMlXRJ MGKRsaIoAb2fQCtKYPevz/4KFqotg8kT8ITWimEXc1GT+2SeAVtvSrprcqUqMpWl MbWpcqS9CB3SbBZesVHnkRiyxQzOjnTufVJ42pfSAXSRzHXb6YjNRlmpAcT1Szr3 kYbyYNc/m0gUFpReuXttOV8kE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:references:date:mime-version:in-reply-to :content-type:message-id; s=default; bh=Em6RqKG9kcyqw9BgJ7734Ol9 Qm0=; b=A59qmgTB44xWkWTHqzBpa63hgSTjrbtbnKj1v3XDA6QECWoSEeLNrXN5 I6/xWE7yV1BWuJ9oiKULa7wfrMWpwDsKtdP/6RzK6nBUs3+JWSJF2ZZXx+VcZoxN TLj0rrNzd98wwofAw6TVjdXSqze2amynPVmCLuYopc9vhMOqNgE= Received: (qmail 21867 invoked by alias); 23 Oct 2019 09:39:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21855 invoked by uid 89); 23 Oct 2019 09:39:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy=3017, H*f:sk:172addb, H*i:sk:172addb X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Oct 2019 09:39:28 +0000 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9N9b7io006276 for ; Wed, 23 Oct 2019 05:39:26 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vth0qxpse-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 05:39:25 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 10:39:18 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9N9dGYG26935364 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 09:39:16 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6505111C052; Wed, 23 Oct 2019 09:39:16 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5938E11C050; Wed, 23 Oct 2019 09:39:15 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.149]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 09:39:15 +0000 (GMT) Subject: [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Date: Wed, 23 Oct 2019 17:39:14 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> x-cbid: 19102309-0012-0000-0000-0000035BFF1D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102309-0013-0000-0000-000021972D0D Message-Id: <8c4cac65-7faf-74ec-e008-56ccfdf6e8ca@linux.ibm.com> X-IsSubscribed: yes Hi, I noticed that vsx_xvcdpsp and vsx_xvcvdpsp are almost the same, and vsx_xvcdpsp looks replaceable with vsx_xvcvdpsp since it's only called by gen_*. Bootstrapped and regress tested on powerpc64le-linux-gnu. gcc/ChangeLog 2019-10-23 Kewen Lin * config/rs6000/vsx.md (vsx_xvcdpsp): Remove define_insn. (UNSPEC_VSX_XVCDPSP): Remove. * config/rs6000/rs6000.c (rs6000_generate_float2_double_code): Replace gen_vsx_xvcdpsp by gen_vsx_xvcvdpsp. From 8c6309c131b7614ed8d6aeb4ca2d3d89ab0b8d38 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Tue, 8 Oct 2019 01:51:06 -0500 Subject: [PATCH 1/3] Replace vsx_xvcdpsp by vsx_xvcvdpsp --- gcc/config/rs6000/rs6000.c | 4 ++-- gcc/config/rs6000/vsx.md | 9 --------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c2834bd..23898b1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -25549,8 +25549,8 @@ rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2) rtx_tmp2 = gen_reg_rtx (V4SFmode); rtx_tmp3 = gen_reg_rtx (V4SFmode); - emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0)); - emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1)); + emit_insn (gen_vsx_xvcvdpsp (rtx_tmp2, rtx_tmp0)); + emit_insn (gen_vsx_xvcvdpsp (rtx_tmp3, rtx_tmp1)); if (BYTES_BIG_ENDIAN) emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3)); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f54d343..d6f079c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -301,7 +301,6 @@ UNSPEC_VSX_XVCVSXDDP UNSPEC_VSX_XVCVUXDDP UNSPEC_VSX_XVCVDPSXDS - UNSPEC_VSX_XVCDPSP UNSPEC_VSX_XVCVDPUXDS UNSPEC_VSX_SIGN_EXTEND UNSPEC_VSX_XVCVSPSXWS @@ -2367,14 +2366,6 @@ "xvcvuxdsp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcdpsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCDPSP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpsp %x0,%x1" - [(set_attr "type" "vecdouble")]) - ;; Convert from 32-bit to 64-bit types ;; Provide both vector and scalar targets (define_insn "vsx_xvcvsxwdp" From patchwork Wed Oct 23 09:40:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1181978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-511558-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="IdmKZk6N"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46yljz0zdKz9sPV for ; Wed, 23 Oct 2019 20:40:54 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:references:date:mime-version:in-reply-to :content-type:message-id; q=dns; s=default; b=VkkHa8Do6BZ/K0h4nA un0pps+CVOtm+UbM2PKWi5HnOTQnhsUHsASzWw8dojbjRgyqhuIhDY1JPGR9Pu+t +DGKCqn6oTGUaeyhrglgM/xEpl7VVmaBkjFfZmGNglSz2lYzkP4dWzGz3mkjXdZl 86z3XT5Zcp5HVvWpAhW5UkQXI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:references:date:mime-version:in-reply-to :content-type:message-id; s=default; bh=mnnALQY1uLhIb2AWOLzlTAtC 9pg=; b=IdmKZk6NewxfTN1qbgeqiZ+6fSbKNiPE3BFGoQUHNvL195wKKhUIDft5 Va1CjuWPTreCJVWKZsxZsEoDS/TktHU37PRou4cfqvWxeJKWQMZPHQrXJhgF595h xaVEicptXFAtOTZVoaAYaFqrNRGqEFRJC2zdXfcNJcxfmiiWipU= Received: (qmail 24380 invoked by alias); 23 Oct 2019 09:40:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 24372 invoked by uid 89); 23 Oct 2019 09:40:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Oct 2019 09:40:46 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9N9b21o034488 for ; Wed, 23 Oct 2019 05:40:44 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vtk21k6s9-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 05:40:44 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 10:40:39 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9N9ecUw58458344 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 09:40:38 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07E6811C050; Wed, 23 Oct 2019 09:40:38 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9AC6F11C052; Wed, 23 Oct 2019 09:40:36 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.149]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 09:40:36 +0000 (GMT) Subject: [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Date: Wed, 23 Oct 2019 17:40:35 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> x-cbid: 19102309-0012-0000-0000-0000035BFF35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102309-0013-0000-0000-000021972D28 Message-Id: X-IsSubscribed: yes Hi, For those fixed point <-> floating point vector conversion with same element unit size, such as: SP <-> SI, DP <-> DI, it's fine to use the existing RTL operations like any_fix/any_float for them. This patch is to update them with any_fix/any_float. Bootstrapped and regress tested on powerpc64le-linux-gnu. gcc/ChangeLog 2019-10-23 Kewen Lin * config/rs6000/vsx.md (UNSPEC_VSX_CV[SU]XWSP, UNSPEC_VSX_XVCV[SU]XDDP, UNSPEC_VSX_XVCVDP[SU]XDS, UNSPEC_VSX_XVCVSPSXWS): Remove. (vsx_xvcv[su]xddp, vsx_xvcvdp[su]xds, vsx_xvcvsp[su]xws, vsx_xvcv[su]xwsp): Update define_insn RTL patterns. From 39ae875d4ae6ce22e170aeb456ef307a1f5fd1e0 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 23 Oct 2019 02:56:48 -0500 Subject: [PATCH 2/3] Update RTL pattern on vector SP<->[SU]W DP<->[SU]D conversion --- gcc/config/rs6000/vsx.md | 105 +++++++++++++---------------------------------- 1 file changed, 28 insertions(+), 77 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d6f079c..83e4071 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -277,8 +277,6 @@ UNSPEC_VSX_CVUXDSP UNSPEC_VSX_CVSPSXDS UNSPEC_VSX_CVSPUXDS - UNSPEC_VSX_CVSXWSP - UNSPEC_VSX_CVUXWSP UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -298,12 +296,7 @@ UNSPEC_VSX_DIVSD UNSPEC_VSX_DIVUD UNSPEC_VSX_MULSD - UNSPEC_VSX_XVCVSXDDP - UNSPEC_VSX_XVCVUXDDP - UNSPEC_VSX_XVCVDPSXDS - UNSPEC_VSX_XVCVDPUXDS UNSPEC_VSX_SIGN_EXTEND - UNSPEC_VSX_XVCVSPSXWS UNSPEC_VSX_XVCVSPSXDS UNSPEC_VSX_VSLO UNSPEC_VSX_EXTRACT @@ -2202,6 +2195,34 @@ ;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) +(define_insn "vsx_xvcvxwsp" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (any_float:V4SF (match_operand:V4SI 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvxwsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_insn "vsx_xvcvxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF (match_operand:V2DI 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspxws" + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") + (any_fix:V4SI (match_operand:V4SF 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvspxws %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_insn "vsx_xvcvdpxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (any_fix:V2DI (match_operand:V2DF 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + (define_expand "vsx_xvcvsxddp_scale" [(match_operand:V2DF 0 "vsx_register_operand") (match_operand:V2DI 1 "vsx_register_operand") @@ -2217,14 +2238,6 @@ DONE; }) -(define_insn "vsx_xvcvsxddp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSXDDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxddp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_expand "vsx_xvcvuxddp_scale" [(match_operand:V2DF 0 "vsx_register_operand") (match_operand:V2DI 1 "vsx_register_operand") @@ -2240,14 +2253,6 @@ DONE; }) -(define_insn "vsx_xvcvuxddp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVUXDDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxddp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_expand "vsx_xvcvdpsxds_scale" [(match_operand:V2DI 0 "vsx_register_operand") (match_operand:V2DF 1 "vsx_register_operand") @@ -2270,26 +2275,6 @@ }) ;; convert vector of 64-bit floating point numbers to vector of -;; 64-bit signed integer -(define_insn "vsx_xvcvdpsxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") - (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVDPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpsxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - -;; convert vector of 32-bit floating point numbers to vector of -;; 32-bit signed integer -(define_insn "vsx_xvcvspsxws" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") - (unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSPSXWS))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvspsxws %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; convert vector of 64-bit floating point numbers to vector of ;; 64-bit unsigned integer (define_expand "vsx_xvcvdpuxds_scale" [(match_operand:V2DI 0 "vsx_register_operand") @@ -2312,24 +2297,6 @@ DONE; }) -;; convert vector of 32-bit floating point numbers to vector of -;; 32-bit unsigned integer -(define_insn "vsx_xvcvspuxws" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") - (unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSPSXWS))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvspuxws %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "vsx_xvcvdpuxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") - (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVDPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpuxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. @@ -2416,22 +2383,6 @@ "xvcvspuxds %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvsxwsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWSP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvsxwsp %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "vsx_xvcvuxwsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWSP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvuxwsp %x0,%x1" - [(set_attr "type" "vecfloat")]) - ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df" From patchwork Wed Oct 23 09:42:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1181979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 10:42:50 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9N9gG4229032882 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 09:42:16 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9A30811C04A; Wed, 23 Oct 2019 09:42:48 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2028E11C050; Wed, 23 Oct 2019 09:42:47 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.149]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 09:42:46 +0000 (GMT) Subject: [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff unit size From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Date: Wed, 23 Oct 2019 17:42:45 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> x-cbid: 19102309-0020-0000-0000-0000037D0250 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102309-0021-0000-0000-000021D342FE Message-Id: <22fd6de1-dc31-a977-a803-0a2cb3f11444@linux.ibm.com> X-IsSubscribed: yes Hi, Following the previous one 2/3, this patch is to update the vector conversions between fixed point and floating point with different element unit sizes, such as: SP <-> DI, DP <-> SI. Bootstrap and regression testing just launched. gcc/ChangeLog 2019-10-23 Kewen Lin * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes. * config/rs6000/vsx.md (UNSPEC_VSX_CVDPSXWS, UNSPEC_VSX_CVSXDSP, UNSPEC_VSX_CVUXDSP, UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove. (vsx_xvcvspdp): New define_expand, old one split to... (vsx_xvcvspdp_be): ... this. New. And... (vsx_xvcvspdp_le): ... this. New. (vsx_xvcvdpsp): New define_expand, old one split to... (vsx_xvcvdpsp_be): ... this. New. And... (vsx_xvcvdpsp_le): ... this. New. (vsx_xvcvdp[su]xws): New define_expand, old one split to... (vsx_xvcvdpxws_be): ... this. New. And... (vsx_xvcvdpxws_le): ... this. New. (vsx_xvcv[su]xdsp): New define_expand, old one split to... (vsx_xvcvxdsp_be): ... this. New. And... (vsx_xvcvxdsp_le): ... this. New. (vsx_xvcv[su]xwdp): New define_expand, old one split to... (vsx_xvcvxwdp_be): ... this. New. And... (vsx_xvcvxwdp_le): ... this. New. (vsx_xvcvsp[su]xds): New define_expand, old one split to... (vsx_xvcvspxds_be): ... this. New. And... (vsx_xvcvspxds_le): ... this. New. From 5315810c391b75661de9027ea2848d31390e1d8b Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 23 Oct 2019 04:02:00 -0500 Subject: [PATCH 3/3] Update RTL pattern on vector fp/int 32bit <-> 64bit conversion --- gcc/config/rs6000/rs6000-modes.def | 4 + gcc/config/rs6000/vsx.md | 240 +++++++++++++++++++++++++++---------- 2 files changed, 181 insertions(+), 63 deletions(-) diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 677062c..449e176 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +/* Half VMX/VSX vector (for select) */ +VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ +VECTOR_MODE (INT, SI, 2); /* V2SI */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 83e4071..44025f6 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -265,7 +265,6 @@ ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT - UNSPEC_VSX_CVDPSXWS UNSPEC_VSX_CVDPUXWS UNSPEC_VSX_CVSPDP UNSPEC_VSX_CVHPSP @@ -273,10 +272,6 @@ UNSPEC_VSX_CVDPSPN UNSPEC_VSX_CVSXWDP UNSPEC_VSX_CVUXWDP - UNSPEC_VSX_CVSXDSP - UNSPEC_VSX_CVUXDSP - UNSPEC_VSX_CVSPSXDS - UNSPEC_VSX_CVSPUXDS UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -2106,22 +2101,69 @@ "xscvdpsp %x0,%x1" [(set_attr "type" "fp")]) -(define_insn "vsx_xvcvspdp" +(define_insn "vsx_xvcvspdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvspdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" "xvcvspdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvdpsp" +(define_expand "vsx_xvcvspdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1])); + DONE; +}) + +(define_insn "vsx_xvcvdpsp_be" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") - (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" + (float_truncate:V4SF + (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa") + (vec_select:V2DF (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" "xvcvdpsp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_insn "vsx_xvcvdpsp_le" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") + (float_truncate:V4SF + (vec_concat:V4DF + (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvdpsp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpsp" + [(match_operand:V4SF 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvdpsp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvdpsp_le (operands[0], operands[1])); + DONE; +}) + ;; xscvspdp, represent the scalar SF type as V4SF (define_insn "vsx_xscvspdp" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") @@ -2301,48 +2343,144 @@ ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. -(define_insn "vsx_xvcvdpsxws" +;; Convert vector of 64-bit floating point numbers to vector of +;; 32-bit signed/unsigned integers. +(define_insn "vsx_xvcvdpxws_be" [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa") - (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVDPSXWS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpsxws %x0,%x1" + (any_fix:V4SI + (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa") + (vec_select:V2DF (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvdpxws %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvdpuxws" +(define_insn "vsx_xvcvdpxws_le" [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa") - (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVDPUXWS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpuxws %x0,%x1" + (any_fix:V4SI + (vec_concat:V4DF + (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvdpxws %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvsxdsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXDSP))] +(define_expand "vsx_xvcvdpxws" + [(match_operand:V4SI 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand") + (any_fix (pc))] "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxdsp %x0,%x1" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvdpxws_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvdpxws_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 64-bit signed/unsigned integers to vector of +;; 32-bit floating point numbers. +(define_insn "vsx_xvcvxdsp_be" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (any_float:V4SF + (vec_concat:V4DI (match_operand:V2DI 1 "vsx_register_operand" "wa") + (vec_select:V2DI (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvxdsp %x0,%x1" [(set_attr "type" "vecfloat")]) -(define_insn "vsx_xvcvuxdsp" +(define_insn "vsx_xvcvxdsp_le" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXDSP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxdsp %x0,%x1" + (any_float:V4SF + (vec_concat:V4DI + (vec_select:V2DI (match_operand:V2DI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" + "xvcvxdsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_expand "vsx_xvcvxdsp" + [(match_operand:V4SF 0 "vsx_register_operand") + (match_operand:V2DI 1 "vsx_register_operand") + (any_float (pc))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxdsp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxdsp_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 32-bit signed/unsigned integers to vector of +;; 64-bit floating point numbers. +(define_insn "vsx_xvcvxwdp_be" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -;; Convert from 32-bit to 64-bit types -;; Provide both vector and scalar targets -(define_insn "vsx_xvcvsxwdp" +(define_insn "vsx_xvcvxwdp_le" [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWDP))] + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvxwdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SI 1 "vsx_register_operand") + (any_float (pc))] "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxwdp %x0,%x1" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxwdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxwdp_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 32-bit floating point numbers to vector of +;; 64-bit signed/unsigned integers. +(define_insn "vsx_xvcvspxds_be" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspxds_le" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspxds" + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand") + (any_fix (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspxds_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspxds_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvsxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2351,14 +2489,6 @@ "xvcvsxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvuxwdp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxwdp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_insn "vsx_xvcvuxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2367,22 +2497,6 @@ "xvcvuxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspsxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspsxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - -(define_insn "vsx_xvcvspuxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspuxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df"