From patchwork Wed Nov 15 12:56:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 838175 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ycPq94Lm0z9s82 for ; Thu, 16 Nov 2017 00:09:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932481AbdKONJj (ORCPT ); Wed, 15 Nov 2017 08:09:39 -0500 Received: from esa4.microchip.iphmx.com ([68.232.154.123]:32372 "EHLO esa4.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932498AbdKONIx (ORCPT ); Wed, 15 Nov 2017 08:08:53 -0500 X-IronPort-AV: E=Sophos;i="5.43,434,1503385200"; d="scan'208";a="8624123" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 15 Nov 2017 06:08:53 -0700 Received: from eh-station.mchp-main.com (10.10.76.4) by chn-sv-exch07.mchp-main.com (10.10.76.108) with Microsoft SMTP Server id 14.3.352.0; Wed, 15 Nov 2017 06:08:52 -0700 From: Eugen Hristev To: , , , , , , , , CC: Subject: [PATCH v3 1/4] dt-bindings: iio: at91-sama5d2_adc: add optional dma property Date: Wed, 15 Nov 2017 14:56:45 +0200 Message-ID: <1510750608-8697-2-git-send-email-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510750608-8697-1-git-send-email-eugen.hristev@microchip.com> References: <1510750608-8697-1-git-send-email-eugen.hristev@microchip.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Added property for DMA configuration of the device. Signed-off-by: Eugen Hristev Acked-by: Rob Herring --- Changes in v3: None, but we discussed on the ML about whether we should have "dma-names" present in the binding even if it's only one. The helpers in the kernel to retrieve the channel info rely on the presence of this property, so I am resending the patch based on this. If another solution is better, please advise and I can try it and resend the patch. Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt index 552e7a8..6469a4c 100644 --- a/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt @@ -17,6 +17,11 @@ Required properties: This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING , IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH +Optional properties: + - dmas: Phandle to dma channel for the ADC. + - dma-names: Must be "rx" when dmas property is being used. + See ../../dma/dma.txt for details. + Example: adc: adc@fc030000 { @@ -31,4 +36,6 @@ adc: adc@fc030000 { vddana-supply = <&vdd_3v3_lp_reg>; vref-supply = <&vdd_3v3_lp_reg>; atmel,trigger-edge-type = ; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; + dma-names = "rx"; }