From patchwork Wed Nov 15 11:51:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 838140 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466850-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="NFzj2GOw"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ycN4R2JC0z9sBZ for ; Wed, 15 Nov 2017 22:50:59 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=PWmLwZjUo/n4yTjkB3I093ZaOiHoI3siWRBQzc9zc44Zo7tRtf EpWCKEeb3UqDYUXDkODybF3B1glkC31L+0SGLMtyP7R8BwUcSqGRKiwGMorEtfRV uDS/NJDSDoWieLDNb4v/5KQX4f0wAJqkoqfTCZIvzgz5QhTQqL6AxcgNE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=9VtaOUVfx0gkwkCaGybi0lNhkeU=; b=NFzj2GOwJTW/5GHfLbH+ xKFFvH+6q/8n0A4ZrbGyxHUmJap5Bh9ehEPBrQPh7athuw/1sD4JqV0mlcVBqxJi ep6FFeMgRWzwyYU3CEQWxd7nK7EReMhB9LBI02QQTPM4JYz7syIcp4AvxnMFHK9Z POJ3rhONOBOE4e4Q5CfRRKU= Received: (qmail 100683 invoked by alias); 15 Nov 2017 11:50:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 100665 invoked by uid 89); 15 Nov 2017 11:50:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0071.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.71) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Nov 2017 11:50:47 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Tamar.Christina@arm.com; Received: from arm.com (217.140.96.140) by VI1PR08MB0511.eurprd08.prod.outlook.com (2a01:111:e400:5831::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.197.13; Wed, 15 Nov 2017 11:50:43 +0000 Date: Wed, 15 Nov 2017 11:51:15 +0000 From: Tamar Christina To: gcc-patches@gcc.gnu.org Cc: nd@arm.com, james.greenhalgh@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com Subject: [PATCH][GCC][DOCS][AArch64][ARM] Documentation updates adding -A extensions. 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Build done on aarch64-none-elf and arm-none-eabi and no issues. Ok for trunk? Thanks, Tamar gcc/ 2017-11-15 Tamar Christina * doc/extend.texi: Add -A suffix (ARMv8*-A, ARMv7-A). * doc/invoke.texi: Add -A suffix (ARMv8*-A, ARMv7-A). * doc/sourcebuild.texi: Add -A suffix (ARMv8*-A, ARMv7-A). diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 63b58c0681e856da7ecc8c57c5d2f43613389a1d..a7a1ffcb852749b4e39facb434b2feda3534e77b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -1045,7 +1045,7 @@ expressions are automatically promoted to @code{float}. The ARM target provides hardware support for conversions between @code{__fp16} and @code{float} values -as an extension to VFP and NEON (Advanced SIMD), and from ARMv8 provides +as an extension to VFP and NEON (Advanced SIMD), and from ARMv8-A provides hardware support for conversions between @code{__fp16} and @code{double} values. GCC generates code using these hardware instructions if you compile with options to select an FPU that provides them; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e897d93070ae320f741aeba4d2490f8366843935..b2f044cf5fb75c44a180b2231284882728248952 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15504,8 +15504,8 @@ entirely disabled by the @samp{+nofp} option that follows it. Most extension names are generically named, but have an effect that is dependent upon the architecture to which it is applied. For example, the @samp{+simd} option can be applied to both @samp{armv7-a} and -@samp{armv8-a} architectures, but will enable the original ARMv7 -Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-a +@samp{armv8-a} architectures, but will enable the original ARMv7-A +Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-A variant for @samp{armv8-a}. The table below lists the supported extensions for each architecture. @@ -15646,7 +15646,7 @@ Disable the floating-point and Advanced SIMD instructions. @item +crc The Cyclic Redundancy Check (CRC) instructions. @item +simd -The ARMv8 Advanced SIMD and floating-point instructions. +The ARMv8-A Advanced SIMD and floating-point instructions. @item +crypto The cryptographic instructions. @item +nocrypto @@ -15658,7 +15658,7 @@ Disable the floating-point, Advanced SIMD and cryptographic instructions. @item armv8.1-a @table @samp @item +simd -The ARMv8.1 Advanced SIMD and floating-point instructions. +The ARMv8.1-A Advanced SIMD and floating-point instructions. @item +crypto The cryptographic instructions. This also enables the Advanced SIMD and @@ -15678,7 +15678,7 @@ The half-precision floating-point data processing instructions. This also enables the Advanced SIMD and floating-point instructions. @item +simd -The ARMv8.1 Advanced SIMD and floating-point instructions. +The ARMv8.1-A Advanced SIMD and floating-point instructions. @item +crypto The cryptographic instructions. This also enables the Advanced SIMD and @@ -15754,7 +15754,7 @@ The Cyclic Redundancy Check (CRC) instructions. @item +fp.sp The single-precision FPv5 floating-point instructions. @item +simd -The ARMv8 Advanced SIMD and floating-point instructions. +The ARMv8-A Advanced SIMD and floating-point instructions. @item +crypto The cryptographic instructions. @item +nocrypto @@ -16173,9 +16173,9 @@ Divided syntax should be considered deprecated. @item -mrestrict-it @opindex mrestrict-it -Restricts generation of IT blocks to conform to the rules of ARMv8. +Restricts generation of IT blocks to conform to the rules of ARMv8-A. IT blocks can only contain a single 16-bit instruction from a select -set of instructions. This option is on by default for ARMv8 Thumb mode. +set of instructions. This option is on by default for ARMv8-A Thumb mode. @item -mprint-tune-info @opindex mprint-tune-info diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index d5a90e518d67fb289c8caf2e8f2237970b6649ea..9bb14da1a6f6ec76de72a0927a17909c4d2f0ad5 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1714,11 +1714,11 @@ Some multilibs may be incompatible with these options. @item arm_v8_1a_neon_ok @anchor{arm_v8_1a_neon_ok} -ARM target supports options to generate ARMv8.1 Adv.SIMD instructions. +ARM target supports options to generate ARMv8.1-A Adv.SIMD instructions. Some multilibs may be incompatible with these options. @item arm_v8_1a_neon_hw -ARM target supports executing ARMv8.1 Adv.SIMD instructions. Some +ARM target supports executing ARMv8.1-A Adv.SIMD instructions. Some multilibs may be incompatible with the options needed. Implies arm_v8_1a_neon_ok. @@ -1727,34 +1727,34 @@ ARM target supports acquire-release instructions. @item arm_v8_2a_fp16_scalar_ok @anchor{arm_v8_2a_fp16_scalar_ok} -ARM target supports options to generate instructions for ARMv8.2 and +ARM target supports options to generate instructions for ARMv8.2-A and scalar instructions from the FP16 extension. Some multilibs may be incompatible with these options. @item arm_v8_2a_fp16_scalar_hw -ARM target supports executing instructions for ARMv8.2 and scalar +ARM target supports executing instructions for ARMv8.2-A and scalar instructions from the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_neon_ok. @item arm_v8_2a_fp16_neon_ok @anchor{arm_v8_2a_fp16_neon_ok} -ARM target supports options to generate instructions from ARMv8.2 with +ARM target supports options to generate instructions from ARMv8.2-A with the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_scalar_ok. @item arm_v8_2a_fp16_neon_hw -ARM target supports executing instructions from ARMv8.2 with the FP16 +ARM target supports executing instructions from ARMv8.2-A with the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw. @item arm_v8_2a_dotprod_neon_ok @anchor{arm_v8_2a_dotprod_neon_ok} -ARM target supports options to generate instructions from ARMv8.2 with +ARM target supports options to generate instructions from ARMv8.2-A with the Dot Product extension. Some multilibs may be incompatible with these options. @item arm_v8_2a_dotprod_neon_hw -ARM target supports executing instructions from ARMv8.2 with the Dot +ARM target supports executing instructions from ARMv8.2-A with the Dot Product extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_dotprod_neon_ok. @@ -2348,24 +2348,24 @@ arm vfp3 floating point support; see the @ref{arm_vfp3_ok,,arm_vfp3_ok effective target keyword}. @item arm_v8_1a_neon -Add options for ARMv8.1 with Adv.SIMD support, if this is supported +Add options for ARMv8.1-A with Adv.SIMD support, if this is supported by the target; see the @ref{arm_v8_1a_neon_ok,,arm_v8_1a_neon_ok} effective target keyword. @item arm_v8_2a_fp16_scalar -Add options for ARMv8.2 with scalar FP16 support, if this is +Add options for ARMv8.2-A with scalar FP16 support, if this is supported by the target; see the @ref{arm_v8_2a_fp16_scalar_ok,,arm_v8_2a_fp16_scalar_ok} effective target keyword. @item arm_v8_2a_fp16_neon -Add options for ARMv8.2 with Adv.SIMD FP16 support, if this is +Add options for ARMv8.2-A with Adv.SIMD FP16 support, if this is supported by the target; see the @ref{arm_v8_2a_fp16_neon_ok,,arm_v8_2a_fp16_neon_ok} effective target keyword. @item arm_v8_2a_dotprod_neon -Add options for ARMv8.2 with Adv.SIMD Dot Product support, if this is +Add options for ARMv8.2-A with Adv.SIMD Dot Product support, if this is supported by the target; see the @ref{arm_v8_2a_dotprod_neon_ok} effective target keyword.