From patchwork Wed Oct 9 23:49:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWHm3ky4z9s7T for ; Thu, 10 Oct 2019 10:53:08 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f8fNGZ3n"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWHm0qW3zDqYb for ; Thu, 10 Oct 2019 10:53:08 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f8fNGZ3n"; dkim-atps=neutral Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHd2kL4zDqY6 for ; Thu, 10 Oct 2019 10:52:59 +1100 (AEDT) Received: by mail-pg1-x542.google.com with SMTP id r1so1252660pgj.12 for ; Wed, 09 Oct 2019 16:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1xmQN0HMUe7izAn5CnFxP61XiM024Q65zBlGLyNms18=; b=f8fNGZ3nLRzUmoE4YkT1Q6YURCmc6XpHfg3j8E5JW/yqQzCreziXSOdYDSoqSZsBau 2RBKQvdIaA/J5JFtjpDLA+5C9GjEChSvUzwyjabi7L4mUbfcuhAfm5R+FxcRkEoFzm2n hSqjWuJTCHedqAGY81Unh++AFlPpytPLIqm19A0zYW0JxQcb8gin3rIwYp8aWrTYbl0n KZ92lHJoZZpkPqROdV6KkYSTeaXdyqRyUogj+DIrcxTBLkDXEeVkC2q4D3/OTxRHBUQM bpbnF5uAxFPH7znPqjPcmSn3qwkRyfsmQxFtajaW0dJ6oVugly+i4Zw8Y7U7ZcbrLhB6 Ieeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1xmQN0HMUe7izAn5CnFxP61XiM024Q65zBlGLyNms18=; b=hQg8eBd2qgYNG07QiT88R2KApyLC7KaL1kCmIGdsOEdo5SrK7MwcsrOWTIojUjyMIU jnzNU3YwuOBg0KBhqClfd/q3qyBEIWECEoaoiXGve+mUYELftDaSv/TJFi3A858DYv7E YX2HmyYPHk18ppk0+MnPuniVEVXPs6/2DInqrilwaRz6Z+4FHNHPYZPOppBrkPWLOLnF dmnvu87r0uSYw6dtcGLrfXQ3CuQajtYU4AHv2rCBtC7ZXbm3B3kLoD7IcKuIDl+ljSf8 jI4QTw9MGqWLSxDr7Z67I0MJRc6ypGs1qnswpId5MstDAAYGOrV4A90eRgLsRnT1GrgT nPnw== X-Gm-Message-State: APjAAAVisgN4Qgla+zzMvpHdC9RzEivlpop4QajP/EEFhWM2o280Q0UY l3PbwrvutsCGb3+MCeHtuhTnjNYS X-Google-Smtp-Source: APXvYqzyky9NRNco4XyZPOREdYMXDudxnI6CjCHlIIe1+TckHW+/AeFskk4/6paCmub4tBieA31Sjw== X-Received: by 2002:a17:90a:b304:: with SMTP id d4mr7395716pjr.27.1570665177303; Wed, 09 Oct 2019 16:52:57 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:52:56 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:37 +1000 Message-Id: <20191009234951.2850-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 01/15] asm/cvc_entry.S: r2 save fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The TOC save area for the current stack frame should be used to save r2, not the caller's frame. Signed-off-by: Nicholas Piggin Acked-by: Stewart Smith --- asm/cvc_entry.S | 9 +++++++-- include/stack.h | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/asm/cvc_entry.S b/asm/cvc_entry.S index 1296e88fe..3e8b3fdad 100644 --- a/asm/cvc_entry.S +++ b/asm/cvc_entry.S @@ -24,6 +24,11 @@ #.include "kernel/ppcconsts.S" +# Updated hostboot location is src/securerom/rom_entry.S. +# This also has a fix for TOC save frame pointer. + +#include + .section .text .global __cvc_verify_v1 @@ -33,10 +38,10 @@ __cvc_verify_v1: __cvc_sha512_v1: call_rom_entry: - std %r2, 40(%r1) mflr %r0 std %r0, 16(%r1) stdu %r1, -128(%r1) + std %r2, STACK_TOC_OFFSET(%r1) li %r2, 0 mtctr %r3 mr %r3, %r4 @@ -45,8 +50,8 @@ call_rom_entry: mr %r6, %r7 mr %r7, %r8 bctrl + ld %r2, STACK_TOC_OFFSET(%r1) addi %r1, %r1, 128 - ld %r2, 40(%r1) ld %r0, 16(%r1) mtlr %r0 blr diff --git a/include/stack.h b/include/stack.h index 3ad52d64c..09d22adb6 100644 --- a/include/stack.h +++ b/include/stack.h @@ -11,6 +11,8 @@ #define STACK_ENTRY_RESET 0x0100 /* System reset */ #define STACK_ENTRY_SOFTPATCH 0x1500 /* Soft patch (denorm emulation) */ +#define STACK_TOC_OFFSET 40 + /* Safety/ABI gap at top of stack */ #define STACK_TOP_GAP 0x100 From patchwork Wed Oct 9 23:49:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWJf2p9pz9s7T for ; Thu, 10 Oct 2019 10:53:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SlG4jURV"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWJc3mYGzDqY6 for ; Thu, 10 Oct 2019 10:53:52 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::536; helo=mail-pg1-x536.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SlG4jURV"; dkim-atps=neutral Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHd6stLzDqY6 for ; Thu, 10 Oct 2019 10:53:01 +1100 (AEDT) Received: by mail-pg1-x536.google.com with SMTP id i76so2459445pgc.0 for ; Wed, 09 Oct 2019 16:53:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y2+l256D8I6EQm11YigDNOiNPItbc5d0s/QzFLB/Bc0=; b=SlG4jURV+RWzIjzZAJTY7IdP2i1E7wL4vLb56UXulb122D6b8sy0Cb1GJGcI8Z4vPI oYU9DJZINWsvnGG9TsdEmaFJTt4S/0Eo55PbgYkmqoxQDi5AKnPnt+HkMGhTvJaH/f+8 EvsZO6wRrv6BCRkOOlWVi273Y7fcLBjxcCjB8HlmKCrYXgHfCfE2MrAcrVEL513mtM+/ eSoasJr5Wi1+TlpGoDoPxp6YDUun44mQFhSzy8CKU6wSZw79beTqeyZS2VfPa5WmXGpp 2DG/yTyxqaRu2KJ1yJEH71+l1cDFdp0wvCzf29uCE+whvMkMzphRx/5fmOwN7RkMBC22 YQ0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y2+l256D8I6EQm11YigDNOiNPItbc5d0s/QzFLB/Bc0=; b=GTkAEnFCO5QhOwH3G9sqXVlIg0Pw4RJGG+OFWf6MRWQXhZmL9O3FoMcBLqiaTdsnuy 8Xt+4LiFSC8KvBCl6A0FT09MBZHVFdZGkc4xCSL8eQ1G6ZVxu3aZSS+KVv04e76kNPw6 1XHEqJETB+SWsqefw6z8XkXW7vjpil1uxvupxFkzL+DwruOmY2HdPepV98r6wb7rvvDg YPqMWhBwHIKqHt5v9D4GFN3pLfhkfGKluvubWpGmevn7GshRk0bQ7ejSWpX2mU9aQQMt 3k2K5ZsS0HLROo74Cy6LkdP68qCmWtSKo2mJCJIw2PLnQul0Z5cSrF0s+pnht5k7w5M5 CjWw== X-Gm-Message-State: APjAAAXOLrXyJZlrQQozT5jSw23kqaTQ7GIl36U8/YGXxqhrhpz+wvUu 8831SG5G2vwF68FJw6Amo3FT72mp X-Google-Smtp-Source: APXvYqynfK7UK5j/uZNav1+lFU5224cpbud2t9wUyYFEu9nlouhz0+Dc9DHcSvsRg+48Pst2SpYe6A== X-Received: by 2002:a62:b616:: with SMTP id j22mr6538440pff.35.1570665179171; Wed, 09 Oct 2019 16:52:59 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:52:58 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:38 +1000 Message-Id: <20191009234951.2850-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 02/15] Remove dead POWER7 code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. And change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. Signed-off-by: Nicholas Piggin Acked-by: Stewart Smith --- asm/head.S | 10 ------- hdata/paca.c | 80 ---------------------------------------------------- 2 files changed, 90 deletions(-) diff --git a/asm/head.S b/asm/head.S index 58f9aea97..426b5d5c1 100644 --- a/asm/head.S +++ b/asm/head.S @@ -857,16 +857,6 @@ hv_lid_load_table: .long 0 - /* The FSP seems to ignore our primary/secondary entry - * points and instead copy that bit down to 0x180 and - * patch the first instruction to get our expected - * boot CPU number. We ignore that patching for now and - * got to the same entry we use for pHyp and FDT HB. - */ -opal_boot_trampoline: - li %r27,-1 - ba boot_entry - __head - /* * * OPAL entry point from operating system diff --git a/hdata/paca.c b/hdata/paca.c index 28025b0cd..3e8d89856 100644 --- a/hdata/paca.c +++ b/hdata/paca.c @@ -12,8 +12,6 @@ #include "hdata.h" -#define PACA_MAX_THREADS 4 - static unsigned int paca_index(const struct HDIF_common_hdr *paca) { void *start = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); @@ -121,77 +119,6 @@ static void add_be32_sorted(__be32 arr[], __be32 new, unsigned num) arr[i] = new; } -static void add_xics_icps(void) -{ - struct dt_node *cpu; - unsigned int i; - u64 reg[PACA_MAX_THREADS * 2]; - struct dt_node *icp; - - dt_for_each_node(dt_root, cpu) { - u32 irange[2], size, pir; - const struct dt_property *intsrv; - const struct HDIF_common_hdr *paca; - u64 ibase; - unsigned int num_threads; - bool found = false; - - if (!dt_has_node_property(cpu, "device_type", "cpu")) - continue; - - intsrv = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); - if (!intsrv) - continue; - - pir = dt_prop_get_u32(cpu, "ibm,pir"); - - /* Get ibase address */ - paca = get_hdif(&spira.ntuples.paca, PACA_HDIF_SIG); - for_each_paca(paca) { - const struct sppaca_cpu_id *id; - id = HDIF_get_idata(paca, SPPACA_IDATA_CPU_ID, &size); - - if (!CHECK_SPPTR(id)) - continue; - - if (pir != be32_to_cpu(id->pir)) - continue; - ibase = cleanup_addr(be64_to_cpu(id->ibase)); - found = true; - break; - } - if (!found) - return; - - num_threads = intsrv->len / sizeof(u32); - assert(num_threads <= PACA_MAX_THREADS); - - icp = dt_new_addr(dt_root, "interrupt-controller", ibase); - if (!icp) - continue; - - dt_add_property_strings(icp, "compatible", - "IBM,ppc-xicp", - "IBM,power7-xicp"); - - irange[0] = dt_property_get_cell(intsrv, 0); /* Index */ - irange[1] = num_threads; /* num servers */ - dt_add_property(icp, "ibm,interrupt-server-ranges", - irange, sizeof(irange)); - dt_add_property(icp, "interrupt-controller", NULL, 0); - dt_add_property_cells(icp, "#address-cells", 0); - dt_add_property_string(icp, "device_type", - "PowerPC-External-Interrupt-Presentation"); - for (i = 0; i < num_threads*2; i += 2) { - reg[i] = ibase; - /* One page is enough for a handful of regs. */ - reg[i+1] = 4096; - ibase += reg[i+1]; - } - dt_add_property(icp, "reg", reg, sizeof(reg)); - } -} - static bool __paca_parse(void) { const struct HDIF_common_hdr *paca; @@ -311,13 +238,6 @@ static bool __paca_parse(void) free(new_prop); } - /* - * P7 and P8 use the XICS interrupt controller which has a per-core - * interrupt controller node. - */ - if (proc_gen <= proc_gen_p8) - add_xics_icps(); - return true; } From patchwork Wed Oct 9 23:49:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174201 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWK55S6wz9s7T for ; Thu, 10 Oct 2019 10:54:17 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QGi6euSq"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWK53vmczDqZC for ; Thu, 10 Oct 2019 10:54:17 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::644; helo=mail-pl1-x644.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QGi6euSq"; dkim-atps=neutral Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHg5kprzDqY2 for ; Thu, 10 Oct 2019 10:53:03 +1100 (AEDT) Received: by mail-pl1-x644.google.com with SMTP id d22so1851652pls.0 for ; Wed, 09 Oct 2019 16:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D898OVmCpaXB7gf0K4GVYHo3J3bIM1vKrcipi1vF/Dk=; b=QGi6euSqZerni7mQvP55VxrtfwJwpm8UzFrOX6Y9EyqoS0djAbMPS5G/n3qgvd0Zn/ RwrRMjgmgXS24Ckq2d9RL+Rs5CVE4xeFygKmgE1WLdsOnpR9thqsMbLi4UOtL3sczLAb FmzjhdppPZb/tAONkq7iKK4mu1X4pmFim9163eSDwBv467DzIho70FHWCitj71X86Nt+ w/2tGeTaoPqLAGavlGqE0caHWzofjl49Bu1z1PJ+2x93M9Ss0uV3Z655fdtjze1f2jkr dr2U69o1SByzmcbNMNQpNPBHIW9hCL72ovlPZiYMtFwuq6u7PcxRD3wEMmWH37umUyDp zRFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D898OVmCpaXB7gf0K4GVYHo3J3bIM1vKrcipi1vF/Dk=; b=oMMmNZNb5wMNa6kZm0fMnYP+YjdMlXz9Dm/pr6MzSaUpkjwMTSmc8a1CnmkT6RYvOH aclLY/qYIjfnN1+kuuYHOMaK+rL6MFr6IlU5DI/YbH+iwJm1UHNEId/EvQdo1mR1CGkm MYgyGd+xSWPn1fzoOLwD2CuEPJhEjr01Po5Y1FnxSD6+780IP1siitiXCHnCN351QcBl R6e9fn8mAPkLHKUOxsr9AirO1iJMphOlz9FfingxrngA4hdbWKmcxdSdxpQZ4cgq8GTL EJxxvSDAxDEVQ15ClIz/MhwbIoimdUbnpXgeaD8Be09soV/01/+KVMlKEXaW9JRY2xlC dniw== X-Gm-Message-State: APjAAAWqR3Tk0tOLX87WcSpBFwuM143ZZuRE2AgtcV9H9RFgZYZ9U/X9 /AJRMZM6LnsmTidQrhr9hVcVqTcZ X-Google-Smtp-Source: APXvYqz6mLPIhjooXXPo7bz0JsJdQNNyglCrFppBT6q3wJUE0sbnwgTtE4vcExRQi6iuoIWNc/hOlw== X-Received: by 2002:a17:902:d691:: with SMTP id v17mr5580179ply.340.1570665181035; Wed, 09 Oct 2019 16:53:01 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:00 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:39 +1000 Message-Id: <20191009234951.2850-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 03/15] capp: fix endian conversion X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin Acked-by: Stewart Smith Reviewed-by: Andrew Donnellan --- hw/capp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/capp.c b/hw/capp.c index 709e6db14..269deb637 100644 --- a/hw/capp.c +++ b/hw/capp.c @@ -168,7 +168,7 @@ int64_t capp_load_ucode(unsigned int chip_id, uint32_t opal_id, /* 'CAPPULID' in ASCII */ if ((be64_to_cpu(ucode->eyecatcher) != 0x43415050554C4944UL) || - (be64_to_cpu(ucode->version != 1))) { + (be64_to_cpu(ucode->version) != 1)) { PHBERR(opal_id, chip_id, index, "CAPP: ucode header invalid\n"); return OPAL_HARDWARE; From patchwork Wed Oct 9 23:49:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWKP0wrPz9s7T for ; Thu, 10 Oct 2019 10:54:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="unlPAkRF"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWKN5JTVzDqYC for ; Thu, 10 Oct 2019 10:54:32 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="unlPAkRF"; dkim-atps=neutral Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHj3kfVzDqY2 for ; Thu, 10 Oct 2019 10:53:05 +1100 (AEDT) Received: by mail-pg1-x542.google.com with SMTP id x10so2447068pgi.5 for ; Wed, 09 Oct 2019 16:53:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cTgMuMMvyIm0O4m7Y4jwSUkUzUbjEVFVh6aZSl79gmY=; b=unlPAkRFeLOEmSyBHIq8WXjXAP6/JAD4xTGx+3SSdaeoOJiEFaxGUQ/BwhFTdA8zm5 yDU6em0gfmaa4gBnyKr/Dq7Skln6d7A6XEc61Dy//xJcGaNCD1CCUOd1IzxrRYSWaVxT AU4wjfaLVh0aZr8vOYvKuZRAH9umGdzQDrnp42OzlDGPgVaX8/sbeB7cPqVUygt/W6Pc IEOJWxwR7DpoF/mp9Yx+aHPzrXLXmmYBkdl7+bcc7DuXWb+N0eVFbomnM4jhN3eeDvE+ LBUDyAw6LDHSig+NR9BV7+BpoP5ZBxOnkANTREFPyJiEFLCSP8IpK7mfsGsUlKzz3w8C EhCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cTgMuMMvyIm0O4m7Y4jwSUkUzUbjEVFVh6aZSl79gmY=; b=uNiaeohILGHqfEAU/fjBjLeTqcBEcWEzfHDlCcGFFPAIn6+2+JdKZn3l7UdGv8tRgO 8UGZSbnwCCDigMa26KdXlL23kXHQN5gt5MyQgFx76cWCSts7hOvB9h/+qPrJ5O5MHsYp u8qWcfVuBjNZ5IiXTLDyrn4o7z86FqLsarCBNKXZKBjsH85GtPKVd72Of8ipSyPQVQ3E gCFht5oyO8zqUpRHc7jSjL6c9sNGuFkh0hps8/iq1CZp5MIY+Kp8RS8+iu4nsgHDFlvX +5L9f6zscJmlsT86p1sGehL6XKNnPj02wuutmjpkG2lZzkLN/odQ/ikki9bT4h30nQtH SxTA== X-Gm-Message-State: APjAAAU3D8mVAu4/1jYJWXpfKXB3cepyQ26tCJBOS/58LeydCbTudfuE RMEW1L8tdzePJh/o8seokpdGKoe2 X-Google-Smtp-Source: APXvYqx/oky8oXKfsmkE/uE10OgsbqUJGqU6WKqwswmKbXpg0hWbnDxBkEVAm6ndwEy1cZJhYGv2GQ== X-Received: by 2002:a63:131b:: with SMTP id i27mr7014409pgl.209.1570665183343; Wed, 09 Oct 2019 16:53:03 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:02 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:40 +1000 Message-Id: <20191009234951.2850-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 04/15] cpu: use dt accessor device tree access X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- core/cpu.c | 2 +- core/device.c | 1 + core/fdt.c | 4 ++-- core/interrupts.c | 4 ++-- core/pci.c | 28 +++++++++++++--------------- hdata/fsp.c | 7 ++++--- hdata/iohub.c | 20 ++++++++++---------- hw/fsp/fsp-sysparam.c | 4 ++-- hw/fsp/fsp.c | 2 +- hw/imc.c | 4 ++-- hw/lpc.c | 6 +++--- hw/psi.c | 8 ++++---- hw/vas.c | 7 ++++--- 13 files changed, 49 insertions(+), 48 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index d0e4cdc1c..b3433aef5 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1214,7 +1214,7 @@ void init_all_cpus(void) t = &cpu_stacks[pir + thread].cpu; init_cpu_thread(t, state, pir + thread); t->trace = boot_cpu->trace; - t->server_no = ((const u32 *)p->prop)[thread]; + t->server_no = dt_property_get_cell(p, thread); t->is_secondary = true; t->primary = pt; t->node = cpu; diff --git a/core/device.c b/core/device.c index ce0171b67..0118d485f 100644 --- a/core/device.c +++ b/core/device.c @@ -1110,6 +1110,7 @@ void dt_adjust_subtree_phandle(struct dt_node *dev, continue; phandle = dt_prop_get_u32(node, *name); phandle += import_phandle; + phandle = cpu_to_be32(phandle); memcpy((char *)&prop->prop, &phandle, prop->len); } } diff --git a/core/fdt.c b/core/fdt.c index d3c6d9fa1..e093e8b54 100644 --- a/core/fdt.c +++ b/core/fdt.c @@ -146,8 +146,8 @@ static void create_dtb_reservemap(void *fdt, const struct dt_node *root) ranges = (const void *)prop->prop; for (i = 0; i < prop->len / (sizeof(uint64_t) * 2); i++) { - base = *(ranges++); - size = *(ranges++); + base = be64_to_cpu(*(ranges++)); + size = be64_to_cpu(*(ranges++)); save_err(fdt_add_reservemap_entry(fdt, base, size)); } } diff --git a/core/interrupts.c b/core/interrupts.c index b0c1da198..10baa15f6 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -231,8 +231,8 @@ void add_opal_interrupts(void) names[tns++] = 0; i = count++; irqs = realloc(irqs, 8 * count); - irqs[i*2] = isn; - irqs[i*2+1] = iflags; + irqs[i*2] = cpu_to_be32(isn); + irqs[i*2+1] = cpu_to_be32(iflags); } } unlock(&irq_lock); diff --git a/core/pci.c b/core/pci.c index 9ee70f4fd..6c5c83bea 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1334,7 +1334,7 @@ void pci_std_swizzle_irq_map(struct dt_node *np, { uint32_t *map, *p; int dev, irq, esize, edevcount; - size_t map_size, isize; + size_t map_size; /* Some emulated setups don't use standard interrupts * representation @@ -1342,9 +1342,6 @@ void pci_std_swizzle_irq_map(struct dt_node *np, if (lstate->int_size == 0) return; - /* Size in bytes of a target interrupt */ - isize = lstate->int_size * sizeof(uint32_t); - /* Calculate the size of a map entry: * * 3 cells : PCI Address @@ -1384,22 +1381,23 @@ void pci_std_swizzle_irq_map(struct dt_node *np, for (dev = 0; dev < edevcount; dev++) { for (irq = 0; irq < 4; irq++) { /* Calculate pin */ + size_t i; uint32_t new_irq = (irq + dev + swizzle) % 4; /* PCI address portion */ - *(p++) = dev << (8 + 3); + *(p++) = cpu_to_be32(dev << (8 + 3)); *(p++) = 0; *(p++) = 0; /* PCI interrupt portion */ - *(p++) = irq + 1; + *(p++) = cpu_to_be32(irq + 1); /* Parent phandle */ - *(p++) = lstate->int_parent[new_irq]; + *(p++) = cpu_to_be32(lstate->int_parent[new_irq]); /* Parent desc */ - memcpy(p, lstate->int_val[new_irq], isize); - p += lstate->int_size; + for (i = 0; i < lstate->int_size; i++) + *(p++) = cpu_to_be32(lstate->int_val[new_irq][i]); } } @@ -1549,16 +1547,16 @@ static void __noinline pci_add_one_device_node(struct phb *phb, char name[MAX_NAME]; char compat[MAX_NAME]; uint32_t rev_class, vdid; - uint32_t reg[5]; + __be32 reg[5]; uint8_t intpin; bool is_pcie; - const uint32_t ranges_direct[] = { + const __be32 ranges_direct[] = { /* 64-bit direct mapping. We know the bridges * don't cover the entire address space so * use 0xf00... as a good compromise. */ - 0x02000000, 0x0, 0x0, - 0x02000000, 0x0, 0x0, - 0xf0000000, 0x0}; + cpu_to_be32(0x02000000), 0x0, 0x0, + cpu_to_be32(0x02000000), 0x0, 0x0, + cpu_to_be32(0xf0000000), 0x0}; pci_cfg_read32(phb, pd->bdfn, 0, &vdid); pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class); @@ -1635,7 +1633,7 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * entry in the "reg" property. That's enough for Linux and we might * even want to make this legit in future ePAPR */ - reg[0] = pd->bdfn << 8; + reg[0] = cpu_to_be32(pd->bdfn << 8); reg[1] = reg[2] = reg[3] = reg[4] = 0; dt_add_property(np, "reg", reg, sizeof(reg)); diff --git a/hdata/fsp.c b/hdata/fsp.c index 5923f1feb..fe36eef18 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -206,7 +206,7 @@ static void fsp_create_links(const void *spss, int index, chip = fsp_create_link(iopath, i, index); lp = lcount++; links = realloc(links, 4 * lcount); - links[lp] = chip; + links[lp] = cpu_to_be32(chip); } if (links) dt_add_property(fsp_node, "ibm,psi-links", links, lcount * 4); @@ -268,7 +268,7 @@ static void add_uart(const struct spss_iopath *iopath, struct dt_node *lpc) be32_to_cpu(iopath->lpc.uart_baud)); } -static void add_chip_id_to_sensors(struct dt_node *sensor_node, __be32 slca_index) +static void add_chip_id_to_sensors(struct dt_node *sensor_node, uint32_t slca_index) { unsigned int i; const void *hdif; @@ -347,7 +347,8 @@ static void add_ipmi_sensors(struct dt_node *bmc_node) dt_add_property_cells(sensor_node, "ipmi-sensor-type", ipmi_sensors->data[i].type); - add_chip_id_to_sensors(sensor_node, ipmi_sensors->data[i].slca_index); + add_chip_id_to_sensors(sensor_node, + be32_to_cpu(ipmi_sensors->data[i].slca_index)); } } diff --git a/hdata/iohub.c b/hdata/iohub.c index 6921d95ce..2af040a2f 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -109,12 +109,12 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, /* "reg" property contains in order the PE, PCI and SPCI XSCOM * addresses */ - reg[0] = pe_xscom; - reg[1] = 0x20; - reg[2] = pci_xscom; - reg[3] = 0x05; - reg[4] = spci_xscom; - reg[5] = 0x15; + reg[0] = cpu_to_be32(pe_xscom); + reg[1] = cpu_to_be32(0x20); + reg[2] = cpu_to_be32(pci_xscom); + reg[3] = cpu_to_be32(0x05); + reg[4] = cpu_to_be32(spci_xscom); + reg[5] = cpu_to_be32(0x15); dt_add_property(pbcq, "reg", reg, sizeof(reg)); /* A couple more things ... */ @@ -214,10 +214,10 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, return NULL; /* "reg" property contains (in order) the PE and PCI XSCOM addresses */ - reg[0] = pe_xscom; - reg[1] = 0x100; - reg[2] = pci_xscom; - reg[3] = 0x200; + reg[0] = cpu_to_be32(pe_xscom); + reg[1] = cpu_to_be32(0x100); + reg[2] = cpu_to_be32(pci_xscom); + reg[3] = cpu_to_be32(0x200); dt_add_property(pbcq, "reg", reg, sizeof(reg)); /* The hubs themselves go under the stacks */ diff --git a/hw/fsp/fsp-sysparam.c b/hw/fsp/fsp-sysparam.c index 09005ef87..0e1e8181f 100644 --- a/hw/fsp/fsp-sysparam.c +++ b/hw/fsp/fsp-sysparam.c @@ -469,8 +469,8 @@ static void add_opal_sysparam_node(void) strcpy(s, sysparam_attrs[i].name); s = s + strlen(sysparam_attrs[i].name) + 1; - ids[i] = sysparam_attrs[i].id; - lens[i] = sysparam_attrs[i].length; + ids[i] = cpu_to_be32(sysparam_attrs[i].id); + lens[i] = cpu_to_be32(sysparam_attrs[i].length); perms[i] = sysparam_attrs[i].perm; } diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 6fa6534f9..7193c6f4c 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -1915,7 +1915,7 @@ static void fsp_init_links(struct dt_node *fsp_node) u64 reg; u32 link; - link = ((const u32 *)linksprop->prop)[i]; + link = be32_to_cpu(((const __be32 *)linksprop->prop)[i]); fiop = &fsp->iopath[i]; fiop->psi = psi_find_link(link); if (fiop->psi == NULL) { diff --git a/hw/imc.c b/hw/imc.c index ca06f3c36..16b060d39 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -458,8 +458,8 @@ static void imc_dt_update_nest_node(struct dt_node *dev) base_addr = malloc(sizeof(uint64_t) * nr_chip); chipids = malloc(sizeof(uint32_t) * nr_chip); for_each_chip(chip) { - base_addr[i] = chip->homer_base; - chipids[i] = chip->id; + base_addr[i] = cpu_to_be64(chip->homer_base); + chipids[i] = cpu_to_be32(chip->id); i++; } diff --git a/hw/lpc.c b/hw/lpc.c index 354d2b4f0..3411f036f 100644 --- a/hw/lpc.c +++ b/hw/lpc.c @@ -884,9 +884,9 @@ static void lpc_create_int_map(struct lpcm *lpc, struct dt_node *psi_node) continue; *(pmap++) = 0; *(pmap++) = 0; - *(pmap++) = i; - *(pmap++) = psi_node->phandle; - *(pmap++) = lpc->sirq_routes[i] + P9_PSI_IRQ_LPC_SIRQ0; + *(pmap++) = cpu_to_be32(i); + *(pmap++) = cpu_to_be32(psi_node->phandle); + *(pmap++) = cpu_to_be32(lpc->sirq_routes[i] + P9_PSI_IRQ_LPC_SIRQ0); } if (pmap == map) return; diff --git a/hw/psi.c b/hw/psi.c index bc170bbcf..3b497a092 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -786,10 +786,10 @@ static void psi_create_p9_int_map(struct psi *psi, struct dt_node *np) int i; for (i = 0; i < P9_PSI_NUM_IRQS; i++) { - map[i][0] = i; - map[i][1] = get_ics_phandle(); - map[i][2] = psi->interrupt + i; - map[i][3] = 1; + map[i][0] = cpu_to_be32(i); + map[i][1] = cpu_to_be32(get_ics_phandle()); + map[i][2] = cpu_to_be32(psi->interrupt + i); + map[i][3] = cpu_to_be32(1); } dt_add_property(np, "interrupt-map", map, sizeof(map)); dt_add_property_cells(np, "#address-cells", 0); diff --git a/hw/vas.c b/hw/vas.c index 212da0ec1..3c5ebc920 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -375,7 +375,7 @@ static struct vas *alloc_vas(uint32_t chip_id, uint32_t vas_id, uint64_t base) static void create_mm_dt_node(struct proc_chip *chip) { - int gcid; + uint32_t gcid, vas_id; struct dt_node *dn; struct vas *vas; uint64_t hvwc_start, hvwc_len; @@ -384,7 +384,8 @@ static void create_mm_dt_node(struct proc_chip *chip) uint64_t pbf_start, pbf_nbits; vas = chip->vas; - gcid = chip->id; + vas_id = cpu_to_be32(vas->vas_id); + gcid = cpu_to_be32(chip->id); get_hvwc_mmio_bar(chip->id, &hvwc_start, &hvwc_len); get_uwc_mmio_bar(chip->id, &uwc_start, &uwc_len); get_paste_bar(chip->id, &pbar_start, &pbar_len); @@ -400,7 +401,7 @@ static void create_mm_dt_node(struct proc_chip *chip) pbar_start, pbar_len, pbf_start, pbf_nbits); - dt_add_property(dn, "ibm,vas-id", &vas->vas_id, sizeof(vas->vas_id)); + dt_add_property(dn, "ibm,vas-id", &vas_id, sizeof(vas_id)); dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid)); } From patchwork Wed Oct 9 23:49:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWKk2c26z9s7T for ; Thu, 10 Oct 2019 10:54:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IgMBk51Q"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWKk1PnZzDqYq for ; Thu, 10 Oct 2019 10:54:50 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::42b; helo=mail-pf1-x42b.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IgMBk51Q"; dkim-atps=neutral Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHm6tQkzDqZB for ; Thu, 10 Oct 2019 10:53:08 +1100 (AEDT) Received: by mail-pf1-x42b.google.com with SMTP id a2so2649110pfo.10 for ; Wed, 09 Oct 2019 16:53:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uJ/+LT1E/tQsZSHrgSnHAsSU8Pneuu1keaGsM4KDfmM=; b=IgMBk51QfdzEWy/kQoJxnWpymCwaWkDiwjsyc8IKNo4pqKp4ljRL1R7N949KUkeLVW qexpXDgsZHvvseNJ5VrSVR/UF4M3qwwsV9C4KrfIIj5uxDKz6qzNRMj1r2Fl3calo0m8 N6v6MgDPyHjd/7TE0dX0RvAEGC2rQ9+HsN+coqjth7pyOZLLkr1iZmbnUGhDa39VLNik 6HWFlT3RMKE6uYxsa/jleJ7hMTPpQiZmgOxa0BGq6OLmQ1RaQHAJvs6/tXXFL4d+f2mp +6ovXCQbwqi6LwryBM4DSS6Mv8mHfF98ndS06snV+ItKqAXPuSrKXWEWVEyl5MdsvaBl pbbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uJ/+LT1E/tQsZSHrgSnHAsSU8Pneuu1keaGsM4KDfmM=; b=AYsyVEAjHbCQhY4jpFExHvmGlF2J6eV60jzfnEwBJ2/OLhFiwMckGBpbbt6NtavABL 7b2sSTh0rrWP5Rlahor8eWhiCqOf9W/r73YtaZOFDqgpoR16LlPQ73wJsPz2TwCRgOHw fYCDEOMrwApBig17vIWge1ANMHdAt8x/RqOBMWuxxomgtLGqekyv//bphiDQv7oPUPO0 eHn9nGjGqwCLSdk9lmgMSGKBxqB0194bjMlqEQ4sln2LpsD2dSjQY6jkipGI2wNqUY6t bYXJra3u85bflkKXQ/0lcX8mJSgs9bohgxZ6WV1jQxbxJy48TDq3ZzUjpu/je88gkDYh Ioqg== X-Gm-Message-State: APjAAAVC52qHiKreAoVCuosPcAgwWYQs25wFheVsg3MFXafbZzDtGv+A 9nPcvPzrP0EX+X+1fiaJOtuMeTet X-Google-Smtp-Source: APXvYqyBA+BdCz5kqP9jquv6Y979kUOZmxUoEg58xF64IxyfJCpjrrfKmn6UvSa37rTbI27yCH20ug== X-Received: by 2002:a65:5cc5:: with SMTP id b5mr7077642pgt.137.1570665185547; Wed, 09 Oct 2019 16:53:05 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:05 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:41 +1000 Message-Id: <20191009234951.2850-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 05/15] opal-api: add endian conversions to most opal calls X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds missing endian conversions to most calls, sufficient at least to handle calls from a kernel booting on mambo. Subsystems requiring more extensive changes (e.g., xive) will be done with individual changes. Signed-off-by: Nicholas Piggin --- core/console.c | 19 +++++--- core/interrupts.c | 8 +++- core/ipmi-opal.c | 6 +-- core/pci-opal.c | 98 +++++++++++++++++++++++++++++++---------- core/powercap.c | 14 ++++-- core/psr.c | 14 ++++-- core/sensor.c | 36 ++++++++++----- hw/fake-rtc.c | 11 +++-- hw/fsp/fsp-console.c | 26 ++++++----- hw/fsp/fsp-rtc.c | 26 ++++++----- hw/ipmi/ipmi-rtc.c | 12 +++-- hw/lpc-rtc.c | 12 +++-- hw/lpc-uart.c | 16 +++---- hw/npu2-opencapi.c | 12 +++-- hw/xscom.c | 19 +++++++- include/console.h | 6 +-- platforms/mambo/mambo.c | 7 ++- 17 files changed, 238 insertions(+), 104 deletions(-) diff --git a/core/console.c b/core/console.c index 139ba4a97..ac88f0c71 100644 --- a/core/console.c +++ b/core/console.c @@ -351,22 +351,25 @@ void memcons_add_properties(void) * complicated since they can come from the in-memory console (BML) or from the * internal skiboot console driver. */ -static int64_t dummy_console_write(int64_t term_number, int64_t *length, +static int64_t dummy_console_write(int64_t term_number, __be64 *length, const uint8_t *buffer) { + uint64_t l; + if (term_number != 0) return OPAL_PARAMETER; if (!opal_addr_valid(length) || !opal_addr_valid(buffer)) return OPAL_PARAMETER; - write(0, buffer, *length); + l = be64_to_cpu(*length); + write(0, buffer, l); return OPAL_SUCCESS; } static int64_t dummy_console_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *length) { if (term_number != 0) return OPAL_PARAMETER; @@ -375,21 +378,25 @@ static int64_t dummy_console_write_buffer_space(int64_t term_number, return OPAL_PARAMETER; if (length) - *length = INMEM_CON_OUT_LEN; + *length = cpu_to_be64(INMEM_CON_OUT_LEN); return OPAL_SUCCESS; } -static int64_t dummy_console_read(int64_t term_number, int64_t *length, +static int64_t dummy_console_read(int64_t term_number, __be64 *length, uint8_t *buffer) { + uint64_t l; + if (term_number != 0) return OPAL_PARAMETER; if (!opal_addr_valid(length) || !opal_addr_valid(buffer)) return OPAL_PARAMETER; - *length = read(0, buffer, *length); + l = be64_to_cpu(*length); + l = read(0, buffer, l); + *length = cpu_to_be64(l); opal_update_pending_evt(OPAL_EVENT_CONSOLE_INPUT, 0); return OPAL_SUCCESS; diff --git a/core/interrupts.c b/core/interrupts.c index 10baa15f6..d4a2c3124 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -439,9 +439,11 @@ static int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority) } opal_call(OPAL_SET_XIVE, opal_set_xive, 3); -static int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority) +static int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority) { struct irq_source *is = irq_find_source(isn); + uint16_t s; + int64_t ret; if (!opal_addr_valid(server)) return OPAL_PARAMETER; @@ -449,7 +451,9 @@ static int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority) if (!is || !is->ops->get_xive) return OPAL_PARAMETER; - return is->ops->get_xive(is, isn, server, priority); + ret = is->ops->get_xive(is, isn, &s, priority); + *server = cpu_to_be16(s); + return ret; } opal_call(OPAL_GET_XIVE, opal_get_xive, 3); diff --git a/core/ipmi-opal.c b/core/ipmi-opal.c index 796508ca0..d36962d36 100644 --- a/core/ipmi-opal.c +++ b/core/ipmi-opal.c @@ -57,7 +57,7 @@ static int64_t opal_ipmi_send(uint64_t interface, } static int64_t opal_ipmi_recv(uint64_t interface, - struct opal_ipmi_msg *opal_ipmi_msg, uint64_t *msg_len) + struct opal_ipmi_msg *opal_ipmi_msg, __be64 *msg_len) { struct ipmi_msg *msg; int64_t rc; @@ -82,7 +82,7 @@ static int64_t opal_ipmi_recv(uint64_t interface, goto out_del_msg; } - if (*msg_len - sizeof(struct opal_ipmi_msg) < msg->resp_size + 1) { + if (be64_to_cpu(*msg_len) - sizeof(struct opal_ipmi_msg) < msg->resp_size + 1) { rc = OPAL_RESOURCE; goto out_del_msg; } @@ -101,7 +101,7 @@ static int64_t opal_ipmi_recv(uint64_t interface, msg->cmd, msg->netfn >> 2, msg->resp_size); /* Add one as the completion code is returned in the message data */ - *msg_len = msg->resp_size + sizeof(struct opal_ipmi_msg) + 1; + *msg_len = cpu_to_be64(msg->resp_size + sizeof(struct opal_ipmi_msg) + 1); ipmi_free_msg(msg); return OPAL_SUCCESS; diff --git a/core/pci-opal.c b/core/pci-opal.c index 213a72565..16b784e90 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -58,9 +58,38 @@ OPAL_PCICFG_ACCESS_WRITE(write_byte, write8, uint8_t) OPAL_PCICFG_ACCESS_WRITE(write_half_word, write16, uint16_t) OPAL_PCICFG_ACCESS_WRITE(write_word, write32, uint32_t) +static int64_t opal_pci_config_read_half_word_be(uint64_t phb_id, + uint64_t bus_dev_func, + uint64_t offset, + __be16 *__data) +{ + uint16_t data; + int64_t rc; + + rc = opal_pci_config_read_half_word(phb_id, bus_dev_func, offset, &data); + *__data = cpu_to_be16(data); + + return rc; +} + +static int64_t opal_pci_config_read_word_be(uint64_t phb_id, + uint64_t bus_dev_func, + uint64_t offset, + __be32 *__data) +{ + uint32_t data; + int64_t rc; + + rc = opal_pci_config_read_word(phb_id, bus_dev_func, offset, &data); + *__data = cpu_to_be32(data); + + return rc; +} + + opal_call(OPAL_PCI_CONFIG_READ_BYTE, opal_pci_config_read_byte, 4); -opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, opal_pci_config_read_half_word, 4); -opal_call(OPAL_PCI_CONFIG_READ_WORD, opal_pci_config_read_word, 4); +opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, opal_pci_config_read_half_word_be, 4); +opal_call(OPAL_PCI_CONFIG_READ_WORD, opal_pci_config_read_word_be, 4); opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, opal_pci_config_write_byte, 4); opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, opal_pci_config_write_half_word, 4); opal_call(OPAL_PCI_CONFIG_WRITE_WORD, opal_pci_config_write_word, 4); @@ -87,14 +116,15 @@ void opal_pci_eeh_clear_evt(uint64_t phb_id) static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, uint8_t *freeze_state, - uint16_t *pci_error_type, - uint64_t *phb_status) + __be16 *__pci_error_type, + __be64 *__phb_status) { struct phb *phb = pci_get_phb(phb_id); + uint16_t pci_error_type; int64_t rc; - if (!opal_addr_valid(freeze_state) || !opal_addr_valid(pci_error_type) - || !opal_addr_valid(phb_status)) + if (!opal_addr_valid(freeze_state) || !opal_addr_valid(__pci_error_type) + || !opal_addr_valid(__phb_status)) return OPAL_PARAMETER; if (!phb) @@ -103,12 +133,13 @@ static int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, return OPAL_UNSUPPORTED; phb_lock(phb); - if (phb_status) + if (__phb_status) prlog(PR_ERR, "PHB#%04llx: %s: deprecated PHB status\n", phb_id, __func__); rc = phb->ops->eeh_freeze_status(phb, pe_number, freeze_state, - pci_error_type, NULL); + &pci_error_type, NULL); + *__pci_error_type = cpu_to_be16(pci_error_type); phb_unlock(phb); return rc; @@ -371,12 +402,14 @@ opal_call(OPAL_PCI_SET_XIVE_PE, opal_pci_set_xive_pe, 3); static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, uint8_t msi_range, - uint32_t *msi_address, uint32_t *message_data) + __be32 *__msi_address, __be32 *__message_data) { struct phb *phb = pci_get_phb(phb_id); + uint32_t msi_address; + uint32_t message_data; int64_t rc; - if (!opal_addr_valid(msi_address) || !opal_addr_valid(message_data)) + if (!opal_addr_valid(__msi_address) || !opal_addr_valid(__message_data)) return OPAL_PARAMETER; if (!phb) @@ -385,21 +418,26 @@ static int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, return OPAL_UNSUPPORTED; phb_lock(phb); rc = phb->ops->get_msi_32(phb, mve_number, xive_num, msi_range, - msi_address, message_data); + &msi_address, &message_data); phb_unlock(phb); + *__msi_address = cpu_to_be32(msi_address); + *__message_data = cpu_to_be32(message_data); + return rc; } opal_call(OPAL_GET_MSI_32, opal_get_msi_32, 6); static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, uint8_t msi_range, - uint64_t *msi_address, uint32_t *message_data) + __be64 *__msi_address, __be32 *__message_data) { struct phb *phb = pci_get_phb(phb_id); + uint64_t msi_address; + uint32_t message_data; int64_t rc; - if (!opal_addr_valid(msi_address) || !opal_addr_valid(message_data)) + if (!opal_addr_valid(__msi_address) || !opal_addr_valid(__message_data)) return OPAL_PARAMETER; if (!phb) @@ -408,9 +446,12 @@ static int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, return OPAL_UNSUPPORTED; phb_lock(phb); rc = phb->ops->get_msi_64(phb, mve_number, xive_num, msi_range, - msi_address, message_data); + &msi_address, &message_data); phb_unlock(phb); + *__msi_address = cpu_to_be64(msi_address); + *__message_data = cpu_to_be32(message_data); + return rc; } opal_call(OPAL_GET_MSI_64, opal_get_msi_64, 6); @@ -820,14 +861,17 @@ static int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, } opal_call(OPAL_PCI_GET_PHB_DIAG_DATA2, opal_pci_get_phb_diag_data2, 3); -static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, - uint16_t *pci_error_type, uint16_t *severity) +static int64_t opal_pci_next_error(uint64_t phb_id, __be64 *__first_frozen_pe, + __be16 *__pci_error_type, __be16 *__severity) { struct phb *phb = pci_get_phb(phb_id); + uint64_t first_frozen_pe; + uint16_t pci_error_type; + uint16_t severity; int64_t rc; - if (!opal_addr_valid(first_frozen_pe) || - !opal_addr_valid(pci_error_type) || !opal_addr_valid(severity)) + if (!opal_addr_valid(__first_frozen_pe) || + !opal_addr_valid(__pci_error_type) || !opal_addr_valid(__severity)) return OPAL_PARAMETER; if (!phb) @@ -837,10 +881,14 @@ static int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, phb_lock(phb); opal_pci_eeh_clear_evt(phb_id); - rc = phb->ops->next_error(phb, first_frozen_pe, pci_error_type, - severity); + rc = phb->ops->next_error(phb, &first_frozen_pe, &pci_error_type, + &severity); phb_unlock(phb); + *__first_frozen_pe = cpu_to_be64(first_frozen_pe); + *__pci_error_type = cpu_to_be16(pci_error_type); + *__severity = cpu_to_be16(severity); + return rc; } opal_call(OPAL_PCI_NEXT_ERROR, opal_pci_next_error, 4); @@ -901,11 +949,12 @@ static int64_t opal_pci_set_p2p(uint64_t phbid_init, uint64_t phbid_target, } opal_call(OPAL_PCI_SET_P2P, opal_pci_set_p2p, 4); -static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) +static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, __be64 *__addr) { struct phb *phb = pci_get_phb(phb_id); + uint64_t addr; - if (!opal_addr_valid(addr)) + if (!opal_addr_valid(__addr)) return OPAL_PARAMETER; if (!phb) @@ -914,8 +963,11 @@ static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) return OPAL_UNSUPPORTED; phb_lock(phb); - phb->ops->get_tunnel_bar(phb, addr); + phb->ops->get_tunnel_bar(phb, &addr); phb_unlock(phb); + + *__addr = cpu_to_be64(addr); + return OPAL_SUCCESS; } opal_call(OPAL_PCI_GET_PBCQ_TUNNEL_BAR, opal_pci_get_pbcq_tunnel_bar, 2); diff --git a/core/powercap.c b/core/powercap.c index b9d172b54..de2a79095 100644 --- a/core/powercap.c +++ b/core/powercap.c @@ -7,13 +7,19 @@ #include -static int opal_get_powercap(u32 handle, int token __unused, u32 *pcap) +static int opal_get_powercap(u32 handle, int token __unused, __be32 *__pcap) { - if (!pcap || !opal_addr_valid(pcap)) + if (!__pcap || !opal_addr_valid(__pcap)) return OPAL_PARAMETER; - if (powercap_get_class(handle) == POWERCAP_CLASS_OCC) - return occ_get_powercap(handle, pcap); + if (powercap_get_class(handle) == POWERCAP_CLASS_OCC) { + u32 pcap; + int rc; + + rc = occ_get_powercap(handle, &pcap); + *__pcap = cpu_to_be32(pcap); + return rc; + } return OPAL_UNSUPPORTED; }; diff --git a/core/psr.c b/core/psr.c index 4cd3768ae..6698df8d2 100644 --- a/core/psr.c +++ b/core/psr.c @@ -10,13 +10,19 @@ #include static int opal_get_power_shift_ratio(u32 handle, int token __unused, - u32 *ratio) + __be32 *__ratio) { - if (!ratio || !opal_addr_valid(ratio)) + if (!__ratio || !opal_addr_valid(__ratio)) return OPAL_PARAMETER; - if (psr_get_class(handle) == PSR_CLASS_OCC) - return occ_get_psr(handle, ratio); + if (psr_get_class(handle) == PSR_CLASS_OCC) { + u32 ratio; + int rc; + + rc = occ_get_psr(handle, &ratio); + *__ratio = cpu_to_be32(ratio); + return rc; + } return OPAL_UNSUPPORTED; }; diff --git a/core/sensor.c b/core/sensor.c index a804f968a..c23f9b96e 100644 --- a/core/sensor.c +++ b/core/sensor.c @@ -21,11 +21,11 @@ static LIST_HEAD(async_read_list); struct sensor_async_read { struct list_node link; u64 *sensor_data64; - u32 *sensor_data32; + __be32 *sensor_data32; int token; }; -static int add_to_async_read_list(int token, u32 *data32, u64 *data64) +static int add_to_async_read_list(int token, __be32 *__data32, u64 *data64) { struct sensor_async_read *req; @@ -35,7 +35,7 @@ static int add_to_async_read_list(int token, u32 *data32, u64 *data64) req->token = token; req->sensor_data64 = data64; - req->sensor_data32 = data32; + req->sensor_data32 = __data32; lock(&async_read_list_lock); list_add_tail(&async_read_list, &req->link); @@ -59,7 +59,7 @@ void check_sensor_read(int token) if (!req) goto out; - *req->sensor_data32 = *req->sensor_data64; + *req->sensor_data32 = cpu_to_be32(*req->sensor_data64); free(req->sensor_data64); list_del(&req->link); free(req); @@ -67,25 +67,37 @@ out: unlock(&async_read_list_lock); } -static s64 opal_sensor_read_u64(u32 sensor_hndl, int token, u64 *sensor_data) +static s64 opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *__data) { + u64 data; + s64 rc; + switch (sensor_get_family(sensor_hndl)) { case SENSOR_DTS: - return dts_sensor_read(sensor_hndl, token, sensor_data); + rc = dts_sensor_read(sensor_hndl, token, &data); + *__data = cpu_to_be64(data); + return rc; + case SENSOR_OCC: - return occ_sensor_read(sensor_hndl, sensor_data); + rc = occ_sensor_read(sensor_hndl, &data); + *__data = cpu_to_be64(data); + return rc; + default: break; } - if (platform.sensor_read) - return platform.sensor_read(sensor_hndl, token, sensor_data); + if (platform.sensor_read) { + rc = platform.sensor_read(sensor_hndl, token, &data); + *__data = cpu_to_be64(data); + return rc; + } return OPAL_UNSUPPORTED; } static int64_t opal_sensor_read(uint32_t sensor_hndl, int token, - uint32_t *sensor_data) + __be32 *__data) { u64 *val; s64 ret; @@ -96,10 +108,10 @@ static int64_t opal_sensor_read(uint32_t sensor_hndl, int token, ret = opal_sensor_read_u64(sensor_hndl, token, val); if (!ret) { - *sensor_data = *val; + *__data = cpu_to_be32(*val); free(val); } else if (ret == OPAL_ASYNC_COMPLETION) { - ret = add_to_async_read_list(token, sensor_data, val); + ret = add_to_async_read_list(token, __data, val); } return ret; diff --git a/hw/fake-rtc.c b/hw/fake-rtc.c index 328be97d9..6f5411f2d 100644 --- a/hw/fake-rtc.c +++ b/hw/fake-rtc.c @@ -34,13 +34,15 @@ static int64_t fake_rtc_write(uint32_t ymd, uint64_t hmsm) return OPAL_SUCCESS; } -static int64_t fake_rtc_read(uint32_t *ymd, uint64_t *hmsm) +static int64_t fake_rtc_read(__be32 *__ymd, __be32 *__hmsm) { time_t sec; struct tm tm_calculated; + uint32_t ymd; + uint64_t hmsm; - if (!ymd || !hmsm) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; /* Compute the emulated clock value */ @@ -48,10 +50,13 @@ static int64_t fake_rtc_read(uint32_t *ymd, uint64_t *hmsm) sec = tb_to_secs(mftb() - tb_synctime) + mktime(&tm_offset); gmtime_r(&sec, &tm_calculated); - tm_to_datetime(&tm_calculated, ymd, hmsm); + tm_to_datetime(&tm_calculated, &ymd, &hmsm); unlock(&emulation_lock); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); + return OPAL_SUCCESS; } diff --git a/hw/fsp/fsp-console.c b/hw/fsp/fsp-console.c index 42fb98806..837eab5fd 100644 --- a/hw/fsp/fsp-console.c +++ b/hw/fsp/fsp-console.c @@ -579,7 +579,7 @@ void fsp_console_preinit(void) } -static int64_t fsp_console_write(int64_t term_number, int64_t *length, +static int64_t fsp_console_write(int64_t term_number, __be64 *__length, const uint8_t *buffer) { struct fsp_serial *fs; @@ -596,7 +596,7 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, return OPAL_CLOSED; } /* Clamp to a reasonable size */ - requested = *length; + requested = be64_to_cpu(*__length); if (requested > 0x1000) requested = 0x1000; written = fsp_write_vserial(fs, buffer, requested); @@ -618,7 +618,7 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, buffer[6], buffer[6], buffer[7], buffer[7]); #endif /* OPAL_DEBUG_CONSOLE_IO */ - *length = written; + *__length = cpu_to_be64(written); unlock(&fsp_con_lock); if (written) @@ -628,11 +628,12 @@ static int64_t fsp_console_write(int64_t term_number, int64_t *length, } static int64_t fsp_console_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *__length) { static bool elog_generated = false; struct fsp_serial *fs; struct fsp_serbuf_hdr *sb; + int64_t length; if (term_number < 0 || term_number >= MAX_SERIAL) return OPAL_PARAMETER; @@ -645,15 +646,16 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, return OPAL_CLOSED; } sb = fs->out_buf; - *length = (sb->next_out + SER_BUF_DATA_SIZE - sb->next_in - 1) + length = (sb->next_out + SER_BUF_DATA_SIZE - sb->next_in - 1) % SER_BUF_DATA_SIZE; unlock(&fsp_con_lock); /* Console buffer has enough space to write incoming data */ - if (*length != fs->out_buf_prev_len) { - fs->out_buf_prev_len = *length; + if (length != fs->out_buf_prev_len) { + fs->out_buf_prev_len = length; fs->out_buf_timeout = 0; + *__length = cpu_to_be64(length); return OPAL_SUCCESS; } @@ -667,8 +669,10 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, secs_to_tb(SER_BUFFER_OUT_TIMEOUT); } - if (tb_compare(mftb(), fs->out_buf_timeout) != TB_AAFTERB) + if (tb_compare(mftb(), fs->out_buf_timeout) != TB_AAFTERB) { + *__length = cpu_to_be64(length); return OPAL_SUCCESS; + } /* * FSP is still active but not reading console data. Hence @@ -686,13 +690,13 @@ static int64_t fsp_console_write_buffer_space(int64_t term_number, return OPAL_RESOURCE; } -static int64_t fsp_console_read(int64_t term_number, int64_t *length, +static int64_t fsp_console_read(int64_t term_number, __be64 *__length, uint8_t *buffer) { struct fsp_serial *fs; struct fsp_serbuf_hdr *sb; bool pending = false; - uint32_t old_nin, n, i, chunk, req = *length; + uint32_t old_nin, n, i, chunk, req = be64_to_cpu(*__length); int rc = OPAL_SUCCESS; if (term_number < 0 || term_number >= MAX_SERIAL) @@ -716,7 +720,7 @@ static int64_t fsp_console_read(int64_t term_number, int64_t *length, pending = true; n = req; } - *length = n; + *__length = cpu_to_be64(n); chunk = SER_BUF_DATA_SIZE - sb->next_out; if (chunk > n) diff --git a/hw/fsp/fsp-rtc.c b/hw/fsp/fsp-rtc.c index 53838f87c..1d98d8305 100644 --- a/hw/fsp/fsp-rtc.c +++ b/hw/fsp/fsp-rtc.c @@ -249,12 +249,14 @@ static int64_t fsp_rtc_send_read_request(void) return OPAL_BUSY_EVENT; } -static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, - uint64_t *hour_minute_second_millisecond) +static int64_t fsp_opal_rtc_read(uint32_t *__ymd, + uint64_t *__hmsm) { int64_t rc; + uint32_t ymd; + uint64_t hmsm; - if (!year_month_day || !hour_minute_second_millisecond) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; lock(&rtc_lock); @@ -267,8 +269,7 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, /* During R/R of FSP, read cached TOD */ if (fsp_in_rr()) { if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -290,11 +291,9 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, opal_rtc_eval_events(true); if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); prlog(PR_TRACE,"FSP-RTC Cached datetime: %x %llx\n", - *year_month_day, - *hour_minute_second_millisecond); + ymd, hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -306,8 +305,7 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, prlog(PR_TRACE, "RTC read timed out\n"); if (rtc_tod_state == RTC_TOD_VALID) { - rtc_cache_get_datetime(year_month_day, - hour_minute_second_millisecond); + rtc_cache_get_datetime(&ymd, &hmsm); rc = OPAL_SUCCESS; } else { rc = OPAL_INTERNAL_ERROR; @@ -319,6 +317,12 @@ static int64_t fsp_opal_rtc_read(uint32_t *year_month_day, } out: unlock(&rtc_lock); + + if (rc == OPAL_SUCCESS) { + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); + } + return rc; } diff --git a/hw/ipmi/ipmi-rtc.c b/hw/ipmi/ipmi-rtc.c index deb4addcb..d236d1f04 100644 --- a/hw/ipmi/ipmi-rtc.c +++ b/hw/ipmi/ipmi-rtc.c @@ -62,12 +62,14 @@ static int64_t ipmi_set_sel_time(uint32_t _tv) return ipmi_queue_msg(msg); } -static int64_t ipmi_opal_rtc_read(uint32_t *y_m_d, - uint64_t *h_m_s_m) +static int64_t ipmi_opal_rtc_read(uint32_t *__ymd, + uint64_t *__hmsm) { int ret = 0; + uint32_t ymd; + uint64_t hmsm; - if (!y_m_d || !h_m_s_m) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; switch(time_status) { @@ -83,7 +85,9 @@ static int64_t ipmi_opal_rtc_read(uint32_t *y_m_d, break; case updated: - rtc_cache_get_datetime(y_m_d, h_m_s_m); + rtc_cache_get_datetime(&ymd, &hmsm); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); time_status = idle; ret = OPAL_SUCCESS; break; diff --git a/hw/lpc-rtc.c b/hw/lpc-rtc.c index f560c8c9f..53cffba8f 100644 --- a/hw/lpc-rtc.c +++ b/hw/lpc-rtc.c @@ -139,14 +139,16 @@ static void lpc_init_hw(void) unlock(&rtc_lock); } -static int64_t lpc_opal_rtc_read(uint32_t *y_m_d, - uint64_t *h_m_s_m) +static int64_t lpc_opal_rtc_read(uint32_t *__ymd, + uint64_t *__hmsm) { uint8_t val; int64_t rc = OPAL_SUCCESS; struct tm tm; + uint32_t ymd; + uint64_t hmsm; - if (!y_m_d || !h_m_s_m) + if (!__ymd || !__hmsm) return OPAL_PARAMETER; /* Return busy if updating. This is somewhat racy, but will @@ -172,7 +174,9 @@ static int64_t lpc_opal_rtc_read(uint32_t *y_m_d, rtc_cache_update(&tm); /* Convert to OPAL time */ - tm_to_datetime(&tm, y_m_d, h_m_s_m); + tm_to_datetime(&tm, &ymd, &hmsm); + *__ymd = cpu_to_be32(ymd); + *__hmsm = cpu_to_be64(hmsm); } return rc; diff --git a/hw/lpc-uart.c b/hw/lpc-uart.c index feca229b6..b37e04201 100644 --- a/hw/lpc-uart.c +++ b/hw/lpc-uart.c @@ -255,10 +255,10 @@ static uint32_t uart_tx_buf_space(void) (out_buf_prod + OUT_BUF_SIZE - out_buf_cons) % OUT_BUF_SIZE; } -static int64_t uart_opal_write(int64_t term_number, int64_t *length, +static int64_t uart_opal_write(int64_t term_number, __be64 *__length, const uint8_t *buffer) { - size_t written = 0, len = *length; + size_t written = 0, len = be64_to_cpu(*__length); if (term_number != 0) return OPAL_PARAMETER; @@ -277,19 +277,19 @@ static int64_t uart_opal_write(int64_t term_number, int64_t *length, unlock(&uart_lock); - *length = written; + *__length = cpu_to_be64(written); return OPAL_SUCCESS; } static int64_t uart_opal_write_buffer_space(int64_t term_number, - int64_t *length) + __be64 *__length) { if (term_number != 0) return OPAL_PARAMETER; lock(&uart_lock); - *length = uart_tx_buf_space(); + *__length = cpu_to_be64(uart_tx_buf_space()); unlock(&uart_lock); return OPAL_SUCCESS; @@ -326,10 +326,10 @@ static void uart_adjust_opal_event(void) } /* This is called with the console lock held */ -static int64_t uart_opal_read(int64_t term_number, int64_t *length, +static int64_t uart_opal_read(int64_t term_number, __be64 *__length, uint8_t *buffer) { - size_t req_count = *length, read_cnt = 0; + size_t req_count = be64_to_cpu(*__length), read_cnt = 0; uint8_t lsr = 0; if (term_number != 0) @@ -373,7 +373,7 @@ static int64_t uart_opal_read(int64_t term_number, int64_t *length, /* Adjust the OPAL event */ uart_adjust_opal_event(); - *length = read_cnt; + *__length = cpu_to_be64(read_cnt); return OPAL_SUCCESS; } diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 9a391bb01..10d61484e 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -2167,10 +2167,12 @@ out: } static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, - uint64_t size, uint64_t *bar) + uint64_t size, __be64 *__bar) { struct phb *phb = pci_get_phb(phb_id); struct npu2_dev *dev; + uint64_t bar; + int64_t rc; if (!phb || phb->phb_type != phb_type_npu_v2_opencapi) @@ -2180,10 +2182,14 @@ static int64_t opal_npu_mem_alloc(uint64_t phb_id, uint32_t __unused bdfn, if (!dev) return OPAL_PARAMETER; - if (!opal_addr_valid(bar)) + if (!opal_addr_valid(__bar)) return OPAL_PARAMETER; - return alloc_mem_bar(dev, size, bar); + rc = alloc_mem_bar(dev, size, &bar); + if (rc == OPAL_SUCCESS) + *__bar = cpu_to_be64(bar); + + return rc; } opal_call(OPAL_NPU_MEM_ALLOC, opal_npu_mem_alloc, 4); diff --git a/hw/xscom.c b/hw/xscom.c index 9b28422d2..38ec72199 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -639,7 +639,17 @@ int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_loc return rc; } -opal_call(OPAL_XSCOM_READ, xscom_read, 3); +static int64_t opal_xscom_read(uint32_t partid, uint64_t pcb_addr, __be64 *__val) +{ + uint64_t val; + int64_t rc; + + rc = xscom_read(partid, pcb_addr, &val); + *__val = cpu_to_be64(val); + + return rc; +} +opal_call(OPAL_XSCOM_READ, opal_xscom_read, 3); int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_lock) { @@ -683,7 +693,12 @@ int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_loc unlock(&xscom_lock); return rc; } -opal_call(OPAL_XSCOM_WRITE, xscom_write, 3); + +static int64_t opal_xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) +{ + return xscom_write(partid, pcb_addr, val); +} +opal_call(OPAL_XSCOM_WRITE, opal_xscom_write, 3); /* * Perform a xscom read-modify-write. diff --git a/include/console.h b/include/console.h index 26602b7ac..230b825b0 100644 --- a/include/console.h +++ b/include/console.h @@ -47,13 +47,13 @@ struct opal_con_ops { */ void (*init)(void); - int64_t (*write)(int64_t term, int64_t *len, const uint8_t *buf); - int64_t (*read)(int64_t term, int64_t *len, uint8_t *buf); + int64_t (*write)(int64_t term, __be64 *__len, const uint8_t *buf); + int64_t (*read)(int64_t term, __be64 *__len, uint8_t *buf); /* * returns the amount of space available in the console write buffer */ - int64_t (*space)(int64_t term_number, int64_t *length); + int64_t (*space)(int64_t term_number, __be64 *__length); /* * Forces the write buffer to be flushed by the driver diff --git a/platforms/mambo/mambo.c b/platforms/mambo/mambo.c index e523cd3eb..f33b72d20 100644 --- a/platforms/mambo/mambo.c +++ b/platforms/mambo/mambo.c @@ -178,6 +178,8 @@ static int64_t mambo_rtc_read(uint32_t *ymd, uint64_t *hmsm) int64_t mambo_time; struct tm t; time_t mt; + uint32_t __ymd; + uint64_t __hmsm; if (!ymd || !hmsm) return OPAL_PARAMETER; @@ -185,7 +187,10 @@ static int64_t mambo_rtc_read(uint32_t *ymd, uint64_t *hmsm) mambo_time = callthru0(SIM_GET_TIME_CODE); mt = mambo_time >> 32; gmtime_r(&mt, &t); - tm_to_datetime(&t, ymd, hmsm); + tm_to_datetime(&t, &__ymd, &__hmsm); + + *ymd = cpu_to_be32(__ymd); + *hmsm = cpu_to_be64(__hmsm); return OPAL_SUCCESS; } From patchwork Wed Oct 9 23:49:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174204 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWL81J0cz9sCJ for ; Thu, 10 Oct 2019 10:55:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PH8UimMD"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWL76j58zDqY5 for ; Thu, 10 Oct 2019 10:55:11 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PH8UimMD"; dkim-atps=neutral Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHp0C7QzDqZG for ; Thu, 10 Oct 2019 10:53:09 +1100 (AEDT) Received: by mail-pl1-x641.google.com with SMTP id d22so1833984pll.7 for ; Wed, 09 Oct 2019 16:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xGJWtefjtVg+5fW4bAT8rsCUiIz7tCfA6hN0l1f1VCU=; b=PH8UimMDxYThEW+hDLOSRZjQJTonBzTXuS8hUDSJaY1D0wpk4L+Q2/uknjmzkt3CP7 YuR+npRtWHFb5w6MU8xR0nJO3Tef1Yqlow2oBr65ogNXQHgQxSV+Koqy9A7SRE/MOxEm 6ULqlYUJap0urA0ahN7rcCRqcjpvOz7j9q7fxY1ng5TnUCR8QW490nSrd5p3kZdukI+Q uwZHPTymuukuvqafKH8I3PX4mFCGWASKEiXm5WAt5hv/8ZOQkHrYqj+LNacWCvX3VqsT J0L+EswT1fkqHv5QbTmbPwHYTKmrqStJD5L0xfrvFrtBI4wITPEDZZ3/jFTmuZYRQVCG O+hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xGJWtefjtVg+5fW4bAT8rsCUiIz7tCfA6hN0l1f1VCU=; b=djRu9Of/xjeIVgkW13pz16ECNcEz8aGXMlmS45RSnaKxPW9a4S8INWTyVLMXMOzFSF yetjYuo0LzfyqzaFvY1AETFp5S78tx/yrdpfACd40VEYb3rzJv9umRVV/fm4Gg0MEdVK tzbAuxBYBJbC258sgS4vjrL/eL3VrazQb4lAaZ7rPve/R8bD0RBwU05gaHrlsHZZ5vC9 uaRSOyKtVjjp26uodoZ6xRzFovwJClHZ8LL8luAwL6TVXYeMcUHrY6XSZa32Y9f8QJZH 1Pcdv5YsKg35eH8Upwq0lsFXVsdGutDkSEB5X9OHAIiOO21rI0WS4O9FKDTv1+jB1+aV xwdQ== X-Gm-Message-State: APjAAAUoOJC41UGo8Hm3n1ytUERF/8EAkDxS5UQAPgtHB97WGlQHOQ40 Tbn4lFeaMlzTUxUefgpbOPVskS3O X-Google-Smtp-Source: APXvYqyTk7xbFcJ25TZ1Tg9LDTvVQRT7TXxrEuccJEGc1+PAaxEXd5JSeRTTAJBEhhMG9+j2ZfDtvQ== X-Received: by 2002:a17:902:563:: with SMTP id 90mr5560439plf.13.1570665187535; Wed, 09 Oct 2019 16:53:07 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:07 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:42 +1000 Message-Id: <20191009234951.2850-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 06/15] spira: fix endian conversions in spira data structures X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Labels can't be used for static initialisers that require endian conversion. Use constants for these. Signed-off-by: Nicholas Piggin --- hdata/spira.c | 53 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/hdata/spira.c b/hdata/spira.c index 5e73b7d44..9c9d06167 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -37,37 +37,57 @@ __section(".procin.data") struct proc_init_data proc_init_data = { }, }; +extern struct cpu_ctl_init_data cpu_ctl_init_data; extern struct sp_addr_table cpu_ctl_spat_area; -__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area; -__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1; -__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2; +extern struct sp_attn_area cpu_ctl_sp_attn_area1; +extern struct sp_attn_area cpu_ctl_sp_attn_area2; extern struct hsr_data_area cpu_ctl_hsr_area; + +/* + * cpuctrl.data begins at CPU_CTL_OFF - cpu_ctl_init_data is located there. + * + sizeof(struct cpu_ctl_init_data) - cpu_ctl_spat_area + * + sizeof(struct sp_addr_table) - cpu_ctl_sp_attn_area1 + * + sizeof(struct sp_attn_area) - cpu_ctl_sp_attn_area2 + * + sizeof(struct sp_attn_area) - cpu_ctl_hsr_area + * + * Can't use CPU_TO_BE64 directly on the labels as a constant initialiser. + * + * CPU_CTL_INIT_DATA_OFF is offset from 0, the others are addressed from the + * relocated address (+SKIBOOT_BASE) + */ +#define CPU_CTL_INIT_DATA_OFF (CPU_CTL_OFF) +#define CPU_CTL_SPAT_AREA_OFF (CPU_CTL_INIT_DATA_OFF + sizeof(struct cpu_ctl_init_data) + SKIBOOT_BASE) +#define CPU_CTL_SP_ATTN_AREA1_OFF (CPU_CTL_SPAT_AREA_OFF + sizeof(struct sp_addr_table)) +#define CPU_CTL_SP_ATTN_AREA2_OFF (CPU_CTL_SP_ATTN_AREA1_OFF + sizeof(struct sp_attn_area)) +#define CPU_CTL_HSR_AREA_OFF (CPU_CTL_SP_ATTN_AREA2_OFF + sizeof(struct sp_attn_area)) + __section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1; +__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area; -extern struct cpu_ctl_init_data cpu_ctl_init_data; __section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = { .hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data), - .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), sizeof(struct cpu_ctl_legacy_table)), -#if !defined(TEST) + .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), + sizeof(struct cpu_ctl_legacy_table)), .cpu_ctl_lt = { .spat = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_spat_area) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SPAT_AREA_OFF), .size = CPU_TO_BE64(sizeof(struct sp_addr_table)), }, .sp_attn_area1 = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area1) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA1_OFF), .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), }, .sp_attn_area2 = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_sp_attn_area2) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA2_OFF), .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), }, .hsr_area = { - .addr = CPU_TO_BE64((unsigned long)&(cpu_ctl_hsr_area) + SKIBOOT_BASE), + .addr = CPU_TO_BE64(CPU_CTL_HSR_AREA_OFF), .size = CPU_TO_BE64(sizeof(struct hsr_data_area)), }, }, -#endif }; /* Populate MDST table @@ -131,15 +151,12 @@ __section(".spira.data") struct spira spira = { .alloc_len = CPU_TO_BE32(sizeof(init_mdst_table)), }, -#if !defined(TEST) .cpu_ctrl = { - .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data), + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), .alloc_cnt = CPU_TO_BE16(1), .act_cnt = CPU_TO_BE16(1), - .alloc_len = - CPU_TO_BE32(sizeof(cpu_ctl_init_data)), + .alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)), }, -#endif }, }; @@ -170,15 +187,13 @@ __section(".spirah.data") struct spirah spirah = { .alloc_len = CPU_TO_BE32(sizeof(struct proc_init_data)), }, -#if !defined(TEST) .cpu_ctrl = { - .addr = CPU_TO_BE64((unsigned long)&cpu_ctl_init_data), + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), .alloc_cnt = CPU_TO_BE16(1), .act_cnt = CPU_TO_BE16(1), .alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)), }, -#endif .mdump_src = { .addr = CPU_TO_BE64(MDST_TABLE_OFF), .alloc_cnt = CPU_TO_BE16(MDST_TABLE_SIZE / sizeof(struct mdst_table)), From patchwork Wed Oct 9 23:49:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWLX1CdNz9s7T for ; Thu, 10 Oct 2019 10:55:32 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Aw6HJ9Dx"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWLX0DlwzDqZH for ; Thu, 10 Oct 2019 10:55:32 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Aw6HJ9Dx"; dkim-atps=neutral Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHs1LP1zDqZb for ; Thu, 10 Oct 2019 10:53:13 +1100 (AEDT) Received: by mail-pf1-x442.google.com with SMTP id 205so2672796pfw.2 for ; Wed, 09 Oct 2019 16:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8dftLLukIhh46QHFZdTqJJ1Y/j+pzaRRdpsOUB44MDc=; b=Aw6HJ9DxF6IhdvOOpde+/AHfYZfMas4FZ0/Uq78dnSN0JKDEGoV7knxTmepw9GUERJ +1C4OS5CvpkzifKeULBya0Hh+2YOMmPbkiHSuVAyU0lX1EgQet4usvvn42Wfq1FPua0K K8UxtbzqSUYAqYRZ/oWjYC1Yi1lh2gKafcHVQQ0GvJC6XPxAE0rSHXONnk7sZjCLPjpX aWmS0BM0FPSX67OX/EGZ+rMz6uzCNuxQ16LgJLm3YRhPgMafQLlYdI88RWusq+m7BFw3 QAxqnsy76y7ZFMslTduSDmF8DULWZWMDJjHRdmULnmCB3WSNfVvnDP9UJKkf73j47Gb2 +8ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8dftLLukIhh46QHFZdTqJJ1Y/j+pzaRRdpsOUB44MDc=; b=jtxKf9TVyjwcC7PmSjHlfd9LzMrplsEeRWE0+Bah7iAET/66YZ8U4X7cLuJ1jZj8oD ZX3rhEZX3cFw81j0LdEwYU2j1rsPG4bUt4XTMbctKJ/n6sdvhFg074itn/eOHA1QEaT0 s4xmzxjG5qisUE/KbTkS25HA3Dwe2VYHE8gqtpOz2kYOgDz/PHPQOgSwxAcvOlwvwqrN 8X7GHOaKKB5PL8qWSPxF+sjdUBSBJFPy30FyvIn1mZ0CG8EoOzmWLifRLy2qKtjKSEoz 2orzvcD9U0V+Uad/cXZsWCkzthB9KLnehCOe2zIyvjUHH60Sk5+oZOXm1Z8VnKaOBT2j ZxRQ== X-Gm-Message-State: APjAAAWwoAikuwoUuYnJxIQ9M8SshGcOlo2VWFbiEG6/NbpnhkQAfxzg uUQIsMZCUfx4fHPbCVwlTd7l1pGg X-Google-Smtp-Source: APXvYqzkHBfEf7k0k+RuJwYF5QcBP/kQS8+p9tXxmB+Ya13a2ptD4OMUDxmpRtUVMO2BHluen/ihog== X-Received: by 2002:a65:6910:: with SMTP id s16mr7166605pgq.284.1570665189512; Wed, 09 Oct 2019 16:53:09 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:09 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:43 +1000 Message-Id: <20191009234951.2850-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 07/15] fixup_spira remove incorrect endian conversion X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hdata/memory.c | 3 ++- hdata/spira.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index 9af7ae71d..9e5e99b9c 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -135,7 +135,8 @@ static bool add_address_range(struct dt_node *root, "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", (long long)be64_to_cpu(arange->start), (long long)be64_to_cpu(arange->end), - chip_id, arange->mirror_attr, mem_type, mem_status); + chip_id, be32_to_cpu(arange->mirror_attr), + mem_type, mem_status); /* reg contains start and length */ reg[0] = cleanup_addr(be64_to_cpu(arange->start)); diff --git a/hdata/spira.c b/hdata/spira.c index 9c9d06167..9e3f83a3c 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1663,7 +1663,7 @@ static void add_npus(void) static void fixup_spira(void) { #if !defined(TEST) - spiras = (struct spiras *)CPU_TO_BE64(SPIRA_HEAP_BASE); + spiras = (struct spiras *)SPIRA_HEAP_BASE; #endif /* Validate SPIRA-S signature */ From patchwork Wed Oct 9 23:49:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWLv0Zzvz9s7T for ; Thu, 10 Oct 2019 10:55:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S+QGZZfm"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWLt6XJPzDqYd for ; Thu, 10 Oct 2019 10:55:50 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S+QGZZfm"; dkim-atps=neutral Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHt1lBGzDqZB for ; Thu, 10 Oct 2019 10:53:14 +1100 (AEDT) Received: by mail-pg1-x541.google.com with SMTP id b8so2425721pgm.13 for ; Wed, 09 Oct 2019 16:53:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IhJz7B4uoILze2RMsx76OF2o6GFSRPe8nTWZuFtMwbk=; b=S+QGZZfmqUx5R4oD5xJGNynMVHsnLba6k84Pc+GZZKsYogtbHbiloYTNdxXU1LU5W6 q5w7gGSbR0gE0Q37QdLZU08QsyGJVQUvD6qTkWy8x9dcFbxGfu9PeRxlndraAGhl01p8 6Kw56EoFNKYBsuH9rV1Ec8ggXTpAYhaAW0LgVWG5xv6mLv0eOowqc2IEBtWUGsyWiQvH PZi7kc0+eLzFajEXeneqs4GiAfpi7LD6wwqYmimEUExDhtGvvr6mcFIBEtUrQBIq7jLz vuE2bxUN9ghlDRKoGm5T4VVL2z/4LKKCu0awgO2VO60wQi9Pgh/VrR+5GxwVj9ZD4TCk WYYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IhJz7B4uoILze2RMsx76OF2o6GFSRPe8nTWZuFtMwbk=; b=nMTz3RfGOVEHrzfVL1pewtlNXqDZGtyv4fiOptIGOIRBKgTWHxpGp4asbmEuPZ6Znx 7A8SrrEVN5VTjW8K+Gx3sQN09xRb5JFeBAIhanlCjDDBBSNt3hm8EMMtxTL0meT5pmqR auNoZKGjjMbgo4Ja9hAKD8pAubNb0hKtG7IZIGZw+cqznULPN/oqC8l305/hZN7Xit1C AA7vD9heRtQ4MJIY55+fsSKtO+1Levpx9Y/o0rNa+RxOkZeupQmWzKm9rN7YbmFSfs9/ 3pCr++kjfi0ENJKNNcHpWnGKbARMcVjPVD1yxd7zZAeA7p5EK6+B/an1JPIEFls1jeXK UC0Q== X-Gm-Message-State: APjAAAXlDujmoR20JaWWKFPD8zMu72U30kAxEw/uMoEytz5aMGdoDhML u/8/5ci2EMAW94VUgdrD7Yas59bV X-Google-Smtp-Source: APXvYqwgI50sTl8DPOT5xAp/ueyYeGt4Y3EVMQWz7D4FHca3TDdg5Ip08UliPwqjTr7v5CfltRoUqg== X-Received: by 2002:a17:90a:fc82:: with SMTP id ci2mr6993337pjb.13.1570665191440; Wed, 09 Oct 2019 16:53:11 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:11 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:44 +1000 Message-Id: <20191009234951.2850-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 08/15] naca: move naca definition from asm to C X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This results in the same layout and location of the naca and hv data structures. Signed-off-by: Nicholas Piggin --- asm/asm-offsets.c | 2 -- asm/head.S | 50 ------------------------------------------ hdata/Makefile.inc | 2 +- hdata/hdata.h | 2 ++ hdata/naca.c | 26 ++++++++++++++++++++++ hdata/naca.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++ hdata/spira.c | 11 ++++------ hdata/spira.h | 2 ++ include/mem-map.h | 2 ++ skiboot.lds.S | 5 +++++ 10 files changed, 96 insertions(+), 60 deletions(-) create mode 100644 hdata/naca.c create mode 100644 hdata/naca.h diff --git a/asm/asm-offsets.c b/asm/asm-offsets.c index e4584059c..61a25cab3 100644 --- a/asm/asm-offsets.c +++ b/asm/asm-offsets.c @@ -25,8 +25,6 @@ int main(void); int main(void) { - OFFSET(SPIRA_ACTUAL_SIZE, spira, reserved); - OFFSET(CPUTHREAD_PIR, cpu_thread, pir); OFFSET(CPUTHREAD_SAVE_R1, cpu_thread, save_r1); OFFSET(CPUTHREAD_STATE, cpu_thread, state); diff --git a/asm/head.S b/asm/head.S index 426b5d5c1..7ce3c7c97 100644 --- a/asm/head.S +++ b/asm/head.S @@ -806,56 +806,6 @@ enter_nap: bne 1b nap b . -/* - * - * NACA structure, accessed by the FPS to find the SPIRA - * - */ - . = 0x4000 -.global naca -naca: - .llong spirah /* 0x0000 : SPIRA-H */ - .llong 0 /* 0x0008 : Reserved */ - .llong 0 /* 0x0010 : Reserved */ - .llong hv_release_data /* 0x0018 : HV release data */ - .llong 0 /* 0x0020 : Reserved */ - .llong 0 /* 0x0028 : Reserved */ - .llong spira /* 0x0030 : SP Interface Root */ - .llong hv_lid_load_table /* 0x0038 : LID load table */ - .llong 0 /* 0x0040 : Reserved */ - .space 68 - .long 0 /* 0x008c : Reserved */ - .space 16 - .long SPIRA_ACTUAL_SIZE /* 0x00a0 : Actual size of SPIRA */ - .space 28 - .llong 0 /* 0x00c0 : resident module loadmap */ - .space 136 - .llong 0 /* 0x0150 : reserved */ - .space 40 - .llong 0 /* 0x0180 : reserved */ - .space 36 - .long 0 /* 0x01ac : control flags */ - .byte 0 /* 0x01b0 : reserved */ - .space 4 - .byte 0 /* 0x01b5 : default state for SW attn */ - .space 1 - .byte 0x01 /* 0x01b7 : PCIA format */ - .llong hdat_entry /* 0x01b8 : Primary thread entry */ - .llong hdat_entry /* 0x01c0 : Secondary thread entry */ - .space 0xe38 - - .balign 0x10 -hv_release_data: - .space 58 - .llong 0x666 /* VRM ? */ - - .balign 0x10 -hv_lid_load_table: - .long 0x10 - .long 0x10 - .long 0 - .long 0 - /* * diff --git a/hdata/Makefile.inc b/hdata/Makefile.inc index 6f47314d4..67f809bc1 100644 --- a/hdata/Makefile.inc +++ b/hdata/Makefile.inc @@ -1,7 +1,7 @@ # -*-Makefile-*- SUBDIRS += hdata -HDATA_OBJS = spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o +HDATA_OBJS = naca.o spira.o paca.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o HDATA_OBJS += cpu-common.o vpd-common.o hostservices.o i2c.o tpmrel.o DEVSRC_OBJ = hdata/built-in.a diff --git a/hdata/hdata.h b/hdata/hdata.h index f77847172..da5146e7a 100644 --- a/hdata/hdata.h +++ b/hdata/hdata.h @@ -5,6 +5,8 @@ #define __HDATA_H #include +#include "hdif.h" +#include "spira.h" struct dt_node; diff --git a/hdata/naca.c b/hdata/naca.c new file mode 100644 index 000000000..b98df8a5a --- /dev/null +++ b/hdata/naca.c @@ -0,0 +1,26 @@ +#include +#include +#include + +#include "naca.h" +#include "spira.h" + +__section(".naca.data") struct naca naca = { + .spirah_addr = CPU_TO_BE64(SPIRAH_OFF), + .hv_release_data_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_release_data)), + .spira_addr = CPU_TO_BE64(SPIRA_OFF), + .lid_table_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_lid_load_table)), + .spira_size = CPU_TO_BE32(SPIRA_ACTUAL_SIZE), + .hv_load_map_addr = 0, + .attn_enabled = 0, + .pcia_supported = 1, + .__primary_thread_entry = CPU_TO_BE64(0x180), + .__secondary_thread_entry = CPU_TO_BE64(0x180), + .hv_release_data = { + .vrm = CPU_TO_BE32(0x666), /* ? */ + }, + .hv_lid_load_table = { + .w0 = CPU_TO_BE32(0x10), + .w1 = CPU_TO_BE32(0x10), + }, +}; diff --git a/hdata/naca.h b/hdata/naca.h new file mode 100644 index 000000000..1271b59a5 --- /dev/null +++ b/hdata/naca.h @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2019 IBM Corp. */ + +#ifndef __NACA_H +#define __NACA_H + +#include +#include +#include + +struct hv_release_data { + uint8_t reserved_0x0[58]; + __be64 vrm; +} __packed __attribute__((aligned(0x10))); + +struct hv_lid_load_table { + __be32 w0; + __be32 w1; + __be32 w2; + __be32 w3; +} __packed __attribute__((aligned(0x10))); + +/* + * NACA structure, accessed by the FSP to find the SPIRA + */ +struct naca { + __be64 spirah_addr; /* 0x0000 */ + uint8_t reserved_0x8[0x10]; + __be64 hv_release_data_addr; /* 0x0018 */ + uint8_t reserved_0x20[0x10]; + __be64 spira_addr; /* 0x0030 */ + __be64 lid_table_addr; /* 0x0038 */ + uint8_t reserved_0x40[0x60]; + __be32 spira_size; /* 0x00a0 */ + uint8_t reserved_0xa4[0x1c]; + __be64 hv_load_map_addr; /* 0x00c0 */ + uint8_t reserved_0xc8[0xe4]; + uint8_t flags[4]; /* 0x01ac */ + uint8_t reserved_0x1b0[0x5]; + uint8_t attn_enabled; /* 0x01b5 */ + uint8_t reserved_0x1b6[0x1]; + uint8_t pcia_supported; /* 0x01b7 */ + __be64 __primary_thread_entry; /* 0x01b8 */ + __be64 __secondary_thread_entry; /* 0x01c0 */ + uint8_t reserved_0x1d0[0xe38]; + + /* Not part of the naca but it's convenient to put them here */ + struct hv_release_data hv_release_data; + struct hv_lid_load_table hv_lid_load_table; +} __packed __attribute((aligned(0x10))); + +extern struct naca naca; + +#endif diff --git a/hdata/spira.c b/hdata/spira.c index 9e3f83a3c..0d17ae05e 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -3,7 +3,6 @@ #include #include -#include "spira.h" #include #include #include @@ -15,6 +14,8 @@ #include "hdata.h" #include "hostservices.h" +#include "naca.h" +#include "spira.h" /* Processor Initialization structure, contains * the initial NIA and MSR values for the entry @@ -1706,15 +1707,11 @@ static void fixup_spira(void) static void update_spirah_addr(void) { #if !defined(TEST) - extern uint32_t naca; - uint64_t *spirah_offset = (uint64_t *)&naca; - uint64_t *spira_offset = (uint64_t *)((u64)(&naca) + 0x30); - if (proc_gen < proc_gen_p9) return; - *spirah_offset = SPIRAH_OFF; - *spira_offset = SPIRA_OFF; + naca.spirah_addr = CPU_TO_BE64(SPIRAH_OFF); + naca.spira_addr = CPU_TO_BE64(SPIRA_OFF); spirah.ntuples.hs_data_area.addr = CPU_TO_BE64(SPIRA_HEAP_BASE - SKIBOOT_BASE); spirah.ntuples.mdump_res.addr = CPU_TO_BE64(MDRT_TABLE_BASE - SKIBOOT_BASE); #endif diff --git a/hdata/spira.h b/hdata/spira.h index eb5d1ea1b..14fbc5f59 100644 --- a/hdata/spira.h +++ b/hdata/spira.h @@ -80,6 +80,8 @@ struct spira { u8 reserved[0x60]; } __packed __align(0x100); +#define SPIRA_ACTUAL_SIZE (sizeof(struct spira) - 0x60) + extern struct spira spira; /* SPIRA-H signature */ diff --git a/include/mem-map.h b/include/mem-map.h index 991465190..90529df22 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -21,6 +21,8 @@ */ #define EXCEPTION_VECTORS_END 0x2000 +#define NACA_OFF 0x4000 + /* The NACA and other stuff in head.S need to be at the start: we * give it 64k before placing the SPIRA and related data. */ diff --git a/skiboot.lds.S b/skiboot.lds.S index 8890d69aa..3f90c25eb 100644 --- a/skiboot.lds.S +++ b/skiboot.lds.S @@ -59,6 +59,11 @@ SECTIONS KEEP(*(.head)) } + . = NACA_OFF; + .naca : { + KEEP(*(.naca.data)) + } + . = SPIRA_OFF; .spira : { KEEP(*(.spira.data)) From patchwork Wed Oct 9 23:49:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174207 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWM94LSYz9s7T for ; Thu, 10 Oct 2019 10:56:05 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="scMasMGp"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWM92pgNzDqYn for ; Thu, 10 Oct 2019 10:56:05 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::534; helo=mail-pg1-x534.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="scMasMGp"; dkim-atps=neutral Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHv6R0MzDqYd for ; Thu, 10 Oct 2019 10:53:15 +1100 (AEDT) Received: by mail-pg1-x534.google.com with SMTP id y35so2460809pgl.1 for ; Wed, 09 Oct 2019 16:53:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D377o4252Ro5HndK+4EtYeG/eb9NkSj/n3duyIoGiIs=; b=scMasMGpJhb+ERHTZX7dKIBRg0Pp+CGtxZkNhuhHhmFNhzTo46j8aV+fHCQA6lLbq+ tLn8V2yxyUow6T48FGTfJWmhzCGm2XzYxhCMLJFaGOId1lN2wCsRuPnRkEsDkwHoZiKO CMNT+N3dXF+iHdPx5lnP8mKARWwurF24Cgyx3DFToLFDimsq6Jtz46yfZVXA0/tcqGEz oJsk3D6iQ/KhpvJEs3908bDl01zk7ZcMq3dLrYeNRsmX8wVOVy7m/z2Xe/XCbi4V2LQy RM5YPAUDpGcgEKR5QYkzaxBbOwiQY4RiFPm3NN8HNgdaWuK0T6gQoXlXIfVPQkbQzBlx vpAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D377o4252Ro5HndK+4EtYeG/eb9NkSj/n3duyIoGiIs=; b=IaI6b8wPsqVSmT+ek9EXTpx2h9W4ajywgYh3Rd/Y1qzimjc7l3lGOXABp9AZBd0dyw HibNjP8Ra1RbuUQgRaArdTEqiKyF8t8YYQXKanS2rQIiAKJQ4lxeWwMgNVHclMWbtNww fZCJ9OtjR/0wxQrBA17CGMTnaLndUCv5ide6P7rIxvVTMx1v/KSjyvMLVpMFyNmN7rYM LFVwQPK4AkW73ZX1kWwkVXcGo5AisIZR2Xey5p9NjwlJwIVMgR8D8nKhKirtOC/fndYs wmC+QCnc5rutBTyedJx6hrelBwqNqFLOiOog5qfvydx4ssoqiFV2+8bUYF/fGAsbLvn7 3nXA== X-Gm-Message-State: APjAAAXiNkli01CfitKAZ9n7f2Lx4QrPub2N7ZkeKiQ3x9oeP09XFr7A Y3riHPlRcueTYjy7O4ZTGodPObYA X-Google-Smtp-Source: APXvYqxko/FkJHNVNf+i8DWm62TxPRHW6jYohfnvO0YlJF3ULVRyIOE5EhgH5e5XM7EbnSbfzbJ+Lg== X-Received: by 2002:a17:90a:ff0f:: with SMTP id ce15mr7513696pjb.14.1570665193298; Wed, 09 Oct 2019 16:53:13 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:12 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:45 +1000 Message-Id: <20191009234951.2850-10-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 09/15] io: endian conversions for io accessors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This requires a small change to flash drivers which assumed 4-byte LPC reads would not change endian. _raw accessors could be added if this becomes a signifcant pattern, but for now this hack works. Signed-off-by: Nicholas Piggin --- include/io.h | 72 +++++++++++++++++++++++++++++++++++------- libflash/ipmi-hiomap.c | 18 ++++++++--- libflash/mbox-flash.c | 18 ++++++++--- 3 files changed, 88 insertions(+), 20 deletions(-) diff --git a/include/io.h b/include/io.h index c6203a274..3771dbb8a 100644 --- a/include/io.h +++ b/include/io.h @@ -38,7 +38,7 @@ static inline uint16_t __in_be16(const volatile uint16_t *addr) uint16_t val; asm volatile("lhzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be16_to_cpu(val); } static inline uint16_t in_be16(const volatile uint16_t *addr) @@ -47,9 +47,18 @@ static inline uint16_t in_be16(const volatile uint16_t *addr) return __in_be16(addr); } +static inline uint16_t __in_le16(const volatile uint16_t *addr) +{ + uint16_t val; + asm volatile("lhzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le16_to_cpu(val); +} + static inline uint16_t in_le16(const volatile uint16_t *addr) { - return bswap_16(in_be16(addr)); + sync(); + return __in_le16(addr); } static inline uint32_t __in_be32(const volatile uint32_t *addr) @@ -57,7 +66,7 @@ static inline uint32_t __in_be32(const volatile uint32_t *addr) uint32_t val; asm volatile("lwzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be32_to_cpu(val); } static inline uint32_t in_be32(const volatile uint32_t *addr) @@ -66,9 +75,18 @@ static inline uint32_t in_be32(const volatile uint32_t *addr) return __in_be32(addr); } +static inline uint32_t __in_le32(const volatile uint32_t *addr) +{ + uint32_t val; + asm volatile("lwzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le32_to_cpu(val); +} + static inline uint32_t in_le32(const volatile uint32_t *addr) { - return bswap_32(in_be32(addr)); + sync(); + return __in_le32(addr); } static inline uint64_t __in_be64(const volatile uint64_t *addr) @@ -76,7 +94,7 @@ static inline uint64_t __in_be64(const volatile uint64_t *addr) uint64_t val; asm volatile("ldcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be64_to_cpu(val); } static inline uint64_t in_be64(const volatile uint64_t *addr) @@ -85,9 +103,18 @@ static inline uint64_t in_be64(const volatile uint64_t *addr) return __in_be64(addr); } +static inline uint64_t __in_le64(const volatile uint64_t *addr) +{ + uint64_t val; + asm volatile("ldcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le64_to_cpu(val); +} + static inline uint64_t in_le64(const volatile uint64_t *addr) { - return bswap_64(in_be64(addr)); + sync(); + return __in_le64(addr); } static inline void __out_8(volatile uint8_t *addr, uint8_t val) @@ -105,7 +132,7 @@ static inline void out_8(volatile uint8_t *addr, uint8_t val) static inline void __out_be16(volatile uint16_t *addr, uint16_t val) { asm volatile("sthcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be16(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be16(volatile uint16_t *addr, uint16_t val) @@ -114,15 +141,22 @@ static inline void out_be16(volatile uint16_t *addr, uint16_t val) return __out_be16(addr, val); } +static inline void __out_le16(volatile uint16_t *addr, uint16_t val) +{ + asm volatile("sthcix %0,0,%1" + : : "r"(cpu_to_le16(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le16(volatile uint16_t *addr, uint16_t val) { - out_be16(addr, bswap_16(val)); + sync(); + return __out_le16(addr, val); } static inline void __out_be32(volatile uint32_t *addr, uint32_t val) { asm volatile("stwcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be32(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be32(volatile uint32_t *addr, uint32_t val) @@ -131,15 +165,22 @@ static inline void out_be32(volatile uint32_t *addr, uint32_t val) return __out_be32(addr, val); } +static inline void __out_le32(volatile uint32_t *addr, uint32_t val) +{ + asm volatile("stwcix %0,0,%1" + : : "r"(cpu_to_le32(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le32(volatile uint32_t *addr, uint32_t val) { - out_be32(addr, bswap_32(val)); + sync(); + return __out_le32(addr, val); } static inline void __out_be64(volatile uint64_t *addr, uint64_t val) { asm volatile("stdcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be64(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be64(volatile uint64_t *addr, uint64_t val) @@ -148,9 +189,16 @@ static inline void out_be64(volatile uint64_t *addr, uint64_t val) return __out_be64(addr, val); } +static inline void __out_le64(volatile uint64_t *addr, uint64_t val) +{ + asm volatile("stdcix %0,0,%1" + : : "r"(cpu_to_le64(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le64(volatile uint64_t *addr, uint64_t val) { - out_be64(addr, bswap_64(val)); + sync(); + return __out_le64(addr, val); } /* Assistant to macros used to access PCI config space */ diff --git a/libflash/ipmi-hiomap.c b/libflash/ipmi-hiomap.c index 7327b83a3..91d674231 100644 --- a/libflash/ipmi-hiomap.c +++ b/libflash/ipmi-hiomap.c @@ -570,8 +570,13 @@ static int lpc_window_read(struct ipmi_hiomap *ctx, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(uint32_t *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -615,12 +620,17 @@ static int lpc_window_write(struct ipmi_hiomap *ctx, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(uint32_t *)buf); + rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + dat, 4); chunk = 4; } else { + uint8_t dat = *(uint8_t *)buf; + rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + dat, 1); chunk = 1; } if (rc) { diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 9d47fe7ea..6fed30a9b 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -159,8 +159,13 @@ static int lpc_window_read(struct mbox_flash_data *mbox_flash, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(uint32_t *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -194,12 +199,17 @@ static int lpc_window_write(struct mbox_flash_data *mbox_flash, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(uint32_t *)buf); + rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + dat, 4); chunk = 4; } else { + uint8_t dat = *(uint8_t *)buf; + rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + dat, 1); chunk = 1; } if (rc) { From patchwork Wed Oct 9 23:49:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWMW32Fkz9s7T for ; Thu, 10 Oct 2019 10:56:23 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pNhrdy3D"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWMW1t87zDqYn for ; Thu, 10 Oct 2019 10:56:23 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pNhrdy3D"; dkim-atps=neutral Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHz2QcfzDqYX for ; Thu, 10 Oct 2019 10:53:19 +1100 (AEDT) Received: by mail-pf1-x441.google.com with SMTP id b128so2677972pfa.1 for ; Wed, 09 Oct 2019 16:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V4z9fzEpkhTROzJyzhb0KUgp4MKz++ETPzzLjs+MFNM=; b=pNhrdy3DNXJ6E8oV69dTwzoO37WJMoubktVsRrZeM0RidkL7+PDOcdXWn7bBkOspcz he/MLoZ24Ao3ow58Xwn761YUbsLr96ioJLrulxzoaBghRyBc9ew2rgxsoPGxaJ1Z26zy PADnnukbIqRqhW499+yvQzyv/u8kNFs1Y3gEJPN4fH2NmZu39YNTkb6apJXFqAFvPKJ2 /8m0Y3EHZvMXd4ADbcv1TQVk6QHKqsw1wLn6F/n4OFwP4VfXlu2quZ3c5H1J+myRTLCR WT8woUckVeHM2eAbsDw6qc4J+QFmaSf9y0qA5SHTThZpASIdcV86jNXtG9IoIGz1/lNs /FOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V4z9fzEpkhTROzJyzhb0KUgp4MKz++ETPzzLjs+MFNM=; b=AMrd1muJUUb8y5d45pLf+gqbgV/Cs7eXgbzdkXXP8w4h/PM9OVOgE+CRe2itUfgXBH v4DMzBvkVHt8kRMq7YHZZYw00OS8j1H++FgzhPMULo5lUQEHc6y2dfMElcsb59OSxeeV MFLqFuWAFZ24x/n7G6P4Jpi1cxyK9esKWmPmfhgty7WCOvMSgzNfmzFPQqyZfcnjEsR/ 2znmmDCzDAcDO/12YNUNPcKNDyRZZ/WFJfe7+SJD+KmhKrEuuAmzC17NT6Zmii4W4R5g 35BWzBld+rRcnzpYs6poQY7EvgkZWMg9hOKaHA+Mkc88sTqIubGiaH8HVb6G8i7VCyFO wAwQ== X-Gm-Message-State: APjAAAUQ1/kHbNknOw5wjYcN+spvapZzn5+1ZaNI2zzT8QbXY+Pd9KDe xfLjOaEUS7O0wFDxBQKKFGE2Qshg X-Google-Smtp-Source: APXvYqxhhJDnV/z0KAhq/6bSXSXtTI0xeHbZp2vY7GUoF/r0omOhiMN4s21mo3aTWf280Xm/uvcF7A== X-Received: by 2002:a17:90a:2142:: with SMTP id a60mr7337508pje.8.1570665195403; Wed, 09 Oct 2019 16:53:15 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:14 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:46 +1000 Message-Id: <20191009234951.2850-11-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 10/15] xive: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert xive opal calls, dt construction, and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/xive.c | 386 ++++++++++++++++++++++++++----------------------- include/xive.h | 50 +++---- 2 files changed, 230 insertions(+), 206 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 96a9bc647..8bfe74db3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -421,7 +421,7 @@ struct xive { /* Indirect NVT/VP table. NULL entries are unallocated, count is * the numbre of pointers (ie, sub page placeholders). */ - uint64_t *vp_ind_base; + __be64 *vp_ind_base; uint32_t vp_ind_count; #else void *vp_base; @@ -805,7 +805,7 @@ static struct xive_eq *xive_get_eq(struct xive *x, unsigned int idx) #ifdef USE_INDIRECT if (idx >= (x->eq_ind_count * EQ_PER_PAGE)) return NULL; - p = (struct xive_eq *)(x->eq_ind_base[idx / EQ_PER_PAGE] & + p = (struct xive_eq *)(be64_to_cpu(x->eq_ind_base[idx / EQ_PER_PAGE]) & VSD_ADDRESS_MASK); if (!p) return NULL; @@ -845,11 +845,11 @@ static struct xive_ive *xive_get_ive(struct xive *x, unsigned int isn) /* If using single-escalation, don't let anybody get to the individual * esclation interrupts */ - if (eq->w0 & EQ_W0_UNCOND_ESCALATE) + if (be32_to_cpu(eq->__w0) & EQ_W0_UNCOND_ESCALATE) return NULL; /* Grab the buried IVE */ - return (struct xive_ive *)(char *)&eq->w4; + return (struct xive_ive *)(char *)&eq->__w4; } else { /* Check the block matches */ if (isn < x->int_base || isn >= x->int_max) { @@ -874,7 +874,7 @@ static struct xive_vp *xive_get_vp(struct xive *x, unsigned int idx) #ifdef USE_INDIRECT assert(idx < (x->vp_ind_count * VP_PER_PAGE)); - p = (struct xive_vp *)(x->vp_ind_base[idx / VP_PER_PAGE] & + p = (struct xive_vp *)(be64_to_cpu(x->vp_ind_base[idx / VP_PER_PAGE]) & VSD_ADDRESS_MASK); if (!p) return NULL; @@ -893,8 +893,8 @@ static void xive_init_default_vp(struct xive_vp *vp, memset(vp, 0, sizeof(struct xive_vp)); /* Stash the EQ base in the pressure relief interrupt field */ - vp->w1 = (eq_blk << 28) | eq_idx; - vp->w0 = VP_W0_VALID; + vp->__w1 = cpu_to_be32((eq_blk << 28) | eq_idx); + vp->__w0 = cpu_to_be32(VP_W0_VALID); } static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, @@ -903,17 +903,16 @@ static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, { memset(eq, 0, sizeof(struct xive_eq)); - eq->w1 = EQ_W1_GENERATION; - eq->w3 = ((uint64_t)backing_page) & 0xffffffff; - eq->w2 = (((uint64_t)backing_page)) >> 32 & 0x0fffffff; - eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | - SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); - eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); - eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE | - SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) | - EQ_W0_FIRMWARE; + eq->__w1 = cpu_to_be32(EQ_W1_GENERATION); + eq->__w3 = cpu_to_be32(((uint64_t)backing_page) & 0xffffffff); + eq->__w2 = cpu_to_be32(((((uint64_t)backing_page)) >> 32) & 0x0fffffff); + eq->__w6 = cpu_to_be32(SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | + SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx)); + eq->__w7 = cpu_to_be32(SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio)); + eq->__w0 = cpu_to_be32(EQ_W0_VALID | EQ_W0_ENQUEUE | + SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) | EQ_W0_FIRMWARE); #ifdef EQ_ALWAYS_NOTIFY - eq->w0 |= EQ_W0_UCOND_NOTIFY; + eq->__w0 |= cpu_to_be32(EQ_W0_UCOND_NOTIFY); #endif } @@ -926,8 +925,8 @@ static uint32_t *xive_get_eq_buf(uint32_t eq_blk, uint32_t eq_idx) assert(x); eq = xive_get_eq(x, eq_idx); assert(eq); - assert(eq->w0 & EQ_W0_VALID); - addr = (((uint64_t)eq->w2) & 0x0fffffff) << 32 | eq->w3; + assert(be32_to_cpu(eq->__w0) & EQ_W0_VALID); + addr = (((uint64_t)be32_to_cpu(eq->__w2)) & 0x0fffffff) << 32 | be32_to_cpu(eq->__w3); return (uint32_t *)addr; } @@ -998,8 +997,8 @@ static uint32_t xive_alloc_eq_set(struct xive *x, bool alloc_indirect __unused) } } memset(page, 0, 0x10000); - x->eq_ind_base[ind_idx] = vsd_flags | - (((uint64_t)page) & VSD_ADDRESS_MASK); + x->eq_ind_base[ind_idx] = cpu_to_be64(vsd_flags | + (((uint64_t)page) & VSD_ADDRESS_MASK)); /* Any cache scrub needed ? */ } #endif /* USE_INDIRECT */ @@ -1046,7 +1045,7 @@ static bool xive_provision_vp_ind(struct xive *x, uint32_t vp_idx, uint32_t orde vsd = ((uint64_t)page) & VSD_ADDRESS_MASK; vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); - x->vp_ind_base[i] = vsd; + x->vp_ind_base[i] = cpu_to_be64(vsd); } return true; } @@ -1456,7 +1455,7 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, * one written. */ for (i = start_dword + dword_count - 1; i >= start_dword ;i--) { - uint64_t dw = ((uint64_t *)new_data)[i - start_dword]; + uint64_t dw = be64_to_cpu(((__be64 *)new_data)[i - start_dword]); __xive_regw(x, dreg0 + i * 8, dreg0x + i, dw, NULL); } @@ -1846,7 +1845,7 @@ static bool xive_prealloc_tables(struct xive *x) } /* SBEs are initialized to 0b01 which corresponds to "ints off" */ memset(x->sbe_base, 0x55, SBE_SIZE); - xive_dbg(x, "SBE at %p size 0x%x\n", x->sbe_base, IVT_SIZE); + xive_dbg(x, "SBE at %p size 0x%x\n", x->sbe_base, SBE_SIZE); /* EAS/IVT entries are 8 bytes */ x->ivt_base = local_alloc(x->chip_id, IVT_SIZE, IVT_SIZE); @@ -1919,7 +1918,7 @@ static bool xive_prealloc_tables(struct xive *x) vsd |= SETFIELD(VSD_TSIZE, 0ull, 4); vsd |= SETFIELD(VSD_MODE, 0ull, VSD_MODE_EXCLUSIVE); vsd |= VSD_FIRMWARE; - x->vp_ind_base[i] = vsd; + x->vp_ind_base[i] = cpu_to_be64(vsd); } #else /* USE_INDIRECT */ @@ -1966,7 +1965,7 @@ static void xive_add_provisioning_properties(void) count = xive_block_count; #endif for (i = 0; i < count; i++) - chips[i] = xive_block_to_chip[i]; + chips[i] = cpu_to_be32(xive_block_to_chip[i]); dt_add_property(xive_dt_node, "ibm,xive-provision-chips", chips, 4 * count); } @@ -2094,7 +2093,8 @@ uint32_t xive_alloc_hw_irqs(uint32_t chip_id, uint32_t count, uint32_t align) for (i = 0; i < count; i++) { struct xive_ive *ive = xive_get_ive(x, base + i); - ive->w = IVE_VALID | IVE_MASKED | SETFIELD(IVE_EQ_DATA, 0ul, base + i); + ive->__w = cpu_to_be64(IVE_VALID | IVE_MASKED | + SETFIELD(IVE_EQ_DATA, 0ul, base + i)); } unlock(&x->lock); @@ -2140,8 +2140,8 @@ uint32_t xive_alloc_ipi_irqs(uint32_t chip_id, uint32_t count, uint32_t align) for (i = 0; i < count; i++) { struct xive_ive *ive = xive_get_ive(x, base + i); - ive->w = IVE_VALID | IVE_MASKED | - SETFIELD(IVE_EQ_DATA, 0ul, base + i); + ive->__w = cpu_to_be64(IVE_VALID | IVE_MASKED | + SETFIELD(IVE_EQ_DATA, 0ul, base + i)); } unlock(&x->lock); @@ -2267,6 +2267,7 @@ static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, uint32_t eq_blk, eq_idx; uint32_t vp_blk __unused, vp_idx; uint32_t prio, server; + uint64_t ive_w; bool is_escalation = GIRQ_IS_ESCALATION(isn); /* Find XIVE on which the IVE resides */ @@ -2277,17 +2278,18 @@ static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, ive = xive_get_ive(x, isn); if (!ive) return false; - if (!(ive->w & IVE_VALID) && !is_escalation) { + ive_w = be64_to_cpu(ive->__w); + if (!(ive_w & IVE_VALID) && !is_escalation) { xive_err(x, "ISN %x lead to invalid IVE !\n", isn); return false; } if (out_lirq) - *out_lirq = GETFIELD(IVE_EQ_DATA, ive->w); + *out_lirq = GETFIELD(IVE_EQ_DATA, ive_w); /* Find the EQ and its xive instance */ - eq_blk = GETFIELD(IVE_EQ_BLOCK, ive->w); - eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w); + eq_blk = GETFIELD(IVE_EQ_BLOCK, ive_w); + eq_idx = GETFIELD(IVE_EQ_INDEX, ive_w); eq_x = xive_from_vc_blk(eq_blk); /* This can fail if the interrupt hasn't been initialized yet @@ -2302,15 +2304,15 @@ static bool xive_get_irq_targetting(uint32_t isn, uint32_t *out_target, /* XXX Check valid and format 0 */ /* No priority conversion, return the actual one ! */ - if (ive->w & IVE_MASKED) + if (ive_w & IVE_MASKED) prio = 0xff; else - prio = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); + prio = GETFIELD(EQ_W7_F0_PRIORITY, be32_to_cpu(eq->__w7)); if (out_prio) *out_prio = prio; - vp_blk = GETFIELD(EQ_W6_NVT_BLOCK, eq->w6); - vp_idx = GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + vp_blk = GETFIELD(EQ_W6_NVT_BLOCK, be32_to_cpu(eq->__w6)); + vp_idx = GETFIELD(EQ_W6_NVT_INDEX, be32_to_cpu(eq->__w6)); server = VP2PIR(vp_blk, vp_idx); if (out_target) @@ -2360,8 +2362,8 @@ static inline bool xive_eq_for_target(uint32_t target, uint8_t prio, /* Grab it, it's in the pressure relief interrupt field, * top 4 bits are the block (word 1). */ - eq_blk = vp->w1 >> 28; - eq_idx = vp->w1 & 0x0fffffff; + eq_blk = be32_to_cpu(vp->__w1) >> 28; + eq_idx = be32_to_cpu(vp->__w1) & 0x0fffffff; /* Currently the EQ block and VP block should be the same */ if (eq_blk != vp_blk) { @@ -2397,7 +2399,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, ive = xive_get_ive(x, isn); if (!ive) return OPAL_PARAMETER; - if (!(ive->w & IVE_VALID) && !is_escalation) { + if (!(be64_to_cpu(ive->__w) & IVE_VALID) && !is_escalation) { xive_err(x, "ISN %x lead to invalid IVE !\n", isn); return OPAL_PARAMETER; } @@ -2409,7 +2411,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, prio = XIVE_EMULATION_PRIO; /* Read existing IVE */ - new_ive = ive->w; + new_ive = be64_to_cpu(ive->__w); /* Are we masking ? */ if (prio == 0xff && !is_escalation) { @@ -2420,7 +2422,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, prio = 7; } else { /* Unmasking */ - new_ive = ive->w & ~IVE_MASKED; + new_ive = be64_to_cpu(ive->__w) & ~IVE_MASKED; xive_vdbg(x, "ISN %x unmasked !\n", isn); /* For normal interrupt sources, keep track of which ones @@ -2460,7 +2462,7 @@ static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target, 2, 1, &new_ive, true, synchronous); } else { sync(); - ive->w = new_ive; + ive->__w = cpu_to_be64(new_ive); rc = xive_ivc_scrub(x, x->block_id, GIRQ_TO_IDX(isn)); } @@ -2641,6 +2643,7 @@ void __xive_source_eoi(struct irq_source *is, uint32_t isn) uint32_t idx = isn - s->esb_base; struct xive_ive *ive; void *mmio_base; + uint64_t ive_w; uint64_t eoi_val; /* Grab the IVE */ @@ -2649,13 +2652,15 @@ void __xive_source_eoi(struct irq_source *is, uint32_t isn) return; ive += GIRQ_TO_IDX(isn); + ive_w = be64_to_cpu(ive->__w); + /* XXX To fix the races with mask/unmask potentially causing * multiple queue entries, we need to keep track of EOIs here, * before the masked test below */ /* If it's invalid or masked, don't do anything */ - if ((ive->w & IVE_MASKED) || !(ive->w & IVE_VALID)) + if ((ive_w & IVE_MASKED) || !(ive_w & IVE_VALID)) return; /* Grab MMIO control address for that ESB */ @@ -3029,13 +3034,17 @@ static bool xive_check_eq_update(struct xive *x, uint32_t idx, struct xive_eq *e if (memcmp(eq, &eq2, sizeof(struct xive_eq)) != 0) { xive_err(x, "EQ update mismatch idx %d\n", idx); xive_err(x, "want: %08x %08x %08x %08x\n", - eq->w0, eq->w1, eq->w2, eq->w3); + be32_to_cpu(eq->__w0), be32_to_cpu(eq->__w1), + be32_to_cpu(eq->__w2), be32_to_cpu(eq->__w3)); xive_err(x, " %08x %08x %08x %08x\n", - eq->w4, eq->w5, eq->w6, eq->w7); + be32_to_cpu(eq->__w4), be32_to_cpu(eq->__w5), + be32_to_cpu(eq->__w6), be32_to_cpu(eq->__w7)); xive_err(x, "got : %08x %08x %08x %08x\n", - eq2.w0, eq2.w1, eq2.w2, eq2.w3); + be32_to_cpu(eq2.__w0), be32_to_cpu(eq2.__w1), + be32_to_cpu(eq2.__w2), be32_to_cpu(eq2.__w3)); xive_err(x, " %08x %08x %08x %08x\n", - eq2.w4, eq2.w5, eq2.w6, eq2.w7); + be32_to_cpu(eq2.__w4), be32_to_cpu(eq2.__w5), + be32_to_cpu(eq2.__w6), be32_to_cpu(eq2.__w7)); return false; } return true; @@ -3051,13 +3060,17 @@ static bool xive_check_vpc_update(struct xive *x, uint32_t idx, struct xive_vp * if (memcmp(vp, &vp2, sizeof(struct xive_vp)) != 0) { xive_err(x, "VP update mismatch idx %d\n", idx); xive_err(x, "want: %08x %08x %08x %08x\n", - vp->w0, vp->w1, vp->w2, vp->w3); + be32_to_cpu(vp->__w0), be32_to_cpu(vp->__w1), + be32_to_cpu(vp->__w2), be32_to_cpu(vp->__w3)); xive_err(x, " %08x %08x %08x %08x\n", - vp->w4, vp->w5, vp->w6, vp->w7); + be32_to_cpu(vp->__w4), be32_to_cpu(vp->__w5), + be32_to_cpu(vp->__w6), be32_to_cpu(vp->__w7)); xive_err(x, "got : %08x %08x %08x %08x\n", - vp2.w0, vp2.w1, vp2.w2, vp2.w3); + be32_to_cpu(vp2.__w0), be32_to_cpu(vp2.__w1), + be32_to_cpu(vp2.__w2), be32_to_cpu(vp2.__w3)); xive_err(x, " %08x %08x %08x %08x\n", - vp2.w4, vp2.w5, vp2.w6, vp2.w7); + be32_to_cpu(vp2.__w4), be32_to_cpu(vp2.__w5), + be32_to_cpu(vp2.__w6), be32_to_cpu(vp2.__w7)); return false; } return true; @@ -3089,7 +3102,7 @@ static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); sync(); - vp.w1 = (i << 16) | i; + vp.__w1 = cpu_to_be32((i << 16) | i); xive_vpc_cache_update(x, blk, idx, 0, 8, &vp, false, true); if (!xive_check_vpc_update(x, idx, &vp)) { @@ -3132,6 +3145,7 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) /* Use the cache watch to write it out */ lock(&x_eq->lock); + xive_eqc_cache_update(x_eq, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); @@ -3349,7 +3363,7 @@ static void xive_init_cpu_properties(struct cpu_thread *cpu) t = (i == 0) ? cpu : find_cpu_by_pir(cpu->pir + i); if (!t) continue; - iprop[i][0] = t->xstate->ipi_irq; + iprop[i][0] = cpu_to_be32(t->xstate->ipi_irq); iprop[i][1] = 0; /* Edge */ } dt_add_property(cpu->node, "interrupts", iprop, cpu_thread_count * 8); @@ -3420,7 +3434,7 @@ static uint32_t xive_read_eq(struct xive_cpu_state *xs, bool just_peek) unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); prerror("EQ @%p W0=%08x W1=%08x qbuf @%p\n", - eq, eq->w0, eq->w1, xs->eqbuf); + eq, be32_to_cpu(eq->__w0), be32_to_cpu(eq->__w1), xs->eqbuf); } log_add(xs, LOG_TYPE_POPQ, 7, cur, xs->eqbuf[(xs->eqptr + 1) & xs->eqmsk], @@ -3637,20 +3651,20 @@ static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) xive_cpu_err(me, "no ive attached\n"); return true; } - xive_cpu_err(me, "ive=%016llx\n", ive->w); + xive_cpu_err(me, "ive=%016llx\n", be64_to_cpu(ive->__w)); for_each_chip(chip) { x = chip->xive; if (!x) continue; ive = x->ivt_base; for (i = 0; i < MAX_INT_ENTRIES; i++) { - if ((ive[i].w & IVE_EQ_DATA) == irq) { + if ((be64_to_cpu(ive[i].__w) & IVE_EQ_DATA) == irq) { eq_blk = GETFIELD(IVE_EQ_BLOCK, ive[i].w); eq_idx = GETFIELD(IVE_EQ_INDEX, ive[i].w); xive_cpu_err(me, "Found source: 0x%x ive=%016llx\n" " eq 0x%x/%x", BLKIDX_TO_GIRQ(x->block_id, i), - ive[i].w, eq_blk, eq_idx); + be64_to_cpu(ive[i].__w), eq_blk, eq_idx); xive_dump_eq(eq_blk, eq_idx); } } @@ -3668,7 +3682,7 @@ static inline bool check_misrouted_ipi(struct cpu_thread *c __unused, } #endif -static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) +static int64_t opal_xive_get_xirr(__be32 *out_xirr, bool just_poll) { struct cpu_thread *c = this_cpu(); struct xive_cpu_state *xs = c->xstate; @@ -3752,7 +3766,7 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) false, false); unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); - log_add(xs, LOG_TYPE_EQD, 2, eq->w0, eq->w1); + log_add(xs, LOG_TYPE_EQD, 2, cpu_to_be32(eq->__w0), cpu_to_be32(eq->__w1)); } #endif /* XIVE_PERCPU_LOG */ @@ -3775,7 +3789,7 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) if (check_misrouted_ipi(c, val)) val = 2; - *out_xirr = (old_cppr << 24) | val; + *out_xirr = cpu_to_be32((old_cppr << 24) | val); /* If we are polling, that's it */ if (just_poll) @@ -3812,9 +3826,9 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) skip: log_add(xs, LOG_TYPE_XIRR2, 5, xs->cppr, xs->pending, - *out_xirr, xs->eqptr, xs->eqgen); + be32_to_cpu(*out_xirr), xs->eqptr, xs->eqgen); xive_cpu_vdbg(c, " returning XIRR=%08x, pending=0x%x\n", - *out_xirr, xs->pending); + be32_to_cpu(*out_xirr), xs->pending); unlock(&xs->lock); @@ -3890,11 +3904,11 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags) } static int64_t opal_xive_get_irq_info(uint32_t girq, - uint64_t *out_flags, - uint64_t *out_eoi_page, - uint64_t *out_trig_page, - uint32_t *out_esb_shift, - uint32_t *out_src_chip) + __be64 *out_flags, + __be64 *out_eoi_page, + __be64 *out_trig_page, + __be32 *out_esb_shift, + __be32 *out_src_chip) { struct irq_source *is = irq_find_source(girq); struct xive_src *s = container_of(is, struct xive_src, is); @@ -3909,7 +3923,7 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, assert(is->ops == &xive_irq_source_ops); if (out_flags) - *out_flags = xive_convert_irq_flags(s->flags); + *out_flags = cpu_to_be64(xive_convert_irq_flags(s->flags)); /* * If the orig source has a set_xive callback, then set @@ -3918,15 +3932,15 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, */ if (out_flags && s->orig_ops) { if (s->orig_ops->set_xive) - *out_flags |= OPAL_XIVE_IRQ_MASK_VIA_FW; + *out_flags |= cpu_to_be64(OPAL_XIVE_IRQ_MASK_VIA_FW); if (s->orig_ops->eoi) - *out_flags |= OPAL_XIVE_IRQ_EOI_VIA_FW; + *out_flags |= cpu_to_be64(OPAL_XIVE_IRQ_EOI_VIA_FW); } idx = girq - s->esb_base; if (out_esb_shift) - *out_esb_shift = s->esb_shift; + *out_esb_shift = cpu_to_be32(s->esb_shift); mm_base = (uint64_t)s->esb_mmio + (1ull << s->esb_shift) * idx; @@ -3942,27 +3956,31 @@ static int64_t opal_xive_get_irq_info(uint32_t girq, trig_page = mm_base; if (out_eoi_page) - *out_eoi_page = eoi_page; + *out_eoi_page = cpu_to_be64(eoi_page); if (out_trig_page) - *out_trig_page = trig_page; + *out_trig_page = cpu_to_be64(trig_page); if (out_src_chip) - *out_src_chip = GIRQ_TO_CHIP(girq); + *out_src_chip = cpu_to_be32(GIRQ_TO_CHIP(girq)); return OPAL_SUCCESS; } static int64_t opal_xive_get_irq_config(uint32_t girq, - uint64_t *out_vp, + __be64 *out_vp, uint8_t *out_prio, - uint32_t *out_lirq) + __be32 *out_lirq) { uint32_t vp; + uint32_t lirq; + uint8_t prio; if (xive_mode != XIVE_MODE_EXPL) return OPAL_WRONG_STATE; - if (xive_get_irq_targetting(girq, &vp, out_prio, out_lirq)) { - *out_vp = vp; + if (xive_get_irq_targetting(girq, &vp, &prio, &lirq)) { + *out_vp = cpu_to_be64(vp); + *out_prio = prio; + *out_lirq = cpu_to_be32(lirq); return OPAL_SUCCESS; } else return OPAL_PARAMETER; @@ -3993,15 +4011,16 @@ static int64_t opal_xive_set_irq_config(uint32_t girq, } static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, - uint64_t *out_qpage, - uint64_t *out_qsize, - uint64_t *out_qeoi_page, - uint32_t *out_escalate_irq, - uint64_t *out_qflags) + __be64 *out_qpage, + __be64 *out_qsize, + __be64 *out_qeoi_page, + __be32 *out_escalate_irq, + __be64 *out_qflags) { uint32_t blk, idx; struct xive *x; struct xive_eq *eq; + uint32_t eq_w0; if (xive_mode != XIVE_MODE_EXPL) return OPAL_WRONG_STATE; @@ -4017,22 +4036,24 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, if (!eq) return OPAL_PARAMETER; + eq_w0 = be32_to_cpu(eq->__w0); + if (out_escalate_irq) { uint32_t esc_idx = idx; /* If escalations are routed to a single queue, fix up * the escalation interrupt number here. */ - if (eq->w0 & EQ_W0_UNCOND_ESCALATE) + if (eq_w0 & EQ_W0_UNCOND_ESCALATE) esc_idx |= 7; *out_escalate_irq = - MAKE_ESCALATION_GIRQ(blk, esc_idx); + cpu_to_be32(MAKE_ESCALATION_GIRQ(blk, esc_idx)); } /* If this is a single-escalation gather queue, that's all * there is to return */ - if (eq->w0 & EQ_W0_SILENT_ESCALATE) { + if (eq_w0 & EQ_W0_SILENT_ESCALATE) { if (out_qflags) *out_qflags = 0; if (out_qpage) @@ -4045,30 +4066,30 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, } if (out_qpage) { - if (eq->w0 & EQ_W0_ENQUEUE) + if (eq_w0 & EQ_W0_ENQUEUE) *out_qpage = - (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3; + cpu_to_be64((((uint64_t)(be32_to_cpu(eq->__w2) & 0x0fffffff)) << 32) | be32_to_cpu(eq->__w3)); else *out_qpage = 0; } if (out_qsize) { - if (eq->w0 & EQ_W0_ENQUEUE) - *out_qsize = GETFIELD(EQ_W0_QSIZE, eq->w0) + 12; + if (eq_w0 & EQ_W0_ENQUEUE) + *out_qsize = cpu_to_be64(GETFIELD(EQ_W0_QSIZE, eq_w0) + 12); else *out_qsize = 0; } if (out_qeoi_page) { *out_qeoi_page = - (uint64_t)x->eq_mmio + idx * 0x20000; + cpu_to_be64((uint64_t)x->eq_mmio + idx * 0x20000); } if (out_qflags) { *out_qflags = 0; - if (eq->w0 & EQ_W0_VALID) - *out_qflags |= OPAL_XIVE_EQ_ENABLED; - if (eq->w0 & EQ_W0_UCOND_NOTIFY) - *out_qflags |= OPAL_XIVE_EQ_ALWAYS_NOTIFY; - if (eq->w0 & EQ_W0_ESCALATE_CTL) - *out_qflags |= OPAL_XIVE_EQ_ESCALATE; + if (eq_w0 & EQ_W0_VALID) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ENABLED); + if (eq_w0 & EQ_W0_UCOND_NOTIFY) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ALWAYS_NOTIFY); + if (eq_w0 & EQ_W0_ESCALATE_CTL) + *out_qflags |= cpu_to_be64(OPAL_XIVE_EQ_ESCALATE); } return OPAL_SUCCESS; @@ -4076,9 +4097,9 @@ static int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, static void xive_cleanup_eq(struct xive_eq *eq) { - eq->w0 = eq->w0 & EQ_W0_FIRMWARE; - eq->w1 = EQ_W1_ESe_Q | EQ_W1_ESn_Q; - eq->w2 = eq->w3 = eq->w4 = eq->w5 = eq->w6 = eq->w7 = 0; + eq->__w0 = cpu_to_be32(be32_to_cpu(eq->__w0) & EQ_W0_FIRMWARE); + eq->__w1 = cpu_to_be32(EQ_W1_ESe_Q | EQ_W1_ESn_Q); + eq->__w2 = eq->__w3 = eq->__w4 = eq->__w5 = eq->__w6 = eq->__w7 = 0; } static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, @@ -4110,7 +4131,7 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, /* If this is a silent escalation queue, it cannot be * configured directly */ - if (old_eq->w0 & EQ_W0_SILENT_ESCALATE) + if (be32_to_cpu(old_eq->__w0) & EQ_W0_SILENT_ESCALATE) return OPAL_PARAMETER; /* This shouldn't fail or xive_eq_for_target would have @@ -4132,14 +4153,14 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, case 16: case 21: case 24: - eq.w3 = ((uint64_t)qpage) & 0xffffffff; - eq.w2 = (((uint64_t)qpage)) >> 32 & 0x0fffffff; - eq.w0 |= EQ_W0_ENQUEUE; - eq.w0 = SETFIELD(EQ_W0_QSIZE, eq.w0, qsize - 12); + eq.__w3 = cpu_to_be32(((uint64_t)qpage) & 0xffffffff); + eq.__w2 = cpu_to_be32((((uint64_t)qpage)) >> 32 & 0x0fffffff); + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) | EQ_W0_ENQUEUE); + eq.__w0 = cpu_to_be32(SETFIELD(EQ_W0_QSIZE, be32_to_cpu(eq.__w0), qsize - 12)); break; case 0: - eq.w2 = eq.w3 = 0; - eq.w0 &= ~EQ_W0_ENQUEUE; + eq.__w2 = eq.__w3 = 0; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) & ~EQ_W0_ENQUEUE); break; default: return OPAL_PARAMETER; @@ -4148,34 +4169,35 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, /* Ensure the priority and target are correctly set (they will * not be right after allocation */ - eq.w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | - SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); - eq.w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); + eq.__w6 = cpu_to_be32(SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | + SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx)); + eq.__w7 = cpu_to_be32(SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio)); /* XXX Handle group i bit when needed */ /* Always notify flag */ if (qflags & OPAL_XIVE_EQ_ALWAYS_NOTIFY) - eq.w0 |= EQ_W0_UCOND_NOTIFY; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) | EQ_W0_UCOND_NOTIFY); else - eq.w0 &= ~EQ_W0_UCOND_NOTIFY; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) & ~EQ_W0_UCOND_NOTIFY); /* Escalation flag */ if (qflags & OPAL_XIVE_EQ_ESCALATE) - eq.w0 |= EQ_W0_ESCALATE_CTL; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) | EQ_W0_ESCALATE_CTL); else - eq.w0 &= ~EQ_W0_ESCALATE_CTL; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) & ~EQ_W0_ESCALATE_CTL); /* Unconditionally clear the current queue pointer, set * generation to 1 and disable escalation interrupts. */ - eq.w1 = EQ_W1_GENERATION | - (old_eq->w1 & (EQ_W1_ESe_P | EQ_W1_ESe_Q | - EQ_W1_ESn_P | EQ_W1_ESn_Q)); + eq.__w1 = cpu_to_be32(EQ_W1_GENERATION | + (be32_to_cpu(old_eq->__w1) & + (EQ_W1_ESe_P | EQ_W1_ESe_Q | + EQ_W1_ESn_P | EQ_W1_ESn_Q))); /* Enable. We always enable backlog for an enabled queue * otherwise escalations won't work. */ - eq.w0 |= EQ_W0_VALID | EQ_W0_BACKLOG; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) | EQ_W0_VALID | EQ_W0_BACKLOG); } else xive_cleanup_eq(&eq); @@ -4188,8 +4210,8 @@ static int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, } static int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, - uint32_t *out_qtoggle, - uint32_t *out_qindex) + __be32 *out_qtoggle, + __be32 *out_qindex) { uint32_t blk, idx; struct xive *x; @@ -4219,11 +4241,11 @@ static int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio, return rc; /* We don't do disable queues */ - if (!(eq->w0 & EQ_W0_VALID)) + if (!(be32_to_cpu(eq->__w0) & EQ_W0_VALID)) return OPAL_WRONG_STATE; - *out_qtoggle = GETFIELD(EQ_W1_GENERATION, eq->w1); - *out_qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1); + *out_qtoggle = cpu_to_be32(GETFIELD(EQ_W1_GENERATION, be32_to_cpu(eq->__w1))); + *out_qindex = cpu_to_be32(GETFIELD(EQ_W1_PAGE_OFF, be32_to_cpu(eq->__w1))); return OPAL_SUCCESS; } @@ -4251,13 +4273,13 @@ static int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio, return OPAL_PARAMETER; /* We don't do disable queues */ - if (!(eq->w0 & EQ_W0_VALID)) + if (!(be32_to_cpu(eq->__w0) & EQ_W0_VALID)) return OPAL_WRONG_STATE; new_eq = *eq; - new_eq.w1 = SETFIELD(EQ_W1_GENERATION, new_eq.w1, qtoggle); - new_eq.w1 = SETFIELD(EQ_W1_PAGE_OFF, new_eq.w1, qindex); + new_eq.__w1 = cpu_to_be32(SETFIELD(EQ_W1_GENERATION, be32_to_cpu(new_eq.__w1), qtoggle)); + new_eq.__w1 = cpu_to_be32(SETFIELD(EQ_W1_PAGE_OFF, be32_to_cpu(new_eq.__w1), qindex)); lock(&x->lock); rc = xive_eqc_cache_update(x, blk, idx, 0, 4, &new_eq, false, false); @@ -4289,10 +4311,10 @@ static int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr) } static int64_t opal_xive_get_vp_info(uint64_t vp_id, - uint64_t *out_flags, - uint64_t *out_cam_value, - uint64_t *out_report_cl_pair, - uint32_t *out_chip_id) + __be64 *out_flags, + __be64 *out_cam_value, + __be64 *out_report_cl_pair, + __be32 *out_chip_id) { struct xive *x; struct xive_vp *vp; @@ -4334,22 +4356,22 @@ static int64_t opal_xive_get_vp_info(uint64_t vp_id, eq = xive_get_eq(x, eq_idx); if (!eq) return OPAL_PARAMETER; - if (vp->w0 & VP_W0_VALID) - *out_flags |= OPAL_XIVE_VP_ENABLED; - if (eq->w0 & EQ_W0_SILENT_ESCALATE) - *out_flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; + if (be32_to_cpu(vp->__w0) & VP_W0_VALID) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_ENABLED); + if (be32_to_cpu(eq->__w0) & EQ_W0_SILENT_ESCALATE) + *out_flags |= cpu_to_be64(OPAL_XIVE_VP_SINGLE_ESCALATION); } if (out_cam_value) - *out_cam_value = (blk << 19) | idx; + *out_cam_value = cpu_to_be64((blk << 19) | idx); if (out_report_cl_pair) { - *out_report_cl_pair = ((uint64_t)(vp->w6 & 0x0fffffff)) << 32; - *out_report_cl_pair |= vp->w7 & 0xffffff00; + *out_report_cl_pair = cpu_to_be64(((uint64_t)(be32_to_cpu(vp->__w6) & 0x0fffffff)) << 32); + *out_report_cl_pair |= cpu_to_be64(be32_to_cpu(vp->__w7) & 0xffffff00); } if (out_chip_id) - *out_chip_id = xive_block_to_chip[blk]; + *out_chip_id = cpu_to_be32(xive_block_to_chip[blk]); return OPAL_SUCCESS; } @@ -4377,8 +4399,8 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) /* If trying to enable silent gather, make sure prio 7 is not * already enabled as a normal queue */ - if (enable && (eq_orig->w0 & EQ_W0_VALID) && - !(eq_orig->w0 & EQ_W0_SILENT_ESCALATE)) { + if (enable && (be32_to_cpu(eq_orig->__w0) & EQ_W0_VALID) && + !(be32_to_cpu(eq_orig->__w0) & EQ_W0_SILENT_ESCALATE)) { xive_dbg(x, "Attempt at enabling silent gather but" " prio 7 queue already in use\n"); return OPAL_PARAMETER; @@ -4388,15 +4410,14 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) if (enable) { /* W0: Enabled and "s" set, no other bit */ - eq.w0 &= EQ_W0_FIRMWARE; - eq.w0 |= EQ_W0_VALID | EQ_W0_SILENT_ESCALATE | - EQ_W0_ESCALATE_CTL | EQ_W0_BACKLOG; + eq.__w0 = cpu_to_be32((be32_to_cpu(eq.__w0) & EQ_W0_FIRMWARE) + | EQ_W0_VALID | EQ_W0_SILENT_ESCALATE | + EQ_W0_ESCALATE_CTL | EQ_W0_BACKLOG); /* W1: Mark ESn as 01, ESe as 00 */ - eq.w1 &= ~EQ_W1_ESn_P; - eq.w1 |= EQ_W1_ESn_Q; - eq.w1 &= ~(EQ_W1_ESe); - } else if (eq.w0 & EQ_W0_SILENT_ESCALATE) + eq.__w1 = cpu_to_be32(((be32_to_cpu(eq.__w1) & ~EQ_W1_ESn_P) + | EQ_W1_ESn_Q) & ~EQ_W1_ESe); + } else if (be32_to_cpu(eq.__w0) & EQ_W0_SILENT_ESCALATE) xive_cleanup_eq(&eq); if (!memcmp(eq_orig, &eq, sizeof(eq))) @@ -4417,19 +4438,19 @@ static int64_t xive_setup_silent_gather(uint64_t vp_id, bool enable) eq = *eq_orig; if (enable) { /* Set new "u" bit */ - eq.w0 |= EQ_W0_UNCOND_ESCALATE; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) | EQ_W0_UNCOND_ESCALATE); /* Re-route escalation interrupt (previous * route is lost !) to the gather queue */ - eq.w4 = SETFIELD(EQ_W4_ESC_EQ_BLOCK, - eq.w4, blk); - eq.w4 = SETFIELD(EQ_W4_ESC_EQ_INDEX, - eq.w4, idx + 7); - } else if (eq.w0 & EQ_W0_UNCOND_ESCALATE) { + eq.__w4 = cpu_to_be32(SETFIELD(EQ_W4_ESC_EQ_BLOCK, + be32_to_cpu(eq.__w4), blk)); + eq.__w4 = cpu_to_be32(SETFIELD(EQ_W4_ESC_EQ_INDEX, + be32_to_cpu(eq.__w4), idx + 7)); + } else if (be32_to_cpu(eq.__w0) & EQ_W0_UNCOND_ESCALATE) { /* Clear the "u" bit, disable escalations if it was set */ - eq.w0 &= ~EQ_W0_UNCOND_ESCALATE; - eq.w0 &= ~EQ_W0_ESCALATE_CTL; + eq.__w0 = cpu_to_be32(be32_to_cpu(eq.__w0) & + ~(EQ_W0_UNCOND_ESCALATE | EQ_W0_ESCALATE_CTL)); } if (!memcmp(eq_orig, &eq, sizeof(eq))) continue; @@ -4470,16 +4491,16 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id, vp_new = *vp; if (flags & OPAL_XIVE_VP_ENABLED) { - vp_new.w0 |= VP_W0_VALID; - vp_new.w6 = report_cl_pair >> 32; - vp_new.w7 = report_cl_pair & 0xffffffff; + vp_new.__w0 = cpu_to_be32(be32_to_cpu(vp_new.__w0) | VP_W0_VALID); + vp_new.__w6 = cpu_to_be32(report_cl_pair >> 32); + vp_new.__w7 = cpu_to_be32(report_cl_pair & 0xffffffff); if (flags & OPAL_XIVE_VP_SINGLE_ESCALATION) rc = xive_setup_silent_gather(vp_id, true); else rc = xive_setup_silent_gather(vp_id, false); } else { - vp_new.w0 = vp_new.w6 = vp_new.w7 = 0; + vp_new.__w0 = vp_new.__w6 = vp_new.__w7 = 0; rc = xive_setup_silent_gather(vp_id, false); } @@ -4504,7 +4525,7 @@ bail: return rc; } -static int64_t opal_xive_get_vp_state(uint64_t vp_id, uint64_t *out_state) +static int64_t opal_xive_get_vp_state(uint64_t vp_id, __be64 *out_state) { struct xive *x; struct xive_vp *vp; @@ -4530,14 +4551,14 @@ static int64_t opal_xive_get_vp_state(uint64_t vp_id, uint64_t *out_state) if (rc) return rc; - if (!(vp->w0 & VP_W0_VALID)) + if (!(be32_to_cpu(vp->__w0) & VP_W0_VALID)) return OPAL_WRONG_STATE; /* * Return word4 and word5 which contain the saved HW thread * context. The IPB register is all we care for now on P9. */ - *out_state = (((uint64_t)vp->w4) << 32) | vp->w5; + *out_state = cpu_to_be64((((uint64_t)be32_to_cpu(vp->__w4)) << 32) | be32_to_cpu(vp->__w5)); return OPAL_SUCCESS; } @@ -4627,7 +4648,7 @@ static void xive_cleanup_vp_ind(struct xive *x) xive_dbg(x, "Cleaning up %d VP ind entries...\n", x->vp_ind_count); for (i = 0; i < x->vp_ind_count; i++) { - if (x->vp_ind_base[i] & VSD_FIRMWARE) { + if (be64_to_cpu(x->vp_ind_base[i]) & VSD_FIRMWARE) { xive_dbg(x, " %04x ... skip (firmware)\n", i); continue; } @@ -4645,7 +4666,7 @@ static void xive_cleanup_eq_ind(struct xive *x) xive_dbg(x, "Cleaning up %d EQ ind entries...\n", x->eq_ind_count); for (i = 0; i < x->eq_ind_count; i++) { - if (x->eq_ind_base[i] & VSD_FIRMWARE) { + if (be64_to_cpu(x->eq_ind_base[i]) & VSD_FIRMWARE) { xive_dbg(x, " %04x ... skip (firmware)\n", i); continue; } @@ -4692,25 +4713,28 @@ static void xive_reset_one(struct xive *x) eq_firmware = false; for (j = 0; j < 8; j++) { uint32_t idx = (i << 3) | j; + uint32_t w0; eq = xive_get_eq(x, idx); if (!eq) continue; + w0 = be32_to_cpu(eq->__w0); + /* We need to preserve the firmware bit, otherwise * we will incorrectly free the EQs that are reserved * for the physical CPUs */ - if (eq->w0 & EQ_W0_VALID) { - if (!(eq->w0 & EQ_W0_FIRMWARE)) + if (w0 & EQ_W0_VALID) { + if (!(w0 & EQ_W0_FIRMWARE)) xive_dbg(x, "EQ 0x%x:0x%x is valid at reset: %08x %08x\n", - x->block_id, idx, eq->w0, eq->w1); + x->block_id, idx, w0, be32_to_cpu(eq->__w1)); eq0 = *eq; xive_cleanup_eq(&eq0); xive_eqc_cache_update(x, x->block_id, idx, 0, 4, &eq0, false, true); } - if (eq->w0 & EQ_W0_FIRMWARE) + if (w0 & EQ_W0_FIRMWARE) eq_firmware = true; } if (!eq_firmware) @@ -4747,7 +4771,7 @@ static void xive_reset_one(struct xive *x) #endif /* Is the VP valid ? */ vp = xive_get_vp(x, i); - if (!vp || !(vp->w0 & VP_W0_VALID)) + if (!vp || !(be32_to_cpu(vp->__w0) & VP_W0_VALID)) continue; /* Clear it */ @@ -4935,16 +4959,16 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) } /* VP must be disabled */ - if (vp->w0 & VP_W0_VALID) { + if (be32_to_cpu(vp->__w0) & VP_W0_VALID) { prlog(PR_ERR, "XIVE: freeing active VP %d\n", vp_id); return OPAL_XIVE_FREE_ACTIVE; } /* Not populated */ - if (vp->w1 == 0) + if (vp->__w1 == 0) continue; - eq_blk = vp->w1 >> 28; - eq_idx = vp->w1 & 0x0fffffff; + eq_blk = be32_to_cpu(vp->__w1) >> 28; + eq_idx = be32_to_cpu(vp->__w1) & 0x0fffffff; lock(&x->lock); @@ -4955,7 +4979,7 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) struct xive *eq_x = xive_from_vc_blk(eq_blk); struct xive_eq eq, *orig_eq = xive_get_eq(eq_x, eq_idx + j); - if (!(orig_eq->w0 & EQ_W0_VALID)) + if (!(be32_to_cpu(orig_eq->__w0) & EQ_W0_VALID)) continue; prlog(PR_WARNING, "XIVE: freeing VP %d with queue %d active\n", @@ -4966,7 +4990,7 @@ static int64_t opal_xive_free_vp_block(uint64_t vp_base) } /* Mark it not populated so we don't try to free it again */ - vp->w1 = 0; + vp->__w1 = 0; if (eq_blk != blk) { prerror("XIVE: Block mismatch trying to free EQs\n"); @@ -5043,8 +5067,8 @@ static int64_t opal_xive_alloc_vp_block(uint32_t alloc_order) * it out of the cache. */ memset(vp, 0, sizeof(*vp)); - vp->w1 = (blk << 28) | eqs; - vp->w5 = 0xff000000; + vp->__w1 = cpu_to_be32((blk << 28) | eqs); + vp->__w5 = cpu_to_be32(0xff000000); } return vp_base; fail: @@ -5081,7 +5105,7 @@ static int64_t xive_try_allocate_irq(struct xive *x) unlock(&x->lock); return OPAL_PARAMETER; } - ive->w = IVE_VALID | IVE_MASKED | SETFIELD(IVE_EQ_DATA, 0ul, girq); + ive->__w = cpu_to_be64(IVE_VALID | IVE_MASKED | SETFIELD(IVE_EQ_DATA, 0ul, girq)); unlock(&x->lock); return girq; @@ -5150,7 +5174,7 @@ static int64_t opal_xive_free_irq(uint32_t girq) xive_update_irq_mask(s, girq - s->esb_base, true); /* Mark the IVE masked and invalid */ - ive->w = IVE_MASKED | IVE_VALID; + ive->__w = cpu_to_be64(IVE_MASKED | IVE_VALID); xive_ivc_scrub(x, x->block_id, idx); /* Free it */ @@ -5290,7 +5314,7 @@ static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir) false, false); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); prlog(PR_INFO, "CPU[%04x]: EQ @%p W0=%08x W1=%08x qbuf @%p\n", - pir, eq, eq->w0, eq->w1, xs->eqbuf); + pir, eq, be32_to_cpu(eq->__w0), be32_to_cpu(eq->__w1), xs->eqbuf); return OPAL_SUCCESS; } diff --git a/include/xive.h b/include/xive.h index b88cdabea..95113efa8 100644 --- a/include/xive.h +++ b/include/xive.h @@ -382,7 +382,7 @@ struct xive_ive { /* Use a single 64-bit definition to make it easier to * perform atomic updates */ - uint64_t w; + __be64 __w; #define IVE_VALID PPC_BIT(0) #define IVE_EQ_BLOCK PPC_BITMASK(4,7) /* Destination EQ block# */ #define IVE_EQ_INDEX PPC_BITMASK(8,31) /* Destination EQ index */ @@ -392,7 +392,7 @@ struct xive_ive { /* EQ */ struct xive_eq { - uint32_t w0; + __be32 __w0; #define EQ_W0_VALID PPC_BIT32(0) /* "v" bit */ #define EQ_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */ #define EQ_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */ @@ -407,7 +407,7 @@ struct xive_eq { #define EQ_QSIZE_4K 0 #define EQ_QSIZE_64K 4 #define EQ_W0_HWDEP PPC_BITMASK32(24,31) - uint32_t w1; + __be32 __w1; #define EQ_W1_ESn PPC_BITMASK32(0,1) #define EQ_W1_ESn_P PPC_BIT32(0) #define EQ_W1_ESn_Q PPC_BIT32(1) @@ -416,21 +416,21 @@ struct xive_eq { #define EQ_W1_ESe_Q PPC_BIT32(3) #define EQ_W1_GENERATION PPC_BIT32(9) #define EQ_W1_PAGE_OFF PPC_BITMASK32(10,31) - uint32_t w2; + __be32 __w2; #define EQ_W2_MIGRATION_REG PPC_BITMASK32(0,3) #define EQ_W2_OP_DESC_HI PPC_BITMASK32(4,31) - uint32_t w3; + __be32 __w3; #define EQ_W3_OP_DESC_LO PPC_BITMASK32(0,31) - uint32_t w4; + __be32 __w4; #define EQ_W4_ESC_EQ_BLOCK PPC_BITMASK32(4,7) #define EQ_W4_ESC_EQ_INDEX PPC_BITMASK32(8,31) - uint32_t w5; + __be32 __w5; #define EQ_W5_ESC_EQ_DATA PPC_BITMASK32(1,31) - uint32_t w6; + __be32 __w6; #define EQ_W6_FORMAT_BIT PPC_BIT32(8) #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) - uint32_t w7; + __be32 __w7; #define EQ_W7_F0_IGNORE PPC_BIT32(0) #define EQ_W7_F0_BLK_GROUPING PPC_BIT32(1) #define EQ_W7_F0_PRIORITY PPC_BITMASK32(8,15) @@ -440,24 +440,24 @@ struct xive_eq { /* VP */ struct xive_vp { - uint32_t w0; + __be32 __w0; #define VP_W0_VALID PPC_BIT32(0) - uint32_t w1; - uint32_t w2; - uint32_t w3; - uint32_t w4; - uint32_t w5; - uint32_t w6; - uint32_t w7; - uint32_t w8; + __be32 __w1; + __be32 __w2; + __be32 __w3; + __be32 __w4; + __be32 __w5; + __be32 __w6; + __be32 __w7; + __be32 __w8; #define VP_W8_GRP_VALID PPC_BIT32(0) - uint32_t w9; - uint32_t wa; - uint32_t wb; - uint32_t wc; - uint32_t wd; - uint32_t we; - uint32_t wf; + __be32 __w9; + __be32 __wa; + __be32 __wb; + __be32 __wc; + __be32 __wd; + __be32 __we; + __be32 __wf; }; /* Internal APIs to other modules */ From patchwork Wed Oct 9 23:49:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWMs2gFKz9s7T for ; Thu, 10 Oct 2019 10:56:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="exWwpK5y"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWMs1hFXzDqYp for ; Thu, 10 Oct 2019 10:56:41 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="exWwpK5y"; dkim-atps=neutral Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWHz64djzDqYW for ; Thu, 10 Oct 2019 10:53:19 +1100 (AEDT) Received: by mail-pf1-x441.google.com with SMTP id y72so2639691pfb.12 for ; Wed, 09 Oct 2019 16:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZeAj+Gp2gd9lF13z6cDn5dXz2VV32azSE3mc5uqX6M=; b=exWwpK5yHqXSkHh2O0bjVyhjr0SoqHkJ7fqYd/Nm048r+XQPx3yg0+U06mAiVGifo4 2E0wWRTFz3XbPlssR1S7UKbrPxf723zVX+IGNl9yCjsWmyBI9zojt2QOWDB4Ooo73p8s Eg4IKN0l3g1lQGNVwpLhY1J7Vzgb1CPh744gT4ZI/YcHLHWzvIRR5Of7Pc7FAu/gtNK0 6jnjoX+jW8KWHzla8MM2dFk385vChTUNT73h/0zVjomQyl8iPU1i42/y+Gu5MGneQMf4 0VZqhA8Nfnu4l4ZmrYBOGJowpBee+2zKWiaINtgNbrV6t/xViVJujxWTB71iaEeQOKSO BRLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vZeAj+Gp2gd9lF13z6cDn5dXz2VV32azSE3mc5uqX6M=; b=poe4gl8qAH+OK6JOSUvsv/G0ES3hWgRlAJvJA1Fmou/a4DQDfrfmVqJLbWfI7axakA qM5mSpDqcgcqsiGpuSKXoKIQfcHy9my56O9m8pkEyPoNK/Y6zirYbnILhcs7mM5lslMT 0vkcKGzFv9YbkLg2BqUH5/V0tOyaHAaQSXuvNXDoSfx+/NlSsF4ixwehzAFrQJEuigqq RKG9zlk4SynrbebEvMoyWnqwybGBCIJqPgf5P7igaLdBGq8Z5vTG5MlY2qYgS0ByiELo cX7UPvm/tDooMUFTEu1pvtwzUNaT41bWzZo6VZJ+NPOhIIul+QNQmu3fd5LIfrLBY8jT Pgmg== X-Gm-Message-State: APjAAAVi/fTHg96um8uSTyJL32P7+VFJZNzQtCkdhCzV1Ywg0DzDg10a lwybGpTSSDqrIbZlKfy+iLKABMdE X-Google-Smtp-Source: APXvYqy9SVD8hCj/XUIoOEQt0NaPG3/qnEZB2s/o+vUTcgaoZ/2HvP2aEAEnciUM9JqIIssiLdIy/g== X-Received: by 2002:a17:90a:8c02:: with SMTP id a2mr7202856pjo.79.1570665197269; Wed, 09 Oct 2019 16:53:17 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:16 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:47 +1000 Message-Id: <20191009234951.2850-12-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 11/15] phb4: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert phb4 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/phb4.c | 321 +++++++++++++++++++++++++------------------------ include/phb4.h | 2 +- 2 files changed, 166 insertions(+), 157 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 3c71427ae..d202b4cfa 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -273,7 +273,7 @@ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn, return OPAL_HARDWARE; /* Fetch the PE# from cache */ - *pe = p->tbl_rtt[bdfn]; + *pe = be16_to_cpu(p->tbl_rtt[bdfn]); return OPAL_SUCCESS; } @@ -923,7 +923,7 @@ static void phb4_init_ioda_cache(struct phb4 *p) * and this occurs before PEs have been assigned. */ for (i = 0; i < RTT_TABLE_ENTRIES; i++) - p->tbl_rtt[i] = PHB4_RESERVED_PE_NUM(p); + p->tbl_rtt[i] = cpu_to_be16(PHB4_RESERVED_PE_NUM(p)); memset(p->tbl_peltv, 0x0, p->tbl_peltv_size); memset(p->tve_cache, 0x0, sizeof(p->tve_cache)); @@ -1748,110 +1748,123 @@ static void phb4_err_clear(struct phb4 *p) static void phb4_read_phb_status(struct phb4 *p, struct OpalIoPhb4ErrorData *stat) { - uint16_t val = 0; uint32_t i; uint64_t *pPEST; + uint16_t __16; + uint32_t __32; + uint64_t __64; memset(stat, 0, sizeof(struct OpalIoPhb4ErrorData)); /* Error data common part */ - stat->common.version = OPAL_PHB_ERROR_DATA_VERSION_1; - stat->common.ioType = OPAL_PHB_ERROR_DATA_TYPE_PHB4; - stat->common.len = sizeof(struct OpalIoPhb4ErrorData); + stat->common.version = cpu_to_be32(OPAL_PHB_ERROR_DATA_VERSION_1); + stat->common.ioType = cpu_to_be32(OPAL_PHB_ERROR_DATA_TYPE_PHB4); + stat->common.len = cpu_to_be32(sizeof(struct OpalIoPhb4ErrorData)); /* Use ASB for config space if the PHB is fenced */ if (p->flags & PHB4_AIB_FENCED) p->flags |= PHB4_CFG_USE_ASB; /* Grab RC bridge control, make it 32-bit */ - phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &val); - stat->brdgCtl = val; + phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &__16); + stat->brdgCtl = cpu_to_be32(__16); /* * Grab various RC PCIe capability registers. All device, slot * and link status are 16-bit, so we grab the pair control+status * for each of them */ - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, - &stat->deviceStatus); - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, - &stat->slotStatus); - phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, - &stat->linkStatus); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, &__32); + stat->deviceStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, &__32); + stat->slotStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, &__32); + stat->linkStatus = cpu_to_be32(__32); /* * I assume those are the standard config space header, cmd & status * together makes 32-bit. Secondary status is 16-bit so I'll clear * the top on that one */ - phb4_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); - phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &val); - stat->devSecStatus = val; + phb4_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &__32); + stat->devCmdStatus = cpu_to_be32(__32); + phb4_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &__16); + stat->devSecStatus = cpu_to_be32(__32); /* Grab a bunch of AER regs */ - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, - &stat->rootErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, - &stat->uncorrErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, - &stat->corrErrorStatus); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, - &stat->tlpHdr1); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, - &stat->tlpHdr2); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, - &stat->tlpHdr3); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, - &stat->tlpHdr4); - phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, - &stat->sourceId); + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, &__32); + stat->rootErrorStatus = cpu_to_be32(__32); + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, &__32); + stat->uncorrErrorStatus = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, &__32); + stat->corrErrorStatus = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, &__32); + stat->tlpHdr1 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, &__32); + stat->tlpHdr2 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, &__32); + stat->tlpHdr3 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, &__32); + stat->tlpHdr4 = cpu_to_be32(__32); + + phb4_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, &__32); + stat->sourceId = cpu_to_be32(__32); + /* PEC NFIR, same as P8/PHB3 */ - xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &stat->nFir); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x3, &stat->nFirMask); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x8, &stat->nFirWOF); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &__64); + stat->nFir = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x3, &__64); + stat->nFirMask = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_stk_xscom + 0x8, &__64); + stat->nFirWOF = cpu_to_be64(__64); /* PHB4 inbound and outbound error Regs */ - stat->phbPlssr = phb4_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS); - stat->phbCsr = phb4_read_reg_asb(p, PHB_DMA_CHAN_STATUS); - stat->lemFir = phb4_read_reg_asb(p, PHB_LEM_FIR_ACCUM); - stat->lemErrorMask = phb4_read_reg_asb(p, PHB_LEM_ERROR_MASK); - stat->lemWOF = phb4_read_reg_asb(p, PHB_LEM_WOF); - stat->phbErrorStatus = phb4_read_reg_asb(p, PHB_ERR_STATUS); - stat->phbFirstErrorStatus = phb4_read_reg_asb(p, PHB_ERR1_STATUS); - stat->phbErrorLog0 = phb4_read_reg_asb(p, PHB_ERR_LOG_0); - stat->phbErrorLog1 = phb4_read_reg_asb(p, PHB_ERR_LOG_1); - stat->phbTxeErrorStatus = phb4_read_reg_asb(p, PHB_TXE_ERR_STATUS); - stat->phbTxeFirstErrorStatus = phb4_read_reg_asb(p, PHB_TXE_ERR1_STATUS); - stat->phbTxeErrorLog0 = phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_0); - stat->phbTxeErrorLog1 = phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_1); - stat->phbRxeArbErrorStatus = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_STATUS); - stat->phbRxeArbFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR1_STATUS); - stat->phbRxeArbErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_0); - stat->phbRxeArbErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_1); - stat->phbRxeMrgErrorStatus = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_STATUS); - stat->phbRxeMrgFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR1_STATUS); - stat->phbRxeMrgErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_0); - stat->phbRxeMrgErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_1); - stat->phbRxeTceErrorStatus = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_STATUS); - stat->phbRxeTceFirstErrorStatus = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR1_STATUS); - stat->phbRxeTceErrorLog0 = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_0); - stat->phbRxeTceErrorLog1 = phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_1); + stat->phbPlssr = cpu_to_be64(phb4_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS)); + stat->phbCsr = cpu_to_be64(phb4_read_reg_asb(p, PHB_DMA_CHAN_STATUS)); + stat->lemFir = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_FIR_ACCUM)); + stat->lemErrorMask = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_ERROR_MASK)); + stat->lemWOF = cpu_to_be64(phb4_read_reg_asb(p, PHB_LEM_WOF)); + stat->phbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_STATUS)); + stat->phbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR1_STATUS)); + stat->phbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_LOG_0)); + stat->phbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_ERR_LOG_1)); + stat->phbTxeErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_STATUS)); + stat->phbTxeFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR1_STATUS)); + stat->phbTxeErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_0)); + stat->phbTxeErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_TXE_ERR_LOG_1)); + stat->phbRxeArbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_STATUS)); + stat->phbRxeArbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR1_STATUS)); + stat->phbRxeArbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_0)); + stat->phbRxeArbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_ARB_ERR_LOG_1)); + stat->phbRxeMrgErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_STATUS)); + stat->phbRxeMrgFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR1_STATUS)); + stat->phbRxeMrgErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_0)); + stat->phbRxeMrgErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_MRG_ERR_LOG_1)); + stat->phbRxeTceErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_STATUS)); + stat->phbRxeTceFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR1_STATUS)); + stat->phbRxeTceErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_0)); + stat->phbRxeTceErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_RXE_TCE_ERR_LOG_1)); /* PHB4 REGB error registers */ - stat->phbPblErrorStatus = phb4_read_reg_asb(p, PHB_PBL_ERR_STATUS); - stat->phbPblFirstErrorStatus = phb4_read_reg_asb(p, PHB_PBL_ERR1_STATUS); - stat->phbPblErrorLog0 = phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_0); - stat->phbPblErrorLog1 = phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_1); + stat->phbPblErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_STATUS)); + stat->phbPblFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR1_STATUS)); + stat->phbPblErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_0)); + stat->phbPblErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PBL_ERR_LOG_1)); - stat->phbPcieDlpErrorStatus = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERR_STATUS); - stat->phbPcieDlpErrorLog1 = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG1); - stat->phbPcieDlpErrorLog2 = phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG2); + stat->phbPcieDlpErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERR_STATUS)); + stat->phbPcieDlpErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG1)); + stat->phbPcieDlpErrorLog2 = cpu_to_be64(phb4_read_reg_asb(p, PHB_PCIE_DLP_ERRLOG2)); - stat->phbRegbErrorStatus = phb4_read_reg_asb(p, PHB_REGB_ERR_STATUS); - stat->phbRegbFirstErrorStatus = phb4_read_reg_asb(p, PHB_REGB_ERR1_STATUS); - stat->phbRegbErrorLog0 = phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_0); - stat->phbRegbErrorLog1 = phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_1); + stat->phbRegbErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_STATUS)); + stat->phbRegbFirstErrorStatus = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR1_STATUS)); + stat->phbRegbErrorLog0 = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_0)); + stat->phbRegbErrorLog1 = cpu_to_be64(phb4_read_reg_asb(p, PHB_REGB_ERR_LOG_1)); /* * Grab PESTA & B content. The error bit (bit#0) should @@ -1861,13 +1874,13 @@ static void phb4_read_phb_status(struct phb4 *p, pPEST = (uint64_t *)p->tbl_pest; phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, true); for (i = 0; i < p->max_num_pes; i++) { - stat->pestA[i] = phb4_read_reg_asb(p, PHB_IODA_DATA0); + stat->pestA[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); stat->pestA[i] |= pPEST[2 * i]; } phb4_ioda_sel(p, IODA3_TBL_PESTB, 0, true); for (i = 0; i < p->max_num_pes; i++) { - stat->pestB[i] = phb4_read_reg_asb(p, PHB_IODA_DATA0); + stat->pestB[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); stat->pestB[i] |= pPEST[2 * i + 1]; } } @@ -2017,17 +2030,17 @@ static void phb4_eeh_dump_regs(struct phb4 *p) } phb4_read_phb_status(p, s); - PHBERR(p, " brdgCtl = %08x\n", s->brdgCtl); + PHBERR(p, " brdgCtl = %08x\n", be32_to_cpu(s->brdgCtl)); /* PHB4 cfg regs */ - PHBERR(p, " deviceStatus = %08x\n", s->deviceStatus); - PHBERR(p, " slotStatus = %08x\n", s->slotStatus); - PHBERR(p, " linkStatus = %08x\n", s->linkStatus); - PHBERR(p, " devCmdStatus = %08x\n", s->devCmdStatus); - PHBERR(p, " devSecStatus = %08x\n", s->devSecStatus); - PHBERR(p, " rootErrorStatus = %08x\n", s->rootErrorStatus); - PHBERR(p, " corrErrorStatus = %08x\n", s->corrErrorStatus); - PHBERR(p, " uncorrErrorStatus = %08x\n", s->uncorrErrorStatus); + PHBERR(p, " deviceStatus = %08x\n", be32_to_cpu(s->deviceStatus)); + PHBERR(p, " slotStatus = %08x\n", be32_to_cpu(s->slotStatus)); + PHBERR(p, " linkStatus = %08x\n", be32_to_cpu(s->linkStatus)); + PHBERR(p, " devCmdStatus = %08x\n", be32_to_cpu(s->devCmdStatus)); + PHBERR(p, " devSecStatus = %08x\n", be32_to_cpu(s->devSecStatus)); + PHBERR(p, " rootErrorStatus = %08x\n", be32_to_cpu(s->rootErrorStatus)); + PHBERR(p, " corrErrorStatus = %08x\n", be32_to_cpu(s->corrErrorStatus)); + PHBERR(p, " uncorrErrorStatus = %08x\n", be32_to_cpu(s->uncorrErrorStatus)); /* Two non OPAL API registers that are useful */ phb4_pcicfg_read16(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, ®); @@ -2041,53 +2054,53 @@ static void phb4_eeh_dump_regs(struct phb4 *p) PHBERR(p, " tlpHdr2 = %08x\n", bswap_32(s->tlpHdr2)); PHBERR(p, " tlpHdr3 = %08x\n", bswap_32(s->tlpHdr3)); PHBERR(p, " tlpHdr4 = %08x\n", bswap_32(s->tlpHdr4)); - PHBERR(p, " sourceId = %08x\n", s->sourceId); - PHBERR(p, " nFir = %016llx\n", s->nFir); - PHBERR(p, " nFirMask = %016llx\n", s->nFirMask); - PHBERR(p, " nFirWOF = %016llx\n", s->nFirWOF); - PHBERR(p, " phbPlssr = %016llx\n", s->phbPlssr); - PHBERR(p, " phbCsr = %016llx\n", s->phbCsr); - PHBERR(p, " lemFir = %016llx\n", s->lemFir); - PHBERR(p, " lemErrorMask = %016llx\n", s->lemErrorMask); - PHBERR(p, " lemWOF = %016llx\n", s->lemWOF); - PHBERR(p, " phbErrorStatus = %016llx\n", s->phbErrorStatus); - PHBERR(p, " phbFirstErrorStatus = %016llx\n", s->phbFirstErrorStatus); - PHBERR(p, " phbErrorLog0 = %016llx\n", s->phbErrorLog0); - PHBERR(p, " phbErrorLog1 = %016llx\n", s->phbErrorLog1); - PHBERR(p, " phbTxeErrorStatus = %016llx\n", s->phbTxeErrorStatus); - PHBERR(p, " phbTxeFirstErrorStatus = %016llx\n", s->phbTxeFirstErrorStatus); - PHBERR(p, " phbTxeErrorLog0 = %016llx\n", s->phbTxeErrorLog0); - PHBERR(p, " phbTxeErrorLog1 = %016llx\n", s->phbTxeErrorLog1); - PHBERR(p, " phbRxeArbErrorStatus = %016llx\n", s->phbRxeArbErrorStatus); - PHBERR(p, "phbRxeArbFrstErrorStatus = %016llx\n", s->phbRxeArbFirstErrorStatus); - PHBERR(p, " phbRxeArbErrorLog0 = %016llx\n", s->phbRxeArbErrorLog0); - PHBERR(p, " phbRxeArbErrorLog1 = %016llx\n", s->phbRxeArbErrorLog1); - PHBERR(p, " phbRxeMrgErrorStatus = %016llx\n", s->phbRxeMrgErrorStatus); - PHBERR(p, "phbRxeMrgFrstErrorStatus = %016llx\n", s->phbRxeMrgFirstErrorStatus); - PHBERR(p, " phbRxeMrgErrorLog0 = %016llx\n", s->phbRxeMrgErrorLog0); - PHBERR(p, " phbRxeMrgErrorLog1 = %016llx\n", s->phbRxeMrgErrorLog1); - PHBERR(p, " phbRxeTceErrorStatus = %016llx\n", s->phbRxeTceErrorStatus); - PHBERR(p, "phbRxeTceFrstErrorStatus = %016llx\n", s->phbRxeTceFirstErrorStatus); - PHBERR(p, " phbRxeTceErrorLog0 = %016llx\n", s->phbRxeTceErrorLog0); - PHBERR(p, " phbRxeTceErrorLog1 = %016llx\n", s->phbRxeTceErrorLog1); - PHBERR(p, " phbPblErrorStatus = %016llx\n", s->phbPblErrorStatus); - PHBERR(p, " phbPblFirstErrorStatus = %016llx\n", s->phbPblFirstErrorStatus); - PHBERR(p, " phbPblErrorLog0 = %016llx\n", s->phbPblErrorLog0); - PHBERR(p, " phbPblErrorLog1 = %016llx\n", s->phbPblErrorLog1); - PHBERR(p, " phbPcieDlpErrorLog1 = %016llx\n", s->phbPcieDlpErrorLog1); - PHBERR(p, " phbPcieDlpErrorLog2 = %016llx\n", s->phbPcieDlpErrorLog2); - PHBERR(p, " phbPcieDlpErrorStatus = %016llx\n", s->phbPcieDlpErrorStatus); - - PHBERR(p, " phbRegbErrorStatus = %016llx\n", s->phbRegbErrorStatus); - PHBERR(p, " phbRegbFirstErrorStatus = %016llx\n", s->phbRegbFirstErrorStatus); - PHBERR(p, " phbRegbErrorLog0 = %016llx\n", s->phbRegbErrorLog0); - PHBERR(p, " phbRegbErrorLog1 = %016llx\n", s->phbRegbErrorLog1); + PHBERR(p, " sourceId = %08x\n", be32_to_cpu(s->sourceId)); + PHBERR(p, " nFir = %016llx\n", be64_to_cpu(s->nFir)); + PHBERR(p, " nFirMask = %016llx\n", be64_to_cpu(s->nFirMask)); + PHBERR(p, " nFirWOF = %016llx\n", be64_to_cpu(s->nFirWOF)); + PHBERR(p, " phbPlssr = %016llx\n", be64_to_cpu(s->phbPlssr)); + PHBERR(p, " phbCsr = %016llx\n", be64_to_cpu(s->phbCsr)); + PHBERR(p, " lemFir = %016llx\n", be64_to_cpu(s->lemFir)); + PHBERR(p, " lemErrorMask = %016llx\n", be64_to_cpu(s->lemErrorMask)); + PHBERR(p, " lemWOF = %016llx\n", be64_to_cpu(s->lemWOF)); + PHBERR(p, " phbErrorStatus = %016llx\n", be64_to_cpu(s->phbErrorStatus)); + PHBERR(p, " phbFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbFirstErrorStatus)); + PHBERR(p, " phbErrorLog0 = %016llx\n", be64_to_cpu(s->phbErrorLog0)); + PHBERR(p, " phbErrorLog1 = %016llx\n", be64_to_cpu(s->phbErrorLog1)); + PHBERR(p, " phbTxeErrorStatus = %016llx\n", be64_to_cpu(s->phbTxeErrorStatus)); + PHBERR(p, " phbTxeFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbTxeFirstErrorStatus)); + PHBERR(p, " phbTxeErrorLog0 = %016llx\n", be64_to_cpu(s->phbTxeErrorLog0)); + PHBERR(p, " phbTxeErrorLog1 = %016llx\n", be64_to_cpu(s->phbTxeErrorLog1)); + PHBERR(p, " phbRxeArbErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeArbErrorStatus)); + PHBERR(p, "phbRxeArbFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeArbFirstErrorStatus)); + PHBERR(p, " phbRxeArbErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeArbErrorLog0)); + PHBERR(p, " phbRxeArbErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeArbErrorLog1)); + PHBERR(p, " phbRxeMrgErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorStatus)); + PHBERR(p, "phbRxeMrgFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeMrgFirstErrorStatus)); + PHBERR(p, " phbRxeMrgErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorLog0)); + PHBERR(p, " phbRxeMrgErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeMrgErrorLog1)); + PHBERR(p, " phbRxeTceErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeTceErrorStatus)); + PHBERR(p, "phbRxeTceFrstErrorStatus = %016llx\n", be64_to_cpu(s->phbRxeTceFirstErrorStatus)); + PHBERR(p, " phbRxeTceErrorLog0 = %016llx\n", be64_to_cpu(s->phbRxeTceErrorLog0)); + PHBERR(p, " phbRxeTceErrorLog1 = %016llx\n", be64_to_cpu(s->phbRxeTceErrorLog1)); + PHBERR(p, " phbPblErrorStatus = %016llx\n", be64_to_cpu(s->phbPblErrorStatus)); + PHBERR(p, " phbPblFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbPblFirstErrorStatus)); + PHBERR(p, " phbPblErrorLog0 = %016llx\n", be64_to_cpu(s->phbPblErrorLog0)); + PHBERR(p, " phbPblErrorLog1 = %016llx\n", be64_to_cpu(s->phbPblErrorLog1)); + PHBERR(p, " phbPcieDlpErrorLog1 = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorLog1)); + PHBERR(p, " phbPcieDlpErrorLog2 = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorLog2)); + PHBERR(p, " phbPcieDlpErrorStatus = %016llx\n", be64_to_cpu(s->phbPcieDlpErrorStatus)); + + PHBERR(p, " phbRegbErrorStatus = %016llx\n", be64_to_cpu(s->phbRegbErrorStatus)); + PHBERR(p, " phbRegbFirstErrorStatus = %016llx\n", be64_to_cpu(s->phbRegbFirstErrorStatus)); + PHBERR(p, " phbRegbErrorLog0 = %016llx\n", be64_to_cpu(s->phbRegbErrorLog0)); + PHBERR(p, " phbRegbErrorLog1 = %016llx\n", be64_to_cpu(s->phbRegbErrorLog1)); for (i = 0; i < p->max_num_pes; i++) { if (!s->pestA[i] && !s->pestB[i]) continue; PHBERR(p, " PEST[%03x] = %016llx %016llx\n", - i, s->pestA[i], s->pestB[i]); + i, be64_to_cpu(s->pestA[i]), be64_to_cpu(s->pestB[i])); } free(s); } @@ -2131,7 +2144,7 @@ static int64_t phb4_set_pe(struct phb *phb, /* Map or unmap the RTT range */ for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++) if ((idx & mask) == (bdfn & mask)) - p->tbl_rtt[idx] = pe_number; + p->tbl_rtt[idx] = cpu_to_be16(pe_number); /* Invalidate the RID Translation Cache (RTC) inside the PHB */ out_be64(p->regs + PHB_RTC_INVALIDATE, PHB_RTC_INVALIDATE_ALL); @@ -3450,7 +3463,7 @@ static uint64_t phb4_get_pesta(struct phb4 *p, uint64_t pe_number) phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false); pesta = phb4_read_reg(p, PHB_IODA_DATA0); if (pesta & IODA3_PESTA_MMIO_FROZEN) - pesta |= pPEST[2*pe_number]; + pesta |= be64_to_cpu(pPEST[2*pe_number]); return pesta; } @@ -3808,13 +3821,13 @@ static int64_t phb4_err_inject_cfg(struct phb4 *phb, uint64_t pe_number, ctrl = PHB_PAPR_ERR_INJ_CTL_CFG; for (bdfn = 0; bdfn < RTT_TABLE_ENTRIES; bdfn++) { - if (phb->tbl_rtt[bdfn] != pe_number) + if (be16_to_cpu(phb->tbl_rtt[bdfn]) != pe_number) continue; /* The PE can be associated with PCI bus or device */ is_bus_pe = false; if ((bdfn + 8) < RTT_TABLE_ENTRIES && - phb->tbl_rtt[bdfn + 8] == pe_number) + be16_to_cpu(phb->tbl_rtt[bdfn + 8]) == pe_number) is_bus_pe = true; /* Figure out the PCI config address */ @@ -5344,7 +5357,7 @@ static void phb4_allocate_tables(struct phb4 *p) p->tbl_rtt = local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE); assert(p->tbl_rtt); for (i = 0; i < RTT_TABLE_ENTRIES; i++) - p->tbl_rtt[i] = PHB4_RESERVED_PE_NUM(p); + p->tbl_rtt[i] = cpu_to_be16(PHB4_RESERVED_PE_NUM(p)); p->tbl_peltv = local_alloc(p->chip_id, p->tbl_peltv_size, p->tbl_peltv_size); assert(p->tbl_peltv); @@ -5482,11 +5495,11 @@ static bool phb4_calculate_windows(struct phb4 *p) "ibm,mmio-windows", -1); assert(prop->len >= (2 * sizeof(uint64_t))); - p->mm0_base = ((const uint64_t *)prop->prop)[0]; - p->mm0_size = ((const uint64_t *)prop->prop)[1]; + p->mm0_base = be64_to_cpu(((__be64 *)prop->prop)[0]); + p->mm0_size = be64_to_cpu(((__be64 *)prop->prop)[1]); if (prop->len > 16) { - p->mm1_base = ((const uint64_t *)prop->prop)[2]; - p->mm1_size = ((const uint64_t *)prop->prop)[3]; + p->mm1_base = be64_to_cpu(((__be64 *)prop->prop)[2]); + p->mm1_size = be64_to_cpu(((__be64 *)prop->prop)[3]); } /* Sort them so that 0 is big and 1 is small */ @@ -5558,16 +5571,12 @@ static const struct irq_source_ops phb4_lsi_ops = { .attributes = phb4_lsi_attributes, }; -#ifdef HAVE_BIG_ENDIAN static u64 lane_eq_default[8] = { - 0x5454545454545454UL, 0x5454545454545454UL, - 0x5454545454545454UL, 0x5454545454545454UL, - 0x7777777777777777UL, 0x7777777777777777UL, - 0x7777777777777777UL, 0x7777777777777777UL + CPU_TO_BE64(0x5454545454545454UL), CPU_TO_BE64(0x5454545454545454UL), + CPU_TO_BE64(0x5454545454545454UL), CPU_TO_BE64(0x5454545454545454UL), + CPU_TO_BE64(0x7777777777777777UL), CPU_TO_BE64(0x7777777777777777UL), + CPU_TO_BE64(0x7777777777777777UL), CPU_TO_BE64(0x7777777777777777UL), }; -#else -#error lane_eq_default needs to be big endian (device tree property) -#endif static void phb4_create(struct dt_node *np) { @@ -5602,11 +5611,11 @@ static void phb4_create(struct dt_node *np) /* Get the various XSCOM register bases from the device-tree */ prop = dt_require_property(np, "ibm,xscom-bases", 5 * sizeof(uint32_t)); - p->pe_xscom = ((const uint32_t *)prop->prop)[0]; - p->pe_stk_xscom = ((const uint32_t *)prop->prop)[1]; - p->pci_xscom = ((const uint32_t *)prop->prop)[2]; - p->pci_stk_xscom = ((const uint32_t *)prop->prop)[3]; - p->etu_xscom = ((const uint32_t *)prop->prop)[4]; + p->pe_xscom = be32_to_cpu(((__be32 *)prop->prop)[0]); + p->pe_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[1]); + p->pci_xscom = be32_to_cpu(((__be32 *)prop->prop)[2]); + p->pci_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[3]); + p->etu_xscom = be32_to_cpu(((__be32 *)prop->prop)[4]); /* * We skip the initial PERST assertion requested by the generic code @@ -5828,13 +5837,13 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, /* Build MMIO windows list */ mmio_win_sz = 0; if (mmio0_bar) { - mmio_win[mmio_win_sz++] = mmio0_bar; - mmio_win[mmio_win_sz++] = mmio0_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_sz); bar_en |= XPEC_NEST_STK_BAR_EN_MMIO0; } if (mmio1_bar) { - mmio_win[mmio_win_sz++] = mmio1_bar; - mmio_win[mmio_win_sz++] = mmio1_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_sz); bar_en |= XPEC_NEST_STK_BAR_EN_MMIO1; } @@ -5864,12 +5873,12 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, prlog_once(PR_DEBUG, "Version reg: 0x%016llx\n", in_be64(foo)); /* Create PHB node */ - reg[0] = phb_bar; - reg[1] = 0x1000; - reg[2] = irq_bar; - reg[3] = 0x10000000; + reg[0] = cpu_to_be64(phb_bar); + reg[1] = cpu_to_be64(0x1000); + reg[2] = cpu_to_be64(irq_bar); + reg[3] = cpu_to_be64(0x10000000); - np = dt_new_addr(dt_root, "pciex", reg[0]); + np = dt_new_addr(dt_root, "pciex", phb_bar); if (!np) return; diff --git a/include/phb4.h b/include/phb4.h index 1c68ec2e2..ca701a311 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -183,7 +183,7 @@ struct phb4 { uint64_t creset_start_time; /* SkiBoot owned in-memory tables */ - uint16_t *tbl_rtt; + __be16 *tbl_rtt; uint8_t *tbl_peltv; uint64_t tbl_peltv_size; uint64_t tbl_pest; From patchwork Wed Oct 9 23:49:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWN905p8z9s7T for ; Thu, 10 Oct 2019 10:56:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BPHlTb27"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWN85wPLzDqYd for ; Thu, 10 Oct 2019 10:56:56 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BPHlTb27"; dkim-atps=neutral Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWJ145ZWzDqYW for ; Thu, 10 Oct 2019 10:53:21 +1100 (AEDT) Received: by mail-pg1-x541.google.com with SMTP id z12so2439519pgp.9 for ; Wed, 09 Oct 2019 16:53:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dqV8EKFV/FohkQSodBVBFKdDWu1NjZx2daYj6GiXBbw=; b=BPHlTb27NaVjuhDMRXW30T7cTwz175yDU0uHRAIG6MVw0l3nu+fMevPJA9tZ17fBHt 8sdYDgbXbXLdDOZQpb4/aUim1YY0e3A1rQkEcP662SUnQJ1o80IDu+KmMhDJA/jvOE4G 32C3WU3IM3X0XRccVA8bRaFFVYpjSFNaHcRHlImoN8nWpnnIO/Nhhd0mwKFLIMm5UMtM sb+v6ied5ee84NFy0WbOUrnH6Ci4eQGxBdYRTgn+vLwJfxEXWkG8IhT5BDy1ulNdGB3l duPg+9D9HTdL0BNu2VVpIqaFqW/s/UHNvQebQ1pZOYO2rCs2Zny2PzUpUGPRne/e27JC UXJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dqV8EKFV/FohkQSodBVBFKdDWu1NjZx2daYj6GiXBbw=; b=SHTChXcgPtPRuALCLkezXQ9wXJpe52JR/m/w4KepI8nyRLeCUOHBmIFD14zNIycXxq rgInUoYHdgISylnYyEF5odPxnckDFquA3iinUpx6vr90yjCBbMRCcLKCzxbq/6mQNtqg TRPOXONaQSUePbno27O6gz3i1twEuxeHOOagLQsfWKWKEZ4UhTDwQlUPEKZd5Al9FqDb jvetJxoTuvrkWlJITm6LIXIb0qahjQFUNJvX4eF2MMCvjwzvD4SagL4259SmkrjoQdVi +RVtEGSyrRlISWIwJp4XDoUNGkI0kMsuG5bwm063wqgTVdTKw1aWgy7izhm25FjIA9/Q Gdew== X-Gm-Message-State: APjAAAU1eIAM5KxFi/WRrvR7HRRpiC+x92xxt8sOAbs4qFeNldCwMumj KlOeuiH5TTNzTrHItdLTDRE3UdIi X-Google-Smtp-Source: APXvYqyNjq/k+hfJUU6LxxF/HMsW0fJF5v35ulgS2o2UcSRvNpfripp0y6SbYZeDK42WvWnfa6Q2vg== X-Received: by 2002:a63:5025:: with SMTP id e37mr4448691pgb.7.1570665199102; Wed, 09 Oct 2019 16:53:19 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:18 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:48 +1000 Message-Id: <20191009234951.2850-13-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 12/15] occ sensors: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert occ sensors dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/occ-sensor.c | 100 ++++++++++++++++++++++++++---------------------- hw/occ.c | 24 ++++++------ include/occ.h | 50 ++++++++++++------------ 3 files changed, 92 insertions(+), 82 deletions(-) diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c index d06ca725b..6a01f6f55 100644 --- a/hw/occ-sensor.c +++ b/hw/occ-sensor.c @@ -116,7 +116,7 @@ struct occ_sensor_data_header *get_sensor_header_block(int occ_num) static inline struct occ_sensor_name *get_names_block(struct occ_sensor_data_header *hb) { - return ((struct occ_sensor_name *)((u64)hb + hb->names_offset)); + return ((struct occ_sensor_name *)((u64)hb + be32_to_cpu(hb->names_offset))); } static inline u32 sensor_handler(int occ_num, int sensor_id, int attr) @@ -131,11 +131,11 @@ static inline u32 sensor_handler(int occ_num, int sensor_id, int attr) */ static void scale_sensor(struct occ_sensor_name *md, u64 *sensor) { - u32 factor = md->scale_factor; + u32 factor = be32_to_cpu(md->scale_factor); int i; s8 exp; - if (md->type == OCC_SENSOR_TYPE_CURRENT) + if (be16_to_cpu(md->type) == OCC_SENSOR_TYPE_CURRENT) *sensor *= 1000; //convert to mA *sensor *= factor >> 8; @@ -152,7 +152,7 @@ static void scale_sensor(struct occ_sensor_name *md, u64 *sensor) static void scale_energy(struct occ_sensor_name *md, u64 *sensor) { - u32 factor = md->freq; + u32 factor = be32_to_cpu(md->freq); int i; s8 exp; @@ -174,17 +174,17 @@ static u64 read_sensor(struct occ_sensor_record *sensor, int attr) { switch (attr) { case SENSOR_SAMPLE: - return sensor->sample; + return be16_to_cpu(sensor->sample); case SENSOR_SAMPLE_MIN: - return sensor->sample_min; + return be16_to_cpu(sensor->sample_min); case SENSOR_SAMPLE_MAX: - return sensor->sample_max; + return be16_to_cpu(sensor->sample_max); case SENSOR_CSM_MIN: - return sensor->csm_min; + return be16_to_cpu(sensor->csm_min); case SENSOR_CSM_MAX: - return sensor->csm_max; + return be16_to_cpu(sensor->csm_max); case SENSOR_ACCUMULATOR: - return sensor->accumulator; + return be64_to_cpu(sensor->accumulator); default: break; } @@ -197,14 +197,16 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) struct occ_sensor_name *md; u8 *ping, *pong; void *buffer = NULL; + u32 reading_offset; if (!hb) return NULL; md = get_names_block(hb); - ping = (u8 *)((u64)hb + hb->reading_ping_offset); - pong = (u8 *)((u64)hb + hb->reading_pong_offset); + ping = (u8 *)((u64)hb + be32_to_cpu(hb->reading_ping_offset)); + pong = (u8 *)((u64)hb + be32_to_cpu(hb->reading_pong_offset)); + reading_offset = be32_to_cpu(md[id].reading_offset); /* Check which buffer is valid and read the data from that. * Ping Pong Action @@ -216,11 +218,11 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) if (*ping && *pong) { u64 tping, tpong; - u64 ping_buf = (u64)ping + md[id].reading_offset; - u64 pong_buf = (u64)pong + md[id].reading_offset; + u64 ping_buf = (u64)ping + reading_offset; + u64 pong_buf = (u64)pong + reading_offset; - tping = ((struct occ_sensor_record *)ping_buf)->timestamp; - tpong = ((struct occ_sensor_record *)pong_buf)->timestamp; + tping = be64_to_cpu(((struct occ_sensor_record *)ping_buf)->timestamp); + tpong = be64_to_cpu(((struct occ_sensor_record *)pong_buf)->timestamp); if (tping > tpong) buffer = ping; @@ -236,7 +238,7 @@ static void *select_sensor_buffer(struct occ_sensor_data_header *hb, int id) } assert(buffer); - buffer = (void *)((u64)buffer + md[id].reading_offset); + buffer = (void *)((u64)buffer + reading_offset); return buffer; } @@ -264,7 +266,7 @@ int occ_sensor_read(u32 handle, u64 *data) if (hb->valid != 1) return OPAL_HARDWARE; - if (id > hb->nr_sensors) + if (id > be16_to_cpu(hb->nr_sensors)) return OPAL_PARAMETER; buff = select_sensor_buffer(hb, id); @@ -276,7 +278,7 @@ int occ_sensor_read(u32 handle, u64 *data) return OPAL_SUCCESS; md = get_names_block(hb); - if (md[id].type == OCC_SENSOR_TYPE_POWER && attr == SENSOR_ACCUMULATOR) + if (be16_to_cpu(md[id].type) == OCC_SENSOR_TYPE_POWER && attr == SENSOR_ACCUMULATOR) scale_energy(&md[id], data); else scale_sensor(&md[id], data); @@ -320,7 +322,8 @@ static bool occ_sensor_sanity(struct occ_sensor_data_header *hb, int chipid) return false; } - if (!hb->names_offset || !hb->reading_ping_offset || + if (!hb->names_offset || + !hb->reading_ping_offset || !hb->reading_pong_offset) { prerror("OCC: Chip %d Invalid sensor buffer pointers\n", chipid); @@ -357,9 +360,10 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, { char sname[30] = ""; char prefix[30] = ""; + uint16_t location = be16_to_cpu(md->location); int i; - if (md->location != OCC_SENSOR_LOC_SYSTEM) + if (location != OCC_SENSOR_LOC_SYSTEM) snprintf(prefix, sizeof(prefix), "%s %d ", "Chip", chipid); for (i = 0; i < ARRAY_SIZE(str_maps); i++) @@ -368,7 +372,7 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, char *end; int num = -1; - if (md->location != OCC_SENSOR_LOC_CORE) + if (location != OCC_SENSOR_LOC_CORE) num = parse_entity(md->name, &end); if (num != -1) { @@ -384,7 +388,7 @@ static void add_sensor_label(struct dt_node *node, struct occ_sensor_name *md, } /* Fallback to OCC literal if mapping is not found */ - if (md->location == OCC_SENSOR_LOC_SYSTEM) { + if (location == OCC_SENSOR_LOC_SYSTEM) { dt_add_property_string(node, "label", md->name); } else { snprintf(sname, sizeof(sname), "%s%s", prefix, md->name); @@ -444,15 +448,15 @@ static bool check_sensor_sample(struct occ_sensor_data_header *hb, u32 offset) { struct occ_sensor_record *ping, *pong; - ping = (struct occ_sensor_record *)((u64)hb + hb->reading_ping_offset - + offset); - pong = (struct occ_sensor_record *)((u64)hb + hb->reading_pong_offset - + offset); + ping = (struct occ_sensor_record *)((u64)hb + + be32_to_cpu(hb->reading_ping_offset) + offset); + pong = (struct occ_sensor_record *)((u64)hb + + be32_to_cpu(hb->reading_pong_offset) + offset); return ping->sample || pong->sample; } static void add_sensor_node(const char *loc, const char *type, int i, int attr, - struct occ_sensor_name *md, u32 *phandle, u32 *ptype, + struct occ_sensor_name *md, __be32 *phandle, u32 *ptype, u32 pir, u32 occ_num, u32 chipid) { char name[30]; @@ -468,10 +472,10 @@ static void add_sensor_node(const char *loc, const char *type, int i, int attr, dt_add_property_string(node, "occ_label", md->name); add_sensor_label(node, md, chipid); - if (md->location == OCC_SENSOR_LOC_CORE) + if (be16_to_cpu(md->location) == OCC_SENSOR_LOC_CORE) dt_add_property_cells(node, "ibm,pir", pir); - *ptype = md->type; + *ptype = be16_to_cpu(md->type); if (attr == SENSOR_SAMPLE) { handler = sensor_handler(occ_num, i, SENSOR_CSM_MAX); @@ -482,7 +486,7 @@ static void add_sensor_node(const char *loc, const char *type, int i, int attr, } dt_add_property_string(node, "compatible", "ibm,opal-sensor"); - *phandle = node->phandle; + *phandle = cpu_to_be32(node->phandle); } bool occ_sensors_init(void) @@ -520,7 +524,9 @@ bool occ_sensors_init(void) for_each_chip(chip) { struct occ_sensor_data_header *hb; struct occ_sensor_name *md; - u32 *phandles, *ptype, phcount = 0; + __be32 *phandles; + u32 *ptype, phcount = 0; + unsigned int nr_sensors; hb = get_sensor_header_block(occ_num); md = get_names_block(hb); @@ -529,30 +535,34 @@ bool occ_sensors_init(void) if (!occ_sensor_sanity(hb, chip->id)) continue; - phandles = malloc(hb->nr_sensors * sizeof(u32)); + nr_sensors = be16_to_cpu(hb->nr_sensors); + + phandles = malloc(nr_sensors * sizeof(__be32)); assert(phandles); - ptype = malloc(hb->nr_sensors * sizeof(u32)); + ptype = malloc(nr_sensors * sizeof(u32)); assert(ptype); - for (i = 0; i < hb->nr_sensors; i++) { - const char *type, *loc; + for (i = 0; i < nr_sensors; i++) { + const char *type_name, *loc; struct cpu_thread *c = NULL; uint32_t pir = 0; + uint16_t type = be16_to_cpu(md[i].type); + uint16_t location = be16_to_cpu(md[i].location); if (md[i].structure_type != OCC_SENSOR_READING_FULL) continue; - if (!(md[i].type & HWMON_SENSORS_MASK)) + if (!(type & HWMON_SENSORS_MASK)) continue; - if (md[i].location == OCC_SENSOR_LOC_GPU && !has_gpu) + if (location == OCC_SENSOR_LOC_GPU && !has_gpu) continue; - if (md[i].type == OCC_SENSOR_TYPE_POWER && - !check_sensor_sample(hb, md[i].reading_offset)) + if (type == OCC_SENSOR_TYPE_POWER && + !check_sensor_sample(hb, be32_to_cpu(md[i].reading_offset))) continue; - if (md[i].location == OCC_SENSOR_LOC_CORE) { + if (location == OCC_SENSOR_LOC_CORE) { int num = parse_entity(md[i].name, NULL); for_each_available_core_in_chip(c, chip->id) @@ -563,16 +573,16 @@ bool occ_sensors_init(void) pir = c->pir; } - type = get_sensor_type_string(md[i].type); - loc = get_sensor_loc_string(md[i].location); + type_name = get_sensor_type_string(type); + loc = get_sensor_loc_string(location); - add_sensor_node(loc, type, i, SENSOR_SAMPLE, &md[i], + add_sensor_node(loc, type_name, i, SENSOR_SAMPLE, &md[i], &phandles[phcount], &ptype[phcount], pir, occ_num, chip->id); phcount++; /* Add energy sensors */ - if (md[i].type == OCC_SENSOR_TYPE_POWER && + if (type == OCC_SENSOR_TYPE_POWER && md[i].structure_type == OCC_SENSOR_READING_FULL) { add_sensor_node(loc, "energy", i, SENSOR_ACCUMULATOR, &md[i], diff --git a/hw/occ.c b/hw/occ.c index db2744ff7..4a0a11f58 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -97,7 +97,7 @@ struct occ_pstate_table { u8 flags; u8 vdd; u8 vcs; - u32 freq_khz; + __be32 freq_khz; } pstates[MAX_PSTATES]; s8 core_max[MAX_P8_CORES]; u8 pad[100]; @@ -115,7 +115,7 @@ struct occ_pstate_table { u8 id; u8 flags; u16 reserved; - u32 freq_khz; + __be32 freq_khz; } pstates[MAX_PSTATES]; u8 core_max[MAX_P9_CORES]; u8 pad[56]; @@ -375,7 +375,7 @@ static bool wait_for_all_occ_init(void) chip->occ_functional = true; prlog(PR_DEBUG, "OCC: Chip %02x Data (%016llx) = %016llx\n", - chip->id, (uint64_t)occ_data, *(uint64_t *)occ_data); + chip->id, (uint64_t)occ_data, be64_to_cpu(*(__be64 *)occ_data)); } end_time = mftb(); prlog(PR_NOTICE, "OCC: All Chip Rdy after %lu ms\n", @@ -407,8 +407,8 @@ static void parse_pstates_v2(struct occ_pstate_table *data, u32 *dt_id, if (cmp_pstates(data->v2.pstates[i].id, pmax) > 0) continue; - dt_id[j] = data->v2.pstates[i].id; - dt_freq[j] = data->v2.pstates[i].freq_khz / 1000; + dt_id[j] = cpu_to_be32(data->v2.pstates[i].id); + dt_freq[j] = cpu_to_be32(be32_to_cpu(data->v2.pstates[i].freq_khz) / 1000); j++; if (data->v2.pstates[i].id == pmin) @@ -429,8 +429,8 @@ static void parse_pstates_v9(struct occ_pstate_table *data, u32 *dt_id, if (cmp_pstates(data->v9.pstates[i].id, pmax) > 0) continue; - dt_id[j] = data->v9.pstates[i].id; - dt_freq[j] = data->v9.pstates[i].freq_khz / 1000; + dt_id[j] = cpu_to_be32(data->v9.pstates[i].id); + dt_freq[j] = cpu_to_be32(be32_to_cpu(data->v9.pstates[i].freq_khz) / 1000); j++; if (data->v9.pstates[i].id == pmin) @@ -500,8 +500,8 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, occ_data_area = (uint64_t)occ_data; prlog(PR_DEBUG, "OCC: Data (%16llx) = %16llx %16llx\n", occ_data_area, - *(uint64_t *)occ_data_area, - *(uint64_t *)(occ_data_area + 8)); + be64_to_cpu(*(__be64 *)occ_data_area), + be64_to_cpu(*(__be64 *)(occ_data_area + 8))); if (!occ_data->valid) { /** @@ -676,13 +676,13 @@ static bool add_cpu_pstate_properties(struct dt_node *power_mgt, pturbo = occ_data->v2.pstate_turbo; pultra_turbo = occ_data->v2.pstate_ultra_turbo; for (i = 0; i < nr_cores; i++) - dt_cmax[i] = occ_data->v2.core_max[i]; + dt_cmax[i] = cpu_to_be32(occ_data->v2.core_max[i]); break; case 0x9: pturbo = occ_data->v9.pstate_turbo; pultra_turbo = occ_data->v9.pstate_ultra_turbo; for (i = 0; i < nr_cores; i++) - dt_cmax[i] = occ_data->v9.core_max[i]; + dt_cmax[i] = cpu_to_be32(occ_data->v9.core_max[i]); break; default: return false; @@ -1600,7 +1600,7 @@ int occ_sensor_group_enable(u32 group_hndl, int token, bool enable) return opal_occ_command(&chips[i], token, &sensor_mask_data); } -void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, u32 *ptype, +void occ_add_sensor_groups(struct dt_node *sg, __be32 *phandles, u32 *ptype, int nr_phandles, int chipid) { struct group_info { diff --git a/include/occ.h b/include/occ.h index 0030af5ae..f3b8f6a9a 100644 --- a/include/occ.h +++ b/include/occ.h @@ -34,7 +34,7 @@ bool occ_get_gpu_presence(struct proc_chip *chip, int gpu_num); extern bool occ_sensors_init(void); extern int occ_sensor_read(u32 handle, u64 *data); extern int occ_sensor_group_clear(u32 group_hndl, int token); -extern void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles, +extern void occ_add_sensor_groups(struct dt_node *sg, __be32 *phandles, u32 *ptype, int nr_phandles, int chipid); extern int occ_sensor_group_enable(u32 group_hndl, int token, bool enable); @@ -186,15 +186,15 @@ enum sensor_struct_type { struct occ_sensor_data_header { u8 valid; u8 version; - u16 nr_sensors; + __be16 nr_sensors; u8 reading_version; u8 pad[3]; - u32 names_offset; + __be32 names_offset; u8 names_version; u8 name_length; u16 reserved; - u32 reading_ping_offset; - u32 reading_pong_offset; + __be32 reading_ping_offset; + __be32 reading_pong_offset; } __attribute__((__packed__)); /** @@ -220,13 +220,13 @@ struct occ_sensor_data_header { struct occ_sensor_name { char name[MAX_CHARS_SENSOR_NAME]; char units[MAX_CHARS_SENSOR_UNIT]; - u16 gsid; - u32 freq; - u32 scale_factor; - u16 type; - u16 location; + __be16 gsid; + __be32 freq; + __be32 scale_factor; + __be16 type; + __be16 location; u8 structure_type; - u32 reading_offset; + __be32 reading_offset; u8 sensor_data; u8 pad[8]; } __attribute__((__packed__)); @@ -258,18 +258,18 @@ struct occ_sensor_name { */ struct occ_sensor_record { u16 gsid; - u64 timestamp; - u16 sample; - u16 sample_min; - u16 sample_max; - u16 csm_min; - u16 csm_max; - u16 profiler_min; - u16 profiler_max; - u16 job_scheduler_min; - u16 job_scheduler_max; - u64 accumulator; - u32 update_tag; + __be64 timestamp; + __be16 sample; + __be16 sample_min; + __be16 sample_max; + __be16 csm_min; + __be16 csm_max; + __be16 profiler_min; + __be16 profiler_max; + __be16 job_scheduler_min; + __be16 job_scheduler_max; + __be64 accumulator; + __be32 update_tag; u8 pad[8]; } __attribute__((__packed__)); @@ -284,8 +284,8 @@ struct occ_sensor_record { */ struct occ_sensor_counter { u16 gsid; - u64 timestamp; - u64 accumulator; + __be64 timestamp; + __be64 accumulator; u8 sample; u8 pad[5]; } __attribute__((__packed__)); From patchwork Wed Oct 9 23:49:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWNY2Wzwz9sN1 for ; Thu, 10 Oct 2019 10:57:17 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l4Apf3ZR"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWNY0tV3zDq9B for ; Thu, 10 Oct 2019 10:57:17 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l4Apf3ZR"; dkim-atps=neutral Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWJ34hjFzDqYj for ; Thu, 10 Oct 2019 10:53:23 +1100 (AEDT) Received: by mail-pl1-x641.google.com with SMTP id u12so1820284pls.12 for ; Wed, 09 Oct 2019 16:53:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AOG503UdfDeTx0lu437omNlIRCX956zjmUF8b0KsQa0=; b=l4Apf3ZRsz3FAslsSgG3N0IozwwgC76XY/toGBWGY0aKdUNpgAbDhKtnlTAezbRQjW 8m3bE/S30McvmVOYEmmOtdFUNVMSNbYsgf1BFDx52y1ULYtL9Q7RThMnlY2aimu55T4z +1lSaMdkaapvG4ZUDU8ATsyVQqL+ys6G+zISTNQtciY2S8w01Qw4+i/iATiynLs42Z1m W92Rd45v2R7Afn9skpP+KkFGpOGyDIxW7hX2DB1UGA39gUNdb2YxS6StuZlosTHnY97P MYEGYQTBafHYSds8rwvBE8WXVpQjyV3Hr6vA0+1FfLKZsZynzahcjzJVCZEhRD7B7zK0 TCUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AOG503UdfDeTx0lu437omNlIRCX956zjmUF8b0KsQa0=; b=b2sXYCzXGx+gV0is7YnKKkAnxFxzyhYcvVu3WLCDFpJWlGXNG2uElmRxSJ3EblEo85 YRvJFtfH6m2ze0s08tflB5zYBg0xw5KRymoiWv3aYWcLQwWdDj50EN5q8jXzY5QffXMt OzXjU0FdohWUyaFo99k7XaVcdgs6ockxV4e1od2KafZThCbnqmarUxflQa4ZubNpzVsI +o0SMEQk8KFebS0EMViJG25O1dyxgFM+s+BaluSqu5AouGjOVqbeTDt5KO7iX0w3fkYu I64SlcetLoR/nwqpjnwxnAV6vTQBMCu1Xq3wW2iA1Uov//zfPqQrdenAy9qleE9ZnMf9 fAew== X-Gm-Message-State: APjAAAWQFUYDkpG8njvB/sdTa4jfA5ZWQoZIREKjDgkmw701pxSDFXjR AkKHSQ/rQELLJFss9yokDNPJSEiy X-Google-Smtp-Source: APXvYqwWTCpG80NxrY+7gJ0MjcCkC7fKK+nA49kxXgLtvOy3bmWiQY4qlRuU82EBVOOn+jZsOGtF/g== X-Received: by 2002:a17:902:9344:: with SMTP id g4mr5916745plp.158.1570665201186; Wed, 09 Oct 2019 16:53:21 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:20 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:49 +1000 Message-Id: <20191009234951.2850-14-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 13/15] memconsole: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert memconsole dt construction and in-memory tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- core/console.c | 22 +++++++++++----------- include/console.h | 16 ++++++++-------- platforms/ibm-fsp/common.c | 4 ++-- platforms/ibm-fsp/hostservices.c | 12 ++++++------ 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/core/console.c b/core/console.c index ac88f0c71..030c1d918 100644 --- a/core/console.c +++ b/core/console.c @@ -30,11 +30,11 @@ static struct lock con_lock = LOCK_UNLOCKED; /* This is mapped via TCEs so we keep it alone in a page */ struct memcons memcons __section(".data.memcons") = { - .magic = MEMCONS_MAGIC, - .obuf_phys = INMEM_CON_START, - .ibuf_phys = INMEM_CON_START + INMEM_CON_OUT_LEN, - .obuf_size = INMEM_CON_OUT_LEN, - .ibuf_size = INMEM_CON_IN_LEN, + .magic = CPU_TO_BE64(MEMCONS_MAGIC), + .obuf_phys = CPU_TO_BE64(INMEM_CON_START), + .ibuf_phys = CPU_TO_BE64(INMEM_CON_START + INMEM_CON_OUT_LEN), + .obuf_size = CPU_TO_BE32(INMEM_CON_OUT_LEN), + .ibuf_size = CPU_TO_BE32(INMEM_CON_IN_LEN), }; static bool dummy_console_enabled(void) @@ -197,7 +197,7 @@ static void inmem_write(char c) if (con_wrapped) opos |= MEMCONS_OUT_POS_WRAP; lwsync(); - memcons.out_pos = opos; + memcons.out_pos = cpu_to_be32(opos); /* If head reaches tail, push tail around & drop chars */ if (con_in == con_out) @@ -207,12 +207,12 @@ static void inmem_write(char c) static size_t inmem_read(char *buf, size_t req) { size_t read = 0; - char *ibuf = (char *)memcons.ibuf_phys; + char *ibuf = (char *)be64_to_cpu(memcons.ibuf_phys); - while (req && memcons.in_prod != memcons.in_cons) { - *(buf++) = ibuf[memcons.in_cons]; + while (req && be32_to_cpu(memcons.in_prod) != be32_to_cpu(memcons.in_cons)) { + *(buf++) = ibuf[be32_to_cpu(memcons.in_cons)]; lwsync(); - memcons.in_cons = (memcons.in_cons + 1) % INMEM_CON_IN_LEN; + memcons.in_cons = cpu_to_be32((be32_to_cpu(memcons.in_cons) + 1) % INMEM_CON_IN_LEN); req--; read++; } @@ -428,7 +428,7 @@ void dummy_console_add_nodes(void) { struct dt_property *p; - add_opal_console_node(0, "raw", memcons.obuf_size); + add_opal_console_node(0, "raw", be32_to_cpu(memcons.obuf_size)); /* Mambo might have left a crap one, clear it */ p = __dt_find_property(dt_chosen, "linux,stdout-path"); diff --git a/include/console.h b/include/console.h index 230b825b0..61448e28e 100644 --- a/include/console.h +++ b/include/console.h @@ -14,17 +14,17 @@ * (This is v3 of the format, the previous one sucked) */ struct memcons { - uint64_t magic; + __be64 magic; #define MEMCONS_MAGIC 0x6630696567726173LL - uint64_t obuf_phys; - uint64_t ibuf_phys; - uint32_t obuf_size; - uint32_t ibuf_size; - uint32_t out_pos; + __be64 obuf_phys; + __be64 ibuf_phys; + __be32 obuf_size; + __be32 ibuf_size; + __be32 out_pos; #define MEMCONS_OUT_POS_WRAP 0x80000000u #define MEMCONS_OUT_POS_MASK 0x00ffffffu - uint32_t in_prod; - uint32_t in_cons; + __be32 in_prod; + __be32 in_cons; }; extern struct memcons memcons; diff --git a/platforms/ibm-fsp/common.c b/platforms/ibm-fsp/common.c index a0339ec25..edb60eb4a 100644 --- a/platforms/ibm-fsp/common.c +++ b/platforms/ibm-fsp/common.c @@ -25,9 +25,9 @@ static void map_debug_areas(void) fsp_tce_map(PSI_DMA_LOG_BUF, (void*)INMEM_CON_START, INMEM_CON_LEN); debug_descriptor.memcons_tce = PSI_DMA_MEMCONS; - t = memcons.obuf_phys - INMEM_CON_START + PSI_DMA_LOG_BUF; + t = be64_to_cpu(memcons.obuf_phys) - INMEM_CON_START + PSI_DMA_LOG_BUF; debug_descriptor.memcons_obuf_tce = t; - t = memcons.ibuf_phys - INMEM_CON_START + PSI_DMA_LOG_BUF; + t = be64_to_cpu(memcons.ibuf_phys) - INMEM_CON_START + PSI_DMA_LOG_BUF; debug_descriptor.memcons_ibuf_tce = t; /* We only have space in the TCE table for the trace diff --git a/platforms/ibm-fsp/hostservices.c b/platforms/ibm-fsp/hostservices.c index 3bdad4a5e..81008ac2b 100644 --- a/platforms/ibm-fsp/hostservices.c +++ b/platforms/ibm-fsp/hostservices.c @@ -178,11 +178,11 @@ static bool hbrt_con_wrapped; #define HBRT_CON_OUT_LEN (HBRT_CON_LEN - HBRT_CON_IN_LEN) static struct memcons hbrt_memcons __section(".data.memcons") = { - .magic = MEMCONS_MAGIC, - .obuf_phys = HBRT_CON_START, - .ibuf_phys = HBRT_CON_START + HBRT_CON_OUT_LEN, - .obuf_size = HBRT_CON_OUT_LEN, - .ibuf_size = HBRT_CON_IN_LEN, + .magic = CPU_TO_BE64(MEMCONS_MAGIC), + .obuf_phys = CPU_TO_BE64(HBRT_CON_START), + .ibuf_phys = CPU_TO_BE64(HBRT_CON_START + HBRT_CON_OUT_LEN), + .obuf_size = CPU_TO_BE32(HBRT_CON_OUT_LEN), + .ibuf_size = CPU_TO_BE32(HBRT_CON_IN_LEN), }; static void hservice_putc(char c) @@ -206,7 +206,7 @@ static void hservice_putc(char c) if (hbrt_con_wrapped) opos |= MEMCONS_OUT_POS_WRAP; lwsync(); - hbrt_memcons.out_pos = opos; + hbrt_memcons.out_pos = cpu_to_be32(opos); } static void hservice_puts(const char *str) From patchwork Wed Oct 9 23:49:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWNs46gsz9sN1 for ; Thu, 10 Oct 2019 10:57:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lo2bMMZV"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWNs2fP9zDqbX for ; Thu, 10 Oct 2019 10:57:33 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::534; helo=mail-pg1-x534.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lo2bMMZV"; dkim-atps=neutral Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWJ60h0DzDqYL for ; Thu, 10 Oct 2019 10:53:26 +1100 (AEDT) Received: by mail-pg1-x534.google.com with SMTP id t3so2439985pga.8 for ; Wed, 09 Oct 2019 16:53:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DHeoCl3QkXVisjGXazAW9gtCDc9+bdVAhXVvWjfSqCE=; b=lo2bMMZV1PNZBIEnoPDDLQ2DpZ5yai6Kkrt0T1bFcMGCbjOuWM7ZJSSU/sn/HizTir ley9qakrhlprJm44t3TBybPyWRjvw7zgynEkeVWfsuIrqsXsaTmMyx0qYxpX+OwgPHDC Ed2szNdCSLhAeq1zuZ1ZR0gRXg0CCobzmOYId69kynJJl8x4yxX6frLzurp+ENGkZSTi dnYX1iwhG/Z72BtJc90sLxaz0WHVLExrYKQX/iXu4JKi0l6cf2qNVfysXt7ZY5FPHlfI 4gvw0+4PCspTIF0ZMEcMtgi4MMzsPD2wNewjzuyhqxr/kUzvg1YpGJpCBiiKXIOFQEq6 1GTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DHeoCl3QkXVisjGXazAW9gtCDc9+bdVAhXVvWjfSqCE=; b=GXjlbq6FaUlhb50zAdVaFhf3AUpqN8blOCtvrHTxMRkGpZLonH8/nxbgCS9wYnUcBF 4Z6W7TZx0tznI8IXNoGbpXZI20Uw3P8XdBPR+KGPi51M/BpZsYwRCMcJVxB+EpcZcmCH oNdc26pag+oBwA6OUHFUJIkEa4p2Q5HaUGOseMKMJ02dL35fj+mWDOnz043pEICaN7iC 1V7sq5lO55nq6GBni/Ss86E7NyVo+aaH8JD+dZU4wZVUuPThIWUqsKdqTr3APOcuGs1z tcwlRztyRgrk26zRukKWb5YC5VuXtD8/iTWzDBSpVOC/q++sEhbPK/uVb1oX3HO+hgoU kihQ== X-Gm-Message-State: APjAAAXbLig9BCx5GTH4GDZKutzR+26AzxahhIQVwO93suVmlpMWUF95 U+DiLK29jVwSXxvgKGDTNE+lPPmV X-Google-Smtp-Source: APXvYqxhV9NZVQQVN5hsQK3pt4u/kjKd6MLM/7SUJWMrMi1vIHsm8jnfM272G9yY7/z6yHQO5YIzug== X-Received: by 2002:aa7:9538:: with SMTP id c24mr6736416pfp.8.1570665203823; Wed, 09 Oct 2019 16:53:23 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:22 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:50 +1000 Message-Id: <20191009234951.2850-15-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 14/15] add little endian support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds support for building LE skiboot with LITTLE_ENDIAN=1. This is not complete, notably PHB3, NPU* and *CAPI*, but it is sufficient to build and boot on mambo and OpenPOWER POWER9 systems. LE/ELFv2 is a nicer calling convention, and results in smaller image and less stack usage. It also follows the rest of the Linux/OpenPOWER stack moving to LE. The OPALv3 call interface still requires an ugly transition through BE for compatibility, but that is all handled on the OPAL side. Signed-off-by: Nicholas Piggin --- Makefile.main | 38 ++++++++++++-- asm/cvc_entry.S | 42 +++++++-------- asm/head.S | 66 +++++++++++++++++------- core/cpu.c | 24 +++++++-- core/init.c | 1 + doc/stb.rst | 2 +- hdata/spira.c | 2 +- include/asm-utils.h | 22 ++++++-- include/cpu.h | 3 ++ include/elf.h | 4 ++ include/stack.h | 4 ++ libpore/p9_cpu_reg_restore_instruction.H | 23 +++++---- libstb/cvc.c | 16 ++++-- libstb/cvc.h | 2 +- 14 files changed, 174 insertions(+), 75 deletions(-) diff --git a/Makefile.main b/Makefile.main index 2d60bbbf5..1d834e81b 100644 --- a/Makefile.main +++ b/Makefile.main @@ -65,21 +65,35 @@ CPPFLAGS += -I$(SRC)/libfdt -I$(SRC)/libflash -I$(SRC)/libxz -I$(SRC)/libc/inclu CPPFLAGS += -I$(SRC)/libpore CPPFLAGS += -D__SKIBOOT__ -nostdinc CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) -CPPFLAGS += -DBITS_PER_LONG=64 -DHAVE_BIG_ENDIAN +CPPFLAGS += -DBITS_PER_LONG=64 + # We might want to remove our copy of stdint.h # but that means uint64_t becomes an ulong instead of an ullong # causing all our printf's to warn CPPFLAGS += -ffreestanding +ifeq ($(LITTLE_ENDIAN),1) +CPPFLAGS += -DHAVE_LITTLE_ENDIAN +else +CPPFLAGS += -DHAVE_BIG_ENDIAN +endif + ifeq ($(DEBUG),1) CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG endif -CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -mbig-endian -m64 -fno-asynchronous-unwind-tables +CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables CFLAGS += -mcpu=power8 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb CFLAGS += $(call try-cflag,$(CC),-ffixed-r13) CFLAGS += $(call try-cflag,$(CC),-std=gnu11) + +ifeq ($(LITTLE_ENDIAN),1) +CFLAGS += -mlittle-endian +else +CFLAGS += -mbig-endian +endif + ifeq ($(ELF_ABI_v2),1) CFLAGS += $(call try-cflag,$(CC),-mabi=elfv2) else @@ -135,8 +149,8 @@ LDFLAGS := -m64 -static -nostdlib -pie LDFLAGS += -Wl,-pie LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none LDFLAGS += -Wl,--no-multi-toc -LDFLAGS += -mcpu=power8 -mbig-endian -Wl,--oformat,elf64-powerpc -LDFLAGS_FINAL = -EB -m elf64ppc --no-multi-toc -N --build-id=none --whole-archive +LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc +LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc LDFLAGS_FINAL += --orphan-handling=warn @@ -144,11 +158,25 @@ LDRFLAGS=-melf64ppc # Debug stuff #LDFLAGS += -Wl,-v -Wl,-Map,foomap +ifeq ($(LITTLE_ENDIAN),1) +LDFLAGS += -mlittle-endian +LDFLAGS_FINAL += -EL +else +LDFLAGS += -mbig-endian +LDFLAGS_FINAL += -EB +endif + ifeq ($(DEAD_CODE_ELIMINATION),1) LDFLAGS += -Wl,--gc-sections endif -AFLAGS := -D__ASSEMBLY__ -mbig-endian -m64 +AFLAGS := -D__ASSEMBLY__ -m64 +ifeq ($(LITTLE_ENDIAN),1) +AFLAGS += -mlittle-endian +else +AFLAGS += -mbig-endian +endif + ifeq ($(ELF_ABI_v2),1) AFLAGS += $(call try-cflag,$(CC),-mabi=elfv2) else diff --git a/asm/cvc_entry.S b/asm/cvc_entry.S index 3e8b3fdad..94cd1aec1 100644 --- a/asm/cvc_entry.S +++ b/asm/cvc_entry.S @@ -1,28 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/secureboot/base/rom_entry.S $ -# -# OpenPOWER HostBoot Project -# -# COPYRIGHT International Business Machines Corp. 2013,2016 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -#.include "kernel/ppcconsts.S" + +# Derived from automatically generated HostBoot rom_entry.S + +#include +#include # Updated hostboot location is src/securerom/rom_entry.S. # This also has a fix for TOC save frame pointer. @@ -49,7 +30,20 @@ call_rom_entry: mr %r5, %r6 mr %r6, %r7 mr %r7, %r8 +#if HAVE_BIG_ENDIAN bctrl +#else + bl $+4 +1: mflr %r9 + addi %r9,%r9,2f - 1b + mtspr SPR_HSRR0, %r9 + mfmsr %r9 + xori %r9,%r9,MSR_LE + mtspr SPR_HSRR1, %r9 + hrfid +2: .long 0x2104804e /* bctrl */ + FIXUP_ENDIAN +#endif ld %r2, STACK_TOC_OFFSET(%r1) addi %r1, %r1, 128 ld %r0, 16(%r1) diff --git a/asm/head.S b/asm/head.S index 7ce3c7c97..68f153b36 100644 --- a/asm/head.S +++ b/asm/head.S @@ -43,6 +43,7 @@ __head: . = 0x10 .global fdt_entry fdt_entry: + FIXUP_ENDIAN mr %r27,%r3 b boot_entry @@ -89,6 +90,7 @@ hir_trigger: . = 0x100 sreset_vector: /* BML entry, load up r3 with device tree location */ + FIXUP_ENDIAN li %r3, 0 oris %r3, %r3, 0xa b fdt_entry /* hack for lab boot */ @@ -96,6 +98,7 @@ sreset_vector: /* Entry point set by the FSP */ .= 0x180 hdat_entry: + FIXUP_ENDIAN li %r27,0 b boot_entry @@ -364,7 +367,11 @@ boot_entry: add %r2,%r2,%r29 /* Fixup our MSR (remove TA) */ +#if HAVE_BIG_ENDIAN LOAD_IMM64(%r3, (MSR_HV | MSR_SF)) +#else + LOAD_IMM64(%r3, (MSR_HV | MSR_SF | MSR_LE)) +#endif mtmsrd %r3,0 /* Check our PIR, avoid threads */ @@ -698,14 +705,18 @@ init_shared_sprs: mtspr SPR_TSCR, %r3 /* HID0: Clear bit 13 (enable core recovery) - * Clear bit 19 (HILE) + * Set/clear bit 19 (HILE) depending on skiboot endian */ mfspr %r3,SPR_HID0 li %r0,1 sldi %r4,%r0,(63-13) - sldi %r5,%r0,(63-19) - or %r0,%r4,%r5 - andc %r3,%r3,%r0 + andc %r3,%r3,%r4 + sldi %r4,%r0,(63-19) +#if HAVE_BIG_ENDIAN + andc %r3,%r3,%r4 +#else + or %r3,%r3,%r4 +#endif sync mtspr SPR_HID0,%r3 mfspr %r3,SPR_HID0 @@ -732,17 +743,21 @@ init_shared_sprs: LOAD_IMM32(%r3,0x80287880) mtspr SPR_TSCR, %r3 /* HID0: Clear bit 5 (enable core recovery) - * Clear bit 4 (HILE) + * Set/clear bit 4 (HILE) depending on skiboot endian * Set bit 8 (radix) */ mfspr %r3,SPR_HID0 li %r0,1 - sldi %r4,%r0,(63-8) + sldi %r4,%r0,(63-4) +#if HAVE_BIG_ENDIAN + andc %r3,%r3,%r4 +#else or %r3,%r3,%r4 +#endif sldi %r4,%r0,(63-5) - sldi %r5,%r0,(63-4) - or %r0,%r4,%r5 - andc %r3,%r3,%r0 + andc %r3,%r3,%r4 + sldi %r4,%r0,(63-8) + or %r3,%r3,%r4 sync mtspr SPR_HID0,%r3 isync @@ -822,6 +837,8 @@ enter_nap: .balign 0x10 .global opal_entry opal_entry: + OPAL_ENTRY_TO_SKIBOOT_ENDIAN + /* Get our per CPU pointer in r12 to check for quiesce */ mfspr %r12,SPR_PIR GET_STACK(%r12,%r12) @@ -967,20 +984,33 @@ opal_entry: lwz %r11,CPUTHREAD_IN_OPAL_CALL(%r12) subi %r11,%r11,1 stw %r11,CPUTHREAD_IN_OPAL_CALL(%r12) +#if HAVE_BIG_ENDIAN /* * blr with BH=01b means it's not a function return, OPAL was entered * via (h)rfid not bl, so we don't have a corresponding link stack * prediction to return to here. */ bclr 20,0,1 +#else + mflr %r12 + mtspr SPR_HSRR0,%r12 + mfmsr %r11 + li %r12,MSR_LE + andc %r11,%r11,%r12 + mtspr SPR_HSRR1,%r11 + hrfid +#endif .global start_kernel start_kernel: + LOAD_IMM64(%r10,MSR_HV|MSR_SF) +__start_kernel: sync icbi 0,%r3 sync isync - mtctr %r3 + mtspr SPR_HSRR0,%r3 + mtspr SPR_HSRR1,%r10 mr %r3,%r4 LOAD_IMM64(%r8,SKIBOOT_BASE); LOAD_IMM32(%r10, opal_entry - __head) @@ -989,21 +1019,19 @@ start_kernel: addi %r7,%r5,1 li %r4,0 li %r5,0 - bctr + hrfid .global start_kernel32 start_kernel32: - mfmsr %r10 - clrldi %r10,%r10,1 - mtmsrd %r10,0 - sync - isync - b start_kernel + LOAD_IMM64(%r10,MSR_HV) + b __start_kernel .global start_kernel_secondary start_kernel_secondary: sync isync - mtctr %r3 + LOAD_IMM64(%r10,MSR_HV|MSR_SF) + mtspr SPR_HSRR0,%r3 + mtspr SPR_HSRR1,%r10 mfspr %r3,SPR_PIR - bctr + hrfid diff --git a/core/cpu.c b/core/cpu.c index b3433aef5..3d6a59033 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -42,7 +42,7 @@ static unsigned long hid0_attn; static bool sreset_enabled; static bool ipi_enabled; static bool pm_enabled; -static bool current_hile_mode; +static bool current_hile_mode = HAVE_LITTLE_ENDIAN; static bool current_radix_mode = true; static bool tm_suspend_enabled; @@ -1415,6 +1415,24 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) return OPAL_SUCCESS; } +void cpu_set_hile_mode(bool hile) +{ + struct hid0_change_req req; + + if (hile == current_hile_mode) + return; + + if (hile) { + req.clr_bits = 0; + req.set_bits = hid0_hile; + } else { + req.clr_bits = hid0_hile; + req.set_bits = 0; + } + cpu_change_all_hid0(&req); + current_hile_mode = hile; +} + static void cpu_cleanup_one(void *param __unused) { mtspr(SPR_AMR, 0); @@ -1453,8 +1471,8 @@ static int64_t cpu_cleanup_all(void) void cpu_fast_reboot_complete(void) { - /* Fast reboot will have cleared HID0:HILE */ - current_hile_mode = false; + /* Fast reboot will have set HID0:HILE to skiboot endian */ + current_hile_mode = HAVE_LITTLE_ENDIAN; /* and set HID0:RADIX */ current_radix_mode = true; diff --git a/core/init.c b/core/init.c index 62d9c709f..7fa8bb9c2 100644 --- a/core/init.c +++ b/core/init.c @@ -620,6 +620,7 @@ void __noreturn load_and_boot_kernel(bool is_reboot) cpu_disable_ME_RI_all(); patch_traps(false); + cpu_set_hile_mode(false); /* Clear HILE on all CPUs */ debug_descriptor.state_flags |= OPAL_BOOT_COMPLETE; diff --git a/doc/stb.rst b/doc/stb.rst index 6fc8f73da..84855ca55 100644 --- a/doc/stb.rst +++ b/doc/stb.rst @@ -92,7 +92,7 @@ CVC-verify Service .. code-block:: c int call_cvc_verify(void *buf, size_t size, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log) + size_t hw_key_hash_size, __be64 *log) This function wrapper calls into the *CVC-verify*, which verifies if the firmware code provided in ``@buf`` is properly signed with the keys trusted by diff --git a/hdata/spira.c b/hdata/spira.c index 0d17ae05e..ed15914bf 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -34,7 +34,7 @@ __section(".procin.data") struct proc_init_data proc_init_data = { .regs_ptr = HDIF_IDATA_PTR(offsetof(struct proc_init_data, regs), 0x10), .regs = { .nia = CPU_TO_BE64(0x180), - .msr = CPU_TO_BE64(0x9000000000000000ULL), /* SF | HV */ + .msr = CPU_TO_BE64(MSR_SF | MSR_HV), }, }; diff --git a/include/asm-utils.h b/include/asm-utils.h index 2d26545e7..c3d8c09ea 100644 --- a/include/asm-utils.h +++ b/include/asm-utils.h @@ -28,17 +28,29 @@ /* Load an address via the TOC */ #define LOAD_ADDR_FROM_TOC(r, e) ld r,e@got(%r2) -#define FIXUP_ENDIAN \ - tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ - b 191f; /* Skip trampoline if endian is good */ \ +/* This must preserve LR, so can't use Linux kernel's FIXUP_ENDIAN */ +#define SWITCH_ENDIAN \ .long 0xa600607d; /* mfmsr r11 */ \ .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0xa64b7b7d; /* mthsrr1 r11 */ \ + .long 0xa602687d; /* mflr r11 */ \ .long 0x05009f42; /* bcl 20,31,$+4 */ \ .long 0xa602487d; /* mflr r10 */ \ .long 0x14004a39; /* addi r10,r10,20 */ \ .long 0xa64b5a7d; /* mthsrr0 r10 */ \ - .long 0xa64b7b7d; /* mthsrr1 r11 */ \ - .long 0x2402004c; /* hrfid */ \ + .long 0xa603687d; /* mtlr r11 */ \ + .long 0x2402004c /* hrfid */ + +#define FIXUP_ENDIAN \ + tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ + b 191f; /* Skip trampoline if endian is good */ \ + SWITCH_ENDIAN; /* Do the switch */ \ 191: +#if HAVE_BIG_ENDIAN +#define OPAL_ENTRY_TO_SKIBOOT_ENDIAN +#else +#define OPAL_ENTRY_TO_SKIBOOT_ENDIAN SWITCH_ENDIAN +#endif + #endif /* __ASM_UTILS_H */ diff --git a/include/cpu.h b/include/cpu.h index cda78644d..008f08a68 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -282,6 +282,9 @@ extern void cpu_process_local_jobs(void); /* Check if there's any job pending */ bool cpu_check_jobs(struct cpu_thread *cpu); +/* Set/clear HILE on all CPUs */ +void cpu_set_hile_mode(bool hile); + /* OPAL sreset vector in place at 0x100 */ void cpu_set_sreset_enable(bool sreset_enabled); diff --git a/include/elf.h b/include/elf.h index 93524bb99..8ce37fad4 100644 --- a/include/elf.h +++ b/include/elf.h @@ -9,7 +9,11 @@ /* Generic ELF header */ struct elf_hdr { uint32_t ei_ident; +#ifdef _BIG_ENDIAN #define ELF_IDENT 0x7F454C46 +#else +#define ELF_IDENT 0x464C457F +#endif uint8_t ei_class; #define ELF_CLASS_32 1 #define ELF_CLASS_64 2 diff --git a/include/stack.h b/include/stack.h index 09d22adb6..b0d6df17d 100644 --- a/include/stack.h +++ b/include/stack.h @@ -11,7 +11,11 @@ #define STACK_ENTRY_RESET 0x0100 /* System reset */ #define STACK_ENTRY_SOFTPATCH 0x1500 /* Soft patch (denorm emulation) */ +#if HAVE_BIG_ENDIAN #define STACK_TOC_OFFSET 40 +#else +#define STACK_TOC_OFFSET 24 +#endif /* Safety/ABI gap at top of stack */ #define STACK_TOP_GAP 0x100 diff --git a/libpore/p9_cpu_reg_restore_instruction.H b/libpore/p9_cpu_reg_restore_instruction.H index dd4358a82..cf00ff5e5 100644 --- a/libpore/p9_cpu_reg_restore_instruction.H +++ b/libpore/p9_cpu_reg_restore_instruction.H @@ -61,23 +61,24 @@ enum RLDICR_CONST = 1, MTSPR_CONST1 = 467, MTMSRD_CONST1 = 178, - MR_R0_TO_R10 = 0x7c0a0378, //mr r10, r0 - MR_R0_TO_R21 = 0x7c150378, //mr r21, r0 - MR_R0_TO_R9 = 0x7c090378, //mr r9, r0 - URMOR_CORRECTION = 0x7d397ba6, MFSPR_CONST = 339, - BLR_INST = 0x4e800020, - MTSPR_BASE_OPCODE = 0x7c0003a6, - ATTN_OPCODE = 0x00000200, OPCODE_18 = 18, SELF_SAVE_FUNC_ADD = 0x2300, SELF_SAVE_OFFSET = 0x180, - SKIP_SPR_REST_INST = 0x4800001c, //b . +0x01c - MFLR_R30 = 0x7fc802a6, - SKIP_SPR_SELF_SAVE = 0x3bff0020, //addi r31 r31, 0x20 - MTLR_INST = 0x7fc803a6 //mtlr r30 }; +#define MR_R0_TO_R10 0x7c0a0378UL //mr r10 r0 +#define MR_R0_TO_R21 0x7c150378UL //mr r21 r0 +#define MR_R0_TO_R9 0x7c090378UL //mr r9 r0 +#define URMOR_CORRECTION 0x7d397ba6UL +#define BLR_INST 0x4e800020UL +#define MTSPR_BASE_OPCODE 0x7c0003a6UL +#define ATTN_OPCODE 0x00000200UL +#define SKIP_SPR_REST_INST 0x4800001cUL //b . +0x01c +#define MFLR_R30 0x7fc802a6UL +#define SKIP_SPR_SELF_SAVE 0x3bff0020UL //addi r31 r31 0x20 +#define MTLR_INST 0x7fc803a6UL //mtlr r30 + #ifdef __cplusplus } // namespace stopImageSection ends diff --git a/libstb/cvc.c b/libstb/cvc.c index dca4ac857..4fc29c08d 100644 --- a/libstb/cvc.c +++ b/libstb/cvc.c @@ -305,16 +305,19 @@ int call_cvc_sha512(const uint8_t *data, size_t data_len, uint8_t *digest, if (!service) return OPAL_UNSUPPORTED; - if (service->version == 1) + if (service->version == 1) { + unsigned long msr = mfmsr(); __cvc_sha512_v1((void*) service->addr, data, data_len, digest); - else + assert(msr == mfmsr()); + } else { return OPAL_UNSUPPORTED; + } return OPAL_SUCCESS; } int call_cvc_verify(void *container, size_t len, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log) + size_t hw_key_hash_size, __be64 *log) { ROM_hw_params hw_params; ROM_response rc; @@ -335,12 +338,15 @@ int call_cvc_verify(void *container, size_t len, const void *hw_key_hash, memset(&hw_params, 0, sizeof(ROM_hw_params)); memcpy(&hw_params.hw_key_hash, hw_key_hash, hw_key_hash_size); - if (service->version == 1) + if (service->version == 1) { + unsigned long msr = mfmsr(); rc = __cvc_verify_v1((void*) service->addr, (ROM_container_raw*) container, &hw_params); - else + assert(msr == mfmsr()); + } else { return OPAL_UNSUPPORTED; + } if (log) *log = hw_params.log; diff --git a/libstb/cvc.h b/libstb/cvc.h index 6d8546fb2..ef105f76d 100644 --- a/libstb/cvc.h +++ b/libstb/cvc.h @@ -30,7 +30,7 @@ int cvc_init(void); * */ int call_cvc_verify(void *buf, size_t size, const void *hw_key_hash, - size_t hw_key_hash_size, uint64_t *log); + size_t hw_key_hash_size, __be64 *log); /* * call_cvc_sha512 - Call the CVC-sha512 service to calculate a sha512 hash. From patchwork Wed Oct 9 23:49:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1174214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pWP95zz3z9s7T for ; Thu, 10 Oct 2019 10:57:49 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mCGw10Fr"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pWP94ttdzDqbv for ; Thu, 10 Oct 2019 10:57:49 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::642; helo=mail-pl1-x642.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mCGw10Fr"; dkim-atps=neutral Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pWJ86rLZzDqYq for ; Thu, 10 Oct 2019 10:53:28 +1100 (AEDT) Received: by mail-pl1-x642.google.com with SMTP id f21so1827703plj.10 for ; Wed, 09 Oct 2019 16:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LWxiDD+TLAaK5kjghewoYPBVikv/IPjlXs0oTPgR97k=; b=mCGw10FrrvfTvDOgpiCDvsH4XiftjAQjeSWASb6dTlAJ/E2c9hmmowwJA9I6WunOFY Muqv8ZllfRntkg8kVOlYIAIbdMN91fTZZIOGnX9n0+4qjyLKUXUEHVG+CV9ea0sMTLnP y5qjX8aDNfBMjH+S2VfopZT3ggRqkbkxF3UjW4oFRCPaT3jBEVPyWsCDEyzHJFRGYqny cT1UC0/sVv3wUx6ZXGvq8lPoaZ/NUiPgLv5APZxx8OyKOCy+NHPhBVpB1kMcYB1eSfXN wVW2uyrrX2BKd0xs1ziBw8Z7lhPiQuxXQ5IkiYSM8tKXczJGITiw4WqsZUW29z59d0ZT QTLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LWxiDD+TLAaK5kjghewoYPBVikv/IPjlXs0oTPgR97k=; b=QFbw2gIbz/dtEpkXeMyEqsuO20jCebm7btf4w5Z7HnLLz8mLgXQzMyxBAqcI07P1ZL tlI7orf7sJlh7e6SV+47UwvIBg1fs9Mg1YX4PN3+i9hPl5WBpBn9Hq3lzOp0Lc2PK7Ix J6C76EdyrW7xheth4HoNlPbj/GhoPjIjd78sBSatQiEOLsNnNKHoiIUj4r2BsJBszWVV tXLURaRm0e9KkoTM/dCGIKBrBPBOXY3AkgJAcZVYIoz7/WEYaA7vn7kpT8Ng1U7vCGYY f7I4QlfPJ+qA9pkQAa7s5i65KBBrzlBciRCm4romBUTrpN0JOosSrxvuszfrQNby/igT +fuA== X-Gm-Message-State: APjAAAWgJvNFlmifmEbBS90Xop+q37z5WBlx8I3Sat8dv+FdWGIcosno 6AUg/u1almC2XXlNKJaG4Su9VRqK X-Google-Smtp-Source: APXvYqw+rqM6Ghu5aKQMFet3PtSlJups/pnBlIjJr2QJrbPoVEmuv6osccVg/zYc9MYfo+X0sx+HYA== X-Received: by 2002:a17:902:209:: with SMTP id 9mr6068020plc.25.1570665205680; Wed, 09 Oct 2019 16:53:25 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id y144sm4015675pfb.188.2019.10.09.16.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 16:53:25 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 10 Oct 2019 09:49:51 +1000 Message-Id: <20191009234951.2850-16-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009234951.2850-1-npiggin@gmail.com> References: <20191009234951.2850-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v4 15/15] dt: assorted cleanups X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This replaces several instances dt accesses with higher level primitives throughout the tree. Signed-off-by: Nicholas Piggin --- core/device.c | 7 +++++++ core/pci.c | 20 ++++++++------------ hdata/iohub.c | 21 +++++++-------------- hdata/memory.c | 7 ++----- hdata/paca.c | 2 +- hw/fsp/fsp.c | 2 +- hw/phb4.c | 28 ++++++++++++---------------- hw/vas.c | 4 ++-- include/device.h | 1 + 9 files changed, 41 insertions(+), 51 deletions(-) diff --git a/core/device.c b/core/device.c index 0118d485f..725a67b66 100644 --- a/core/device.c +++ b/core/device.c @@ -593,6 +593,13 @@ u32 dt_property_get_cell(const struct dt_property *prop, u32 index) return fdt32_to_cpu(((const u32 *)prop->prop)[index]); } +u64 dt_property_get_u64(const struct dt_property *prop, u32 index) +{ + assert(prop->len >= (index+1)*sizeof(u64)); + /* Always aligned, so this works. */ + return fdt64_to_cpu(((const u64 *)prop->prop)[index]); +} + void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val) { assert(prop->len >= (index+1)*sizeof(u32)); diff --git a/core/pci.c b/core/pci.c index 6c5c83bea..718569d64 100644 --- a/core/pci.c +++ b/core/pci.c @@ -1547,16 +1547,8 @@ static void __noinline pci_add_one_device_node(struct phb *phb, char name[MAX_NAME]; char compat[MAX_NAME]; uint32_t rev_class, vdid; - __be32 reg[5]; uint8_t intpin; bool is_pcie; - const __be32 ranges_direct[] = { - /* 64-bit direct mapping. We know the bridges - * don't cover the entire address space so - * use 0xf00... as a good compromise. */ - cpu_to_be32(0x02000000), 0x0, 0x0, - cpu_to_be32(0x02000000), 0x0, 0x0, - cpu_to_be32(0xf0000000), 0x0}; pci_cfg_read32(phb, pd->bdfn, 0, &vdid); pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class); @@ -1633,9 +1625,7 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * entry in the "reg" property. That's enough for Linux and we might * even want to make this legit in future ePAPR */ - reg[0] = cpu_to_be32(pd->bdfn << 8); - reg[1] = reg[2] = reg[3] = reg[4] = 0; - dt_add_property(np, "reg", reg, sizeof(reg)); + dt_add_property_cells(np, "reg", pd->bdfn << 8, 0, 0, 0, 0); /* Print summary info about the device */ pci_print_summary_line(phb, pd, np, rev_class, cname); @@ -1670,7 +1660,13 @@ static void __noinline pci_add_one_device_node(struct phb *phb, * (ie. an empty ranges property). * Instead add a ranges property that explicitly translates 1:1. */ - dt_add_property(np, "ranges", ranges_direct, sizeof(ranges_direct)); + dt_add_property_cells(np, "ranges", + /* 64-bit direct mapping. We know the bridges + * don't cover the entire address space so + * use 0xf00... as a good compromise. */ + 0x02000000, 0x0, 0x0, + 0x02000000, 0x0, 0x0, + 0xf0000000, 0x0); } void __noinline pci_add_device_nodes(struct phb *phb, diff --git a/hdata/iohub.c b/hdata/iohub.c index 2af040a2f..ef763a0ee 100644 --- a/hdata/iohub.c +++ b/hdata/iohub.c @@ -95,7 +95,6 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, unsigned int spci_xscom) { struct dt_node *pbcq; - uint32_t reg[6]; unsigned int hdif_vers; /* Get HDIF version */ @@ -109,13 +108,10 @@ static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, /* "reg" property contains in order the PE, PCI and SPCI XSCOM * addresses */ - reg[0] = cpu_to_be32(pe_xscom); - reg[1] = cpu_to_be32(0x20); - reg[2] = cpu_to_be32(pci_xscom); - reg[3] = cpu_to_be32(0x05); - reg[4] = cpu_to_be32(spci_xscom); - reg[5] = cpu_to_be32(0x15); - dt_add_property(pbcq, "reg", reg, sizeof(reg)); + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x20, + pci_xscom, 0x05, + spci_xscom, 0x15); /* A couple more things ... */ dt_add_property_strings(pbcq, "compatible", "ibm,power8-pbcq"); @@ -202,7 +198,6 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, int phb_base) { struct dt_node *pbcq; - uint32_t reg[4]; uint8_t active_phb_mask = hub->fab_br0_pdt; uint32_t pe_xscom = 0x4010c00 + (pec_index * 0x0000400); uint32_t pci_xscom = 0xd010800 + (pec_index * 0x1000000); @@ -214,11 +209,9 @@ static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, return NULL; /* "reg" property contains (in order) the PE and PCI XSCOM addresses */ - reg[0] = cpu_to_be32(pe_xscom); - reg[1] = cpu_to_be32(0x100); - reg[2] = cpu_to_be32(pci_xscom); - reg[3] = cpu_to_be32(0x200); - dt_add_property(pbcq, "reg", reg, sizeof(reg)); + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x100, + pci_xscom, 0x200); /* The hubs themselves go under the stacks */ dt_add_property_strings(pbcq, "compatible", "ibm,power9-pbcq"); diff --git a/hdata/memory.c b/hdata/memory.c index 9e5e99b9c..7839dea3f 100644 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -77,24 +77,21 @@ static void append_chip_id(struct dt_node *mem, u32 id) { struct dt_property *prop; size_t len, i; - be32 *p; prop = __dt_find_property(mem, "ibm,chip-id"); if (!prop) return; len = prop->len >> 2; - p = (be32*)prop->prop; /* Check if it exists already */ for (i = 0; i < len; i++) { - if (be32_to_cpu(p[i]) == id) + if (dt_property_get_cell(prop, i) == id) return; } /* Add it to the list */ dt_resize_property(&prop, (len + 1) << 2); - p = (be32 *)prop->prop; - p[len] = cpu_to_be32(id); + dt_property_set_cell(prop, len, id); } static void update_status(struct dt_node *mem, uint32_t status) diff --git a/hdata/paca.c b/hdata/paca.c index 3e8d89856..7f6c5e7b7 100644 --- a/hdata/paca.c +++ b/hdata/paca.c @@ -97,7 +97,7 @@ static struct dt_node *find_cpu_by_hardware_proc_id(struct dt_node *root, if (!prop) return NULL; - if (be32_to_cpu(*(be32 *)prop->prop) == hw_proc_id) + if (dt_property_get_cell(prop, 0) == hw_proc_id) return i; } return NULL; diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 7193c6f4c..41da2ea3c 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -1915,7 +1915,7 @@ static void fsp_init_links(struct dt_node *fsp_node) u64 reg; u32 link; - link = be32_to_cpu(((const __be32 *)linksprop->prop)[i]); + link = dt_property_get_cell(linksprop, i); fiop = &fsp->iopath[i]; fiop->psi = psi_find_link(link); if (fiop->psi == NULL) { diff --git a/hw/phb4.c b/hw/phb4.c index d202b4cfa..921c4c2f4 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5495,11 +5495,11 @@ static bool phb4_calculate_windows(struct phb4 *p) "ibm,mmio-windows", -1); assert(prop->len >= (2 * sizeof(uint64_t))); - p->mm0_base = be64_to_cpu(((__be64 *)prop->prop)[0]); - p->mm0_size = be64_to_cpu(((__be64 *)prop->prop)[1]); + p->mm0_base = dt_property_get_u64(prop, 0); + p->mm0_size = dt_property_get_u64(prop, 1); if (prop->len > 16) { - p->mm1_base = be64_to_cpu(((__be64 *)prop->prop)[2]); - p->mm1_size = be64_to_cpu(((__be64 *)prop->prop)[3]); + p->mm1_base = dt_property_get_u64(prop, 2); + p->mm1_size = dt_property_get_u64(prop, 3); } /* Sort them so that 0 is big and 1 is small */ @@ -5611,11 +5611,11 @@ static void phb4_create(struct dt_node *np) /* Get the various XSCOM register bases from the device-tree */ prop = dt_require_property(np, "ibm,xscom-bases", 5 * sizeof(uint32_t)); - p->pe_xscom = be32_to_cpu(((__be32 *)prop->prop)[0]); - p->pe_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[1]); - p->pci_xscom = be32_to_cpu(((__be32 *)prop->prop)[2]); - p->pci_stk_xscom = be32_to_cpu(((__be32 *)prop->prop)[3]); - p->etu_xscom = be32_to_cpu(((__be32 *)prop->prop)[4]); + p->pe_xscom = dt_property_get_cell(prop, 0); + p->pe_stk_xscom = dt_property_get_cell(prop, 1); + p->pci_xscom = dt_property_get_cell(prop, 2); + p->pci_stk_xscom = dt_property_get_cell(prop, 3); + p->etu_xscom = dt_property_get_cell(prop, 4); /* * We skip the initial PERST assertion requested by the generic code @@ -5775,7 +5775,6 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint64_t val, phb_bar = 0, irq_bar = 0, bar_en; uint64_t mmio0_bar = 0, mmio0_bmask, mmio0_sz; uint64_t mmio1_bar = 0, mmio1_bmask, mmio1_sz; - uint64_t reg[4]; void *foo; uint64_t mmio_win[4]; unsigned int mmio_win_sz; @@ -5873,18 +5872,15 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, prlog_once(PR_DEBUG, "Version reg: 0x%016llx\n", in_be64(foo)); /* Create PHB node */ - reg[0] = cpu_to_be64(phb_bar); - reg[1] = cpu_to_be64(0x1000); - reg[2] = cpu_to_be64(irq_bar); - reg[3] = cpu_to_be64(0x10000000); - np = dt_new_addr(dt_root, "pciex", phb_bar); if (!np) return; dt_add_property_strings(np, "compatible", "ibm,power9-pciex", "ibm,ioda3-phb"); dt_add_property_strings(np, "device_type", "pciex"); - dt_add_property(np, "reg", reg, sizeof(reg)); + dt_add_property_u64s(np, "reg", + phb_bar, 0x1000, + irq_bar, 0x10000000); /* Everything else is handled later by skiboot, we just * stick a few hints here diff --git a/hw/vas.c b/hw/vas.c index 3c5ebc920..42130452f 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -401,8 +401,8 @@ static void create_mm_dt_node(struct proc_chip *chip) pbar_start, pbar_len, pbf_start, pbf_nbits); - dt_add_property(dn, "ibm,vas-id", &vas_id, sizeof(vas_id)); - dt_add_property(dn, "ibm,chip-id", &gcid, sizeof(gcid)); + dt_add_property_cells(dn, "ibm,vas-id", vas_id); + dt_add_property_cells(dn, "ibm,chip-id", gcid); } /* diff --git a/include/device.h b/include/device.h index 25325ec07..4f7a0983f 100644 --- a/include/device.h +++ b/include/device.h @@ -130,6 +130,7 @@ void dt_resize_property(struct dt_property **prop, size_t len); void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val); u32 dt_property_get_cell(const struct dt_property *prop, u32 index); +u64 dt_property_get_u64(const struct dt_property *prop, u32 index); /* First child of this node. */ struct dt_node *dt_first(const struct dt_node *root);