From patchwork Wed Oct 2 14:52:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1170737 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y42LNP0X"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jzdt5tflz9sPc for ; Thu, 3 Oct 2019 00:53:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727540AbfJBOxG (ORCPT ); Wed, 2 Oct 2019 10:53:06 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:46641 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726137AbfJBOxF (ORCPT ); Wed, 2 Oct 2019 10:53:05 -0400 Received: by mail-wr1-f68.google.com with SMTP id o18so19981741wrv.13; Wed, 02 Oct 2019 07:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PYXzXb3OB7jSZRuNVFj0gMlw+CgNdBWs0kruPSOz3YU=; b=Y42LNP0XJQuHhLOObBXx50wVAVYVAqA4jT5EERcF98mMSZcEyfi4nWX66O78ecHVa/ X/aHwLin9XQG0LxUFaajZBRTFXPZls45G4bxyfsY1Im6amFPOPZaoI+7+IWcbfhdrSTo 9WJB5p8qJo4Nzog7Do0MXeXPMCfSMK3MOdIQtdMqbSYwQiikzc2jeih5FLt/qErOirkv FMUmMP2H595ZkrDZH3XorUd3f7Aqc2yXw8FRkkP+2rG0io/j6WZNLGy4ERxv5/OzVQ82 Mp1m6jLs8NxULkyCLMWOudkKDvgwy++f0EQMqs/pxii2lIYPNedpsWUyOqKH5gXrAqny wuRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PYXzXb3OB7jSZRuNVFj0gMlw+CgNdBWs0kruPSOz3YU=; b=h/o39HMEbqxO8RqJEpZr9GwhVb019i1/YbfjhvtehqCERVLR2oab3vQsQUFmyYfYCO OJMz/X0zDDTobB5UqWYrm/0KPqzWrDE3O4OV9hFRKJctDEdue3LSyI9VHzpBlQ3OZY/P L51wWJ+rOf8wY2q84Gp84Yn2E5WMsJ2DfIY49a7wKsNFd+3DfGZ8BPqwyOjkXE7RFjXU qrgNLfG188klSoRBiSvUGR/P+XpD/PBekhrECRR6OcA3brSiLVrF4LQB4x7XKvmQ8hv7 /V/o+yQiYMg+HPMTA0LImMqGmIIvGOpz32RXp8tATDO5SPcNNr6sa8ljaj6bC7JVycXV CutQ== X-Gm-Message-State: APjAAAXZRnwUoFjP1O490vPa9h1crrEqBsbjnxn5miICxKrUiMUkmQgd ieTUi74rWO4QBXqgJLdGrmU= X-Google-Smtp-Source: APXvYqzuhOs5vzF/CINZB2NMdU92KduN02xM2AGJ2sH5fWCMdQaPvFWCrCKD48ey6OVJBBLYH8ELLQ== X-Received: by 2002:a5d:4ecf:: with SMTP id s15mr2968739wrv.234.1570027983243; Wed, 02 Oct 2019 07:53:03 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id f8sm4307736wmb.37.2019.10.02.07.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 07:53:02 -0700 (PDT) From: Thierry Reding To: "David S . Miller" Cc: Jose Abreu , Alexandre Torgue , Giuseppe Cavallaro , Florian Fainelli , Jon Hunter , Bitan Biswas , netdev@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH net-next v4 1/2] net: stmmac: Only enable enhanced addressing mode when needed Date: Wed, 2 Oct 2019 16:52:57 +0200 Message-Id: <20191002145258.178745-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002145258.178745-1-thierry.reding@gmail.com> References: <20191002145258.178745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Enhanced addressing mode is only required when more than 32 bits need to be addressed. Add a DMA configuration parameter to enable this mode only when needed. Signed-off-by: Thierry Reding --- Changes in v4: - enable EAME only if DMA addresses can be larger than 32 bits drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 ++++- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +++++++ include/linux/stmmac.h | 1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 965cbe3e6f51..7cc331996cd8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -27,7 +27,10 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, if (dma_cfg->aal) value |= XGMAC_AAL; - writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE); + if (dma_cfg->eame) + value |= XGMAC_EAME; + + writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); } static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index c76a1336a451..b8ac1744950e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4515,6 +4515,13 @@ int stmmac_dvr_probe(struct device *device, if (!ret) { dev_info(priv->device, "Using %d bits DMA width\n", priv->dma_cap.addr64); + + /* + * If more than 32 bits can be addressed, make sure to + * enable enhanced addressing mode. + */ + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) + priv->plat->dma_cfg->eame = true; } else { ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); if (ret) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index dc60d03c4b60..86f9464c3f5d 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -92,6 +92,7 @@ struct stmmac_dma_cfg { int fixed_burst; int mixed_burst; bool aal; + bool eame; }; #define AXI_BLEN 7 From patchwork Wed Oct 2 14:52:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1170739 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pMgw2egX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jzdy0Lzxz9sPc for ; Thu, 3 Oct 2019 00:53:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727735AbfJBOxJ (ORCPT ); Wed, 2 Oct 2019 10:53:09 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:37336 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726137AbfJBOxJ (ORCPT ); Wed, 2 Oct 2019 10:53:09 -0400 Received: by mail-wm1-f67.google.com with SMTP id f22so7321022wmc.2; Wed, 02 Oct 2019 07:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uOeMC9QJIgmJhWdw1hsRV5m6zhZBnDGlsT9nxsYcYJk=; b=pMgw2egXlzrLRfNFrUyfhT7jsxzZI7o8OKtq+Q/3dJOl0qS5MV5jmngfJa/rJDFDXc QcgASrbA43oudaxaVpB0qHwu+vcRkpPc2nlp/0Bt/5B8Vp44sGp8s0N8R6nT8Z05w5R7 EZZD1VYXezqauOjFptj2v5oebfwdvUqCB90x+OiuXb/Z972gf5Si3auCpJkCz6IjoA1K 9is/+aVTnr9qHNIguhVJOMXutU7dFjHeUTEtQN/GqKYklQIxDBUftOVJ2TwZZvvBx/U+ +5KbyjkZ1LQvGWEnMHdjE4DXwHKiE0AA0rbM+veIMJT2s5JMQ4IwJoCVU+zP74G4G1h6 v0TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOeMC9QJIgmJhWdw1hsRV5m6zhZBnDGlsT9nxsYcYJk=; b=VmGt9WhJAmx3IzNrWVsOdQkSNZOfRPLByzd+9el31I2FZJArYz56QSvY9YmcdEPXZW xTDg1WQQWIh7+KhmhyvjI3Vs5IkNIrJijc3gg2FDGMUxGPSGKITVLelInbT04VkXfK0c 7ujvIXFntS4hrn4/KDS+4mK3rfvYRJbgNmFje6pDUv7RMzdnznOI1aSblQIoa4+JBcdg 0N1yHvY3VrqxMwWOwS99WlkFw9VKV1MOZG7SJKgk4k8EEIeoAFANiFrp95i1Gfm/kRp/ ssOeGNibQkm5lemErfGGauBjacA4bbpnzW1X4/j++9L6DPmgzC4XI0r0KAezMIzb3XkO VZ/A== X-Gm-Message-State: APjAAAXwZa0XgqHh2Fr1gWb13fT0fQFXmdeo8UcOHMRRHT+xB0LSD1GB Hkd5JhEBl+lRHaBVUVv4Brc= X-Google-Smtp-Source: APXvYqwrriSwRm56050U2yAevLz1JguR/SlQ20I3rFbvPtrmoOEXZWSMK+qhly90EExj1lAw85bXTg== X-Received: by 2002:a1c:6a03:: with SMTP id f3mr3137029wmc.167.1570027986301; Wed, 02 Oct 2019 07:53:06 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id d4sm20998554wrq.22.2019.10.02.07.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 07:53:04 -0700 (PDT) From: Thierry Reding To: "David S . Miller" Cc: Jose Abreu , Alexandre Torgue , Giuseppe Cavallaro , Florian Fainelli , Jon Hunter , Bitan Biswas , netdev@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH net-next v4 2/2] net: stmmac: Support enhanced addressing mode for DWMAC 4.10 Date: Wed, 2 Oct 2019 16:52:58 +0200 Message-Id: <20191002145258.178745-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002145258.178745-1-thierry.reding@gmail.com> References: <20191002145258.178745-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding The address width of the controller can be read from hardware feature registers much like on XGMAC. Add support for parsing the ADDR64 field so that the DMA mask can be set accordingly. This avoids getting swiotlb involved for DMA on Tegra186 and later. Also make sure that the upper 32 bits of the DMA address are written to the DMA descriptors when enhanced addressing mode is used. Similarily, for each channel, the upper 32 bits of the DMA descriptor ring's base address also need to be programmed to make sure the correct memory can be fetched when the DMA descriptor ring is located beyond the 32-bit boundary. Signed-off-by: Thierry Reding --- Changes in v4: - only write upper 32 bits when necessary Changes in v3: - unconditionally write upper 32 bits Changes in v2: - also program the upper 32 bits of the DMA descriptor base address for each channel drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 + .../ethernet/stmicro/stmmac/dwmac4_descs.c | 4 +-- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 28 +++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 3 ++ 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 89a3420eba42..2fe45fa3c482 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -205,6 +205,7 @@ enum power_event { #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) #define GMAC_HW_FEAT_AVSEL BIT(20) #define GMAC_HW_TSOEN BIT(18) +#define GMAC_HW_ADDR64 GENMASK(15, 14) #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c index 15eb1abba91d..707ab5eba8da 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c @@ -431,8 +431,8 @@ static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr) static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr) { - p->des0 = cpu_to_le32(addr); - p->des1 = 0; + p->des0 = cpu_to_le32(lower_32_bits(addr)); + p->des1 = cpu_to_le32(upper_32_bits(addr)); } static void dwmac4_clear(struct dma_desc *p) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 68c157979b94..229059cef949 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -79,6 +79,10 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) + writel(upper_32_bits(dma_rx_phy), + ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); } @@ -97,6 +101,10 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); + if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) + writel(upper_32_bits(dma_tx_phy), + ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); } @@ -132,6 +140,9 @@ static void dwmac4_dma_init(void __iomem *ioaddr, if (dma_cfg->aal) value |= DMA_SYS_BUS_AAL; + if (dma_cfg->eame) + value |= DMA_SYS_BUS_EAME; + writel(value, ioaddr + DMA_SYS_BUS_MODE); } @@ -356,6 +367,23 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr, dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; + + dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; + switch (dma_cap->addr64) { + case 0: + dma_cap->addr64 = 32; + break; + case 1: + dma_cap->addr64 = 40; + break; + case 2: + dma_cap->addr64 = 48; + break; + default: + dma_cap->addr64 = 32; + break; + } + /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by * shifting and store the sizes in bytes. */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h index b66da0237d2a..5299fa1001a3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -65,6 +65,7 @@ #define DMA_SYS_BUS_MB BIT(14) #define DMA_AXI_1KBBE BIT(13) #define DMA_SYS_BUS_AAL BIT(12) +#define DMA_SYS_BUS_EAME BIT(11) #define DMA_AXI_BLEN256 BIT(7) #define DMA_AXI_BLEN128 BIT(6) #define DMA_AXI_BLEN64 BIT(5) @@ -91,7 +92,9 @@ #define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x) #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8) +#define DMA_CHAN_TX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x10) #define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14) +#define DMA_CHAN_RX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x18) #define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c) #define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20) #define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)