From patchwork Fri Sep 20 17:00:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1165365 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LyQN9rMX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Zg2h6R2Cz9sNk for ; Sat, 21 Sep 2019 03:00:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391640AbfITRAn (ORCPT ); Fri, 20 Sep 2019 13:00:43 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:41302 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391506AbfITRAm (ORCPT ); Fri, 20 Sep 2019 13:00:42 -0400 Received: by mail-wr1-f68.google.com with SMTP id h7so7452142wrw.8; Fri, 20 Sep 2019 10:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PYRjHANJ0MWxLPIUwtgxGbxSiQPDnOdCGXrlF6OG6sU=; b=LyQN9rMXftusXw4XU5bgx8xZjtrXZGdGwiriDtRRBb+NbwDw9oJwjFS4a+jBI8foWq /5BjZL/eLtkw+IOSCHwk0r/VXxw8F/6gf1+ddTo/DhTkgjymFigCh4iLrWNVrbGIRmjm NHOTSqDo8ihWDyHP53CrTAVevpjP35Hr1Hr6dfR87xAUdZ17X6pljXdnevo7zUXo5J1d vKZcA1jbS/ZS1Q4SDX/HVpjuhTJPDq1tzXEqIb7oJ3pMdDoFVuNictfO4DxJLQpKmjYX sJwG70oE6qhEX5ggTvi9/OQ7PHscODPrRgHGatCnhlv7/uzbZ05pVomGVGXwxJdQgyPg mngA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PYRjHANJ0MWxLPIUwtgxGbxSiQPDnOdCGXrlF6OG6sU=; b=Qzdgkh0XyypTLDG51uJwSjAdrfFhm/89lImMENCq4rxEGowtNefMXhMYoq0/vbTaA3 aurLSPq2FmMfkvFL+1dwd0Kd0ooKIRVfPh3gUI+pfuqRzRxDe8/WJj1t6W3Fvhdjx19M n1iX8tSDnK7uefQiqruAioRKbg2VtaXd1xhpJZEv8ESSqoCdYouoD6yHo3PVsaqUXt5l nQbxzcbgVqMhKauEvl8gsOsrTSKtQcri4h8bffKlbFlFq3OuGlS/BuCH0odtaahkbUIL xh38raj8XC/jr+Hf+bjezNwM3epYWQMVtzWKzdf7Ug8WHz5fk+lQAqmnmPJEgVT4XT8b Sdkg== X-Gm-Message-State: APjAAAVnnrOvzNjLY01qdI80kT/CZI58gsOgBbXrZmk8gGe77tNSOZ/0 U7AykmQQTnbwA8EgJis+Cww= X-Google-Smtp-Source: APXvYqwG+IDZfUBwpXjVeS1KW3NuGTdzjIGF/+u7zxEYpfiREVdBPQ/7EEdx3/94+Hk5Gey3cXBvaQ== X-Received: by 2002:a5d:62c8:: with SMTP id o8mr12317178wrv.350.1568998840543; Fri, 20 Sep 2019 10:00:40 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id y13sm3513601wrg.8.2019.09.20.10.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2019 10:00:39 -0700 (PDT) From: Thierry Reding To: "David S . Miller" Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Florian Fainelli , Jon Hunter , Bitan Biswas , netdev@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 1/2] net: stmmac: Only enable enhanced addressing mode when needed Date: Fri, 20 Sep 2019 19:00:35 +0200 Message-Id: <20190920170036.22610-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190920170036.22610-1-thierry.reding@gmail.com> References: <20190920170036.22610-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Enhanced addressing mode is only required when more than 32 bits need to be addressed. Add a DMA configuration parameter to enable this mode only when needed. Signed-off-by: Thierry Reding --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 ++++- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++++++ include/linux/stmmac.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 64956465c030..3e00fd8befcf 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -27,7 +27,10 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, if (dma_cfg->aal) value |= XGMAC_AAL; - writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE); + if (dma_cfg->eame) + value |= XGMAC_EAME; + + writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); } static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 06ccd216ae90..ecd461207dbc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4497,6 +4497,12 @@ int stmmac_dvr_probe(struct device *device, if (!ret) { dev_info(priv->device, "Using %d bits DMA width\n", priv->dma_cap.addr64); + + /* + * If more than 32 bits can be addressed, make sure to + * enable enhanced addressing mode. + */ + priv->plat->dma_cfg->eame = true; } else { ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); if (ret) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 7ad7ae35cf88..d300ac907c76 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -92,6 +92,7 @@ struct stmmac_dma_cfg { int fixed_burst; int mixed_burst; bool aal; + bool eame; }; #define AXI_BLEN 7 From patchwork Fri Sep 20 17:00:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1165367 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gJiY4Nmd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Zg2l6870z9sCJ for ; Sat, 21 Sep 2019 03:00:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391715AbfITRAq (ORCPT ); Fri, 20 Sep 2019 13:00:46 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:38247 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391591AbfITRAo (ORCPT ); Fri, 20 Sep 2019 13:00:44 -0400 Received: by mail-wr1-f67.google.com with SMTP id l11so7479709wrx.5; Fri, 20 Sep 2019 10:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AOBfqbVXzAlxSsTo7twuMhvYkmI6Dik7sGdBy1OQnRw=; b=gJiY4NmdHBtIvaxk6Ijre/8ZmGvdlA8ITr4X26dAXp+W/UfqbWMvG3bi3zLsqMpN/E 6R2Dxoc/1RwoQp3E5EsnLWYgkcYJDfu62x/Qcger+pG9q0xSgWenItqsZlF2BCwPhwX6 DCsqqLvdnbyEBQ7OTy7Vb0UW7Iu+Ei5x40QGn75ntz/X7LFDtxFBTa0pMQJ5mQ6u7qo+ rSWBnxZNekxZ8l27DvK+2LGj194KKp5Yrq97T48d5EWIWhKb/a97FopGS5asDMSENNNR J6AaR8ZAdyJah4kyJ8vedHRo5qukNg8O6KxnE5IRQmI8D1Ao2xWJLk+bl+ZtmMFR3vZW UBTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AOBfqbVXzAlxSsTo7twuMhvYkmI6Dik7sGdBy1OQnRw=; b=thmFlyscF6LaFQIs45+KXWn8FknvEopPbrYF/2+u+uyQuqtonNzV5KzsS+5MS1+cU+ OcRbqx/TNOsoAp+C+R7/1P1OMTLhXtc2mlhPANNAC8KPCfab+qfWZ+vaQy+eux4enHna yhB2Pajb15uR6Ue+BguDb07uoU7v/yDoFar9C95lIXp9krwlTv+n0lWWyP1UcPsiCJhZ 9e21wa7KERINghqGnNKOqDu2jrKhY3ryBnjZt6RabtMrB12pD84Qr8AYBZEIKuRk6qO9 FNAEhdpCJdVGQ75DSoBXkEAFqRjZtxJ01izipE42NdJ5gTITtZJd6vjp/B+TCjSzNJ1K 2ASg== X-Gm-Message-State: APjAAAWl+uAfmq6eKu7f3y0AAXU26UGNnmXYdKfIcUmkqnnelQBBNBCS hC2rRAqolBPFKQHzN/rlvTg= X-Google-Smtp-Source: APXvYqzHRXBzqtaLZXmoyzQcfliuExv+Zq02rByaIw9P8b9cwUUmtmg2bpJKXRDSzWYFsN0rkSUZng== X-Received: by 2002:adf:ead2:: with SMTP id o18mr12563892wrn.107.1568998842562; Fri, 20 Sep 2019 10:00:42 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id a18sm4902104wrh.25.2019.09.20.10.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2019 10:00:41 -0700 (PDT) From: Thierry Reding To: "David S . Miller" Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Florian Fainelli , Jon Hunter , Bitan Biswas , netdev@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 2/2] net: stmmac: Support enhanced addressing mode for DWMAC 4.10 Date: Fri, 20 Sep 2019 19:00:36 +0200 Message-Id: <20190920170036.22610-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190920170036.22610-1-thierry.reding@gmail.com> References: <20190920170036.22610-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding The address width of the controller can be read from hardware feature registers much like on XGMAC. Add support for parsing the ADDR64 field so that the DMA mask can be set accordingly. This avoids getting swiotlb involved for DMA on Tegra186 and later. Also make sure that the upper 32 bits of the DMA address are written to the DMA descriptors when enhanced addressing mode is used. Similarily, for each channel, the upper 32 bits of the DMA descriptor ring's base address also need to be programmed to make sure the correct memory can be fetched when the DMA descriptor ring is located beyond the 32-bit boundary. Signed-off-by: Thierry Reding --- Changes in v3: - unconditionally write upper 32 bits Changes in v2: - also program the upper 32 bits of the DMA descriptor base address for each channel drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 + .../ethernet/stmicro/stmmac/dwmac4_descs.c | 4 ++-- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 22 +++++++++++++++++++ .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 3 +++ 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 2ed11a581d80..f634fa09dffc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -183,6 +183,7 @@ enum power_event { #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24) #define GMAC_HW_FEAT_AVSEL BIT(20) #define GMAC_HW_TSOEN BIT(18) +#define GMAC_HW_ADDR64 GENMASK(15, 14) #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6) #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c index dbde23e7e169..d546041d2fcd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c @@ -431,8 +431,8 @@ static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr) static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr) { - p->des0 = cpu_to_le32(addr); - p->des1 = 0; + p->des0 = cpu_to_le32(lower_32_bits(addr)); + p->des1 = cpu_to_le32(upper_32_bits(addr)); } static void dwmac4_clear(struct dma_desc *p) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 3ed5508586ef..8439dd84f786 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -79,6 +79,7 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); + writel(upper_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); } @@ -97,6 +98,7 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); + writel(upper_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); } @@ -132,6 +134,9 @@ static void dwmac4_dma_init(void __iomem *ioaddr, if (dma_cfg->aal) value |= DMA_SYS_BUS_AAL; + if (dma_cfg->eame) + value |= DMA_SYS_BUS_EAME; + writel(value, ioaddr + DMA_SYS_BUS_MODE); } @@ -354,6 +359,23 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr, dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; + + dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; + switch (dma_cap->addr64) { + case 0: + dma_cap->addr64 = 32; + break; + case 1: + dma_cap->addr64 = 40; + break; + case 2: + dma_cap->addr64 = 48; + break; + default: + dma_cap->addr64 = 32; + break; + } + /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by * shifting and store the sizes in bytes. */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h index b66da0237d2a..5299fa1001a3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -65,6 +65,7 @@ #define DMA_SYS_BUS_MB BIT(14) #define DMA_AXI_1KBBE BIT(13) #define DMA_SYS_BUS_AAL BIT(12) +#define DMA_SYS_BUS_EAME BIT(11) #define DMA_AXI_BLEN256 BIT(7) #define DMA_AXI_BLEN128 BIT(6) #define DMA_AXI_BLEN64 BIT(5) @@ -91,7 +92,9 @@ #define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x) #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) #define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8) +#define DMA_CHAN_TX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x10) #define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14) +#define DMA_CHAN_RX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x18) #define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c) #define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20) #define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)