From patchwork Thu Sep 12 09:17:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 1161457 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=prevas.dk Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=prevas.se header.i=@prevas.se header.b="Yjzfkyt6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46TYBr0GRcz9s4Y for ; Thu, 12 Sep 2019 19:20:03 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6DA87C21E08; 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Thu, 12 Sep 2019 09:17:09 +0000 Received: from AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b]) by AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b%3]) with mapi id 15.20.2241.018; Thu, 12 Sep 2019 09:17:09 +0000 From: Rasmus Villemoes To: "u-boot@lists.denx.de" Thread-Topic: [PATCH 1/4] arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX Thread-Index: AQHVaUra4B75hYKn4kqLSZqciTHbXA== Date: Thu, 12 Sep 2019 09:17:09 +0000 Message-ID: <20190912091656.14301-2-rasmus.villemoes@prevas.dk> References: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> In-Reply-To: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0202CA0019.eurprd02.prod.outlook.com (2603:10a6:3:8c::29) To AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:131::7) x-mailer: git-send-email 2.20.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasmus.Villemoes@prevas.se; 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DIR:OUT; SFP:1102; SCL:1; SRVR:AM7PR10MB3160; H:AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: H2Zts7T9FvOfnMug+MGmhX2seSkDV6HyujqaGIHoQfyXrL5pVgtXiRKeAmkMnmyNmb9ZK1F/g5AZ7F5sBfua/DELCFaCJE5QTDB5gfxtXRDWaH/jSZ/CwhcmRLgorqh6mqOkwacxfq5lKXJwoKbp25D8l2bbLzNGZtyJ76xJ07+dk0Ou/OCkqCREI9reWkPnGPAKb1V59tI2cknQD2aqcuEBk7m+Olv5zNTUMlQ22i3/bd6HiTcyGdPMGCt/EJibSKHNNVA3JjlK3I6NNWfCBRuYZJg4QeZicDEyhTxrK4D0n3Z109e0m0dSQLx1nABqBGarDfoMaPr0GARQmza5aiOTamvtQCTpikQvkPIEZudl6q2m3LdsWeN4x0/gqDDXIV3U9x5L1w4TbtpWITiICJIHFAtIsaJW37ROldFFtFI= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: fcb21faa-b933-4b89-4d28-08d73761fcfa X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2019 09:17:09.6325 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UFpo9yJi3uzxbYc/8vzDyXSRGGScMIYVpmbWImZLvtiC3+z4ieUgynSzydU3BPxyx92hGl3S6hJzaN7R9gYi6Gw3lowEBVTTiDnxmYXlt2I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3160 Cc: Rasmus Villemoes , "NXP i.MX U-Boot Team" , Marek Vasut Subject: [U-Boot] [PATCH 1/4] arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then busy-waiting for it to actually clear. My board hung. The data sheet agrees, these registers do not have _set, _clr, _tog, so fix up the definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody uses those non-existing ops registers. Signed-off-by: Rasmus Villemoes --- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h | 6 ++++-- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 15 ++++++++++----- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h index 6e9ffeb6d5..50fdc9cd03 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h @@ -24,8 +24,10 @@ struct mxs_clkctrl_regs { mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */ + uint32_t hw_clkctrl_ssp0; /* 0x70 */ + uint32_t reserved_ssp0[3]; /* 0x74-0x7c */ + uint32_t hw_clkctrl_gpmi; /* 0x80 */ + uint32_t reserved_gpmi[3]; /* 0x84-0x8c */ mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h index 01e0a7a053..caef9e4b1f 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h @@ -27,11 +27,16 @@ struct mxs_clkctrl_regs { mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + uint32_t hw_clkctrl_ssp0; /* 0x90 */ + uint32_t reserved_ssp0[3]; /* 0x94-0x9c */ + uint32_t hw_clkctrl_ssp1; /* 0xa0 */ + uint32_t reserved_ssp1[3]; /* 0xa4-0xac */ + uint32_t hw_clkctrl_ssp2; /* 0xb0 */ + uint32_t reserved_ssp2[3]; /* 0xb4-0xbc */ + uint32_t hw_clkctrl_ssp3; /* 0xc0 */ + uint32_t reserved_ssp3[3]; /* 0xc4-0xcc */ + uint32_t hw_clkctrl_gpmi; /* 0xd0 */ + uint32_t reserved_gpmi[3]; /* 0xd4-0xdc */ mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ From patchwork Thu Sep 12 09:17:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 1161464 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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DIR:OUT; SFP:1102; SCL:1; SRVR:AM7PR10MB3480; H:AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: i3yOdnvlnE4K6kov16Vqxsa2L58hXsmuD58mgXyvrqyh5cqBGYpHa0iB+dPSL6YQ3l0fTFZP8Lds/ay+9YhG4yMJSI5zmfQFG6kHnlo84RwE79K7Np1DbTVGxz0ybygv7DR9ZEUG/QeU6AU8Ff6oY9mvD8X7o8boItxxzNf6jhYHEL36nJJRLOQ3AxuUbEC2zGZz037SLN4felyU6YUVj9t9tKE5Htc0RsNiTyGqapcTpfZxlTkHfktfU39iZlMlfgJMQ8UjPz8G7jAZgrnyq9fOhEaAUI33dWDjO/aMp+zy6T5aDsW3b8oztUh5Wijsp8lyCHbUqQ8ICTreO02hqilY0VJXZ/lFhDeWVoTjp7oqYQQ/gGBbMbgrft3xrzijWzUJukDKlPLMr8gcD0UAVQtCw45plGmVKdhBkWLMduI= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 725485a8-f092-45e5-6a33-08d73761fdb8 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2019 09:17:10.6172 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cAkb5g6tUBtZ2WpA5iboQ7Zmw2usf5aJmZm1LoL+IOvD9s1TR58W14xSUUXqQEKezJ1g4I6suzacodBLgSOZi/9vLvSlPA2GyvhQ8lwC8mA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3480 Cc: Rasmus Villemoes , "NXP i.MX U-Boot Team" , Marek Vasut Subject: [U-Boot] [PATCH 2/4] arm: mxs: fix comments in arch_cpu_init to match the code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The comment says to clear the bypass bit, but in fact it sets it, thus selecting ref_xtal. And the next line of code does not set the divider to 12, but to (the reset value of) 1. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 85c65dcb44..585c53baf6 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -98,11 +98,11 @@ int arch_cpu_init(void) /* * Enable NAND clock */ - /* Clear bypass bit */ + /* Set bypass bit */ writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, &clkctrl_regs->hw_clkctrl_clkseq_set); - /* Set GPMI clock to ref_gpmi / 12 */ + /* Set GPMI clock to ref_xtal / 1 */ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); From patchwork Thu Sep 12 09:17:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 1161463 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 12 Sep 2019 09:17:11 +0000 Received: from AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b]) by AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b%3]) with mapi id 15.20.2241.018; Thu, 12 Sep 2019 09:17:11 +0000 From: Rasmus Villemoes To: "u-boot@lists.denx.de" Thread-Topic: [PATCH 3/4] arm: mxs: be more careful when enabling gpmi_clk Thread-Index: AQHVaUrbOK7kNHF69EeBbQbZflejeQ== Date: Thu, 12 Sep 2019 09:17:11 +0000 Message-ID: <20190912091656.14301-4-rasmus.villemoes@prevas.dk> References: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> In-Reply-To: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0202CA0019.eurprd02.prod.outlook.com (2603:10a6:3:8c::29) To AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:131::7) x-mailer: git-send-email 2.20.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasmus.Villemoes@prevas.se; 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DIR:OUT; SFP:1102; SCL:1; SRVR:AM7PR10MB3480; H:AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: jK4CtAXewGUvDo2lrVHWMBwgNFVJVBaU6u5b8DgIdTKwJ9bRv1B7IK3E1udzPHHPyIcodR0+OoET4qCQzRZ90nFFmRThYhYW28xw+fF/n/x6UE1XGOy6AM/vD+ZbnfWtH5ArVQifgI1F2ENrbI+rBpu6n6BHIvgpxVV1NxD4eGgXCxa9Td/BAXl8AAjoqQujYlWmMzSpnNkoQDyrHOfwAgHyTmv18jOUwgRCkGlcqh3gT9vPkY1+jwRzMfuRfO3zIZy/H+DLQBkJizSm/em0iXQm/URAuB65goy03ynBQ0C0b2axYsj18fj6zTQYZJ1yjvEBmi0r5wEn/bSL0/ODoeNqxv249HDw7qKQuRWb8usdXPmuTQlofqY2Lv15uDDGcUaN+7o4YKPqsmr/Vbxpmyz0YVUXrH19DdsodlpANuA= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: b0be0a4a-858b-4d0e-7ca7-08d73761fe3e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2019 09:17:11.5039 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9HtwEeAj7/eJ6UOW+GP3QG4/6qtpaYavhxTvkdvgpUTivpX/eE5TLEhMx7nrKz7vNwgrJvUi6bOAnnGWa9ekj+TtFEsz+qmNyLeZkVEENS4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3480 Cc: Rasmus Villemoes , "NXP i.MX U-Boot Team" , Marek Vasut Subject: [U-Boot] [PATCH 3/4] arm: mxs: be more careful when enabling gpmi_clk X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 585c53baf6..183aa40b6d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -103,8 +103,11 @@ int arch_cpu_init(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* Set GPMI clock to ref_xtal / 1 */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) + ; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + CLKCTRL_GPMI_DIV_MASK, 1); udelay(1000); From patchwork Thu Sep 12 09:17:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 1161462 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 12 Sep 2019 09:17:12 +0000 Received: from AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b]) by AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM ([fe80::f0d2:3945:47d4:747b%3]) with mapi id 15.20.2241.018; Thu, 12 Sep 2019 09:17:12 +0000 From: Rasmus Villemoes To: "u-boot@lists.denx.de" Thread-Topic: [PATCH 4/4] arm: mxs: implement mxs_set_gpmiclk Thread-Index: AQHVaUrcC2N7MqONFkWiJjVuNo8mzQ== Date: Thu, 12 Sep 2019 09:17:12 +0000 Message-ID: <20190912091656.14301-5-rasmus.villemoes@prevas.dk> References: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> In-Reply-To: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0202CA0019.eurprd02.prod.outlook.com (2603:10a6:3:8c::29) To AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:131::7) x-mailer: git-send-email 2.20.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasmus.Villemoes@prevas.se; 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DIR:OUT; SFP:1102; SCL:1; SRVR:AM7PR10MB3160; H:AM7PR10MB3478.EURPRD10.PROD.OUTLOOK.COM; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: OtZenVZI1F6eoUpfXlDueATK6qt9DlKcRF8zTB7uoN7ranTBTuWm9/HEa1L2GJ+rCRQ6b+Ry9GEzib+++RY9kgGu8EBM4olX9pZxIe5MR8noc+Ssjb/Eod7cC2eFsDFyUkRTvtOW7FYIH8ufzfjtusR2f/qjaA68+uT/Ri/+2wnh3DL/y9KyF5VzARWr2huL/+zxz8nB24+qkdJ4oL0rdIPMxBlCVTCKXdxTRugL7kiuWY2bG21pej5ViMFPKakSJLaEB29t+N74cKOkfbCg+cicsN8sKHmncDiXtiCVwudKDRVCyBO93Br5YzO+wGrMzGDetn9KFJUdT/szg06mmu7ygwHMTBfoxYIAch5cqI/hdzGe4hY+qQ3/4l+eaAGrOWlPF8AerXIQbzvNVshJUo+MypKbNdKaz8hD5XglGiw= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 07121024-9ec6-4760-2cd1-08d73761feba X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2019 09:17:12.3585 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: U+f/uvuGeB5z79YA1hqvKyK9VItYsUUK8PJ/cSEscjZmSTyGZTcxMXNo4HP5FBB9jBW24ktbByIOGD7EsN5UnTkRPDv+dg9kNgr5oRV6CtE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3160 Cc: Rasmus Villemoes , "NXP i.MX U-Boot Team" , Marek Vasut Subject: [U-Boot] [PATCH 4/4] arm: mxs: implement mxs_set_gpmiclk X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This allows a board file to set the gpmiclk to something other than the default 24 MHz based on ref_xtal. I don't have an mx23-based board, but I believe there's a bug in the current mxs_get_gpmiclk: According to the data sheet, the gpmiclk can be derived from ref_io, not ref_cpu. Since other clocks are also derived from ref_io, it seems most sensible to require the board file to set that appropriately first, then derive the divider from its current setting. For mx28 boards, OTOH, there's a separate ref_gpmi only used for clk_gpmi. For simplicity, if !xtal, simply enable that at its maximum frequency. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/clock.c | 41 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mxs/clock.h | 1 + 2 files changed, 42 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 43d044d917..d247da56fe 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -138,6 +138,47 @@ static uint32_t mxs_get_gpmiclk(void) return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } +void mxs_set_gpmiclk(uint32_t freq, int xtal) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t clk, div; + + if (xtal) { + clk = XTAL_FREQ_KHZ; + } else { +#if defined(CONFIG_MX23) + clk = mxs_get_ioclk(MXC_IOCLK0); +#elif defined(CONFIG_MX28) + /* enable ref_gpmi at 480 MHz. */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_GPMI]); + writeb(CLKCTRL_FRAC_CLKGATE | PLL_FREQ_COEF, + &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_GPMI]); + clk = PLL_FREQ_KHZ; +#endif + } + if (freq > clk) + return; + div = clk / freq; + if (div > CLKCTRL_GPMI_DIV_MASK) + div = CLKCTRL_GPMI_DIV_MASK; + + clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) + ; + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_DIV_MASK, div); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_BUSY) + ; + + if (xtal) + writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, &clkctrl_regs->hw_clkctrl_clkseq_set); + else + writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + /* * Set IO clock frequency, in kHz */ diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h index ee56d10fec..0a6625eb90 100644 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ b/arch/arm/include/asm/arch-mxs/clock.h @@ -44,6 +44,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk); void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); +void mxs_set_gpmiclk(uint32_t freq, int xtal); void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);