From patchwork Tue Aug 20 21:12:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1150364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Ck6H1xGFz9s4Y for ; Wed, 21 Aug 2019 07:13:11 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46Ck6H122GzDr7Q for ; Wed, 21 Aug 2019 07:13:11 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46Ck684zf2zDr6q for ; Wed, 21 Aug 2019 07:13:03 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7KLC6CK073041 for ; Tue, 20 Aug 2019 17:13:00 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ugpem5e7m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 20 Aug 2019 17:13:00 -0400 Received: from m0098410.ppops.net (m0098410.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.27/8.16.0.27) with SMTP id x7KLCxjG075022 for ; Tue, 20 Aug 2019 17:12:59 -0400 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ugpem5e6y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2019 17:12:59 -0400 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id x7KLAd57016944; Tue, 20 Aug 2019 21:12:58 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma02wdc.us.ibm.com with ESMTP id 2ugqwu84jy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2019 21:12:58 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7KLCvLJ14221598 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 20 Aug 2019 21:12:57 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7F1D6136051; Tue, 20 Aug 2019 21:12:57 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 691FD13604F; Tue, 20 Aug 2019 21:12:57 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 20 Aug 2019 21:12:57 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id D67704602F0; Tue, 20 Aug 2019 16:12:55 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Tue, 20 Aug 2019 16:12:55 -0500 Message-Id: <1566335575-23232-1-git-send-email-arbab@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-20_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908200192 Subject: [Skiboot] [PATCH] npu3: Delay enablement of DL parity checking X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently, we turn on TX and PRI parity checking of the DL during NPU initialization, while RX parity checking is not enabled until after link training. This behavior was prescribed for npu2, but on npu3 systems the logic has changed such that we're getting early parity error checkstops. To fix, only set the TX and PRI enable bits after training, consistent with RX. Signed-off-by: Reza Arbab --- hw/npu3-hw-procedures.c | 12 ++++++++---- hw/npu3-nvlink.c | 2 -- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/npu3-hw-procedures.c b/hw/npu3-hw-procedures.c index 54f4b3576880..86067a028d3e 100644 --- a/hw/npu3-hw-procedures.c +++ b/hw/npu3-hw-procedures.c @@ -557,9 +557,11 @@ static uint32_t reset_ntl(struct npu3_dev *dev) val = SETFIELD(NPU3_NTL_PRI_CFG_NDL, 0ull, dev->index); npu3_write(npu, NPU3_NTL_PRI_CFG(dev->index), val); - /* Disable RX parity checking */ + /* Disable parity checking */ val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index)); - val &= ~NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA; + val &= ~(NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA); npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val); if (dev->type == NPU3_DEV_TYPE_NVLINK) @@ -636,9 +638,11 @@ static uint32_t reset_ntl_finish(struct npu3_dev *dev) { if (npu3_dev_fence_get(dev) != NPU3_NTL_CQ_FENCE_STATUS_NONE) return NPU3_PROC_INPROGRESS; - /* Enable RX parity checking */ + /* Enable parity checking */ val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index)); - val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA; + val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | + NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA; npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val); if (dev->type == NPU3_DEV_TYPE_NVLINK) diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c index 35f68a84c1ea..6969b89b2488 100644 --- a/hw/npu3-nvlink.c +++ b/hw/npu3-nvlink.c @@ -928,8 +928,6 @@ static void npu3_dev_init_hw(struct npu3_dev *dev) reg = NPU3_NTL_MISC_CFG2(dev->index); val = npu3_read(npu, reg); val |= NPU3_NTL_MISC_CFG2_BRICK_ENABLE | - NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA | - NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA | NPU3_NTL_MISC_CFG2_RCV_CREDIT_OVERFLOW_ENA; npu3_write(npu, reg, val); }