From patchwork Tue Aug 20 14:53:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150232 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="qluk3iBQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYjG3MRvz9sQw for ; Wed, 21 Aug 2019 00:54:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727212AbfHTOyV (ORCPT ); Tue, 20 Aug 2019 10:54:21 -0400 Received: from vps.xff.cz ([195.181.215.36]:60028 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729155AbfHTOxr (ORCPT ); Tue, 20 Aug 2019 10:53:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312825; bh=pjJHOWO7nxttAsWYJkOKvdkuaULnN0PZZ0RAx5PpN9o=; h=From:To:Cc:Subject:Date:References:From; b=qluk3iBQwrjiEBjSIXnZAafxX6k9lhkgFCeddtDvIAl7JMO+Qt0ZDOCav+zNhQtUW 4i/wOMDdMxpBqkyqrB67GP86/7lpBKTY0FbsdQVpLRS/nayXCeyRz+0IjEubxfNo2q JljrlnPu7zifGmGGs1Y4aDWbZA/PkOP+uwRrjCRI= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/6] dt-bindings: net: sun8i-a83t-emac: Add phy-supply property Date: Tue, 20 Aug 2019 16:53:38 +0200 Message-Id: <20190820145343.29108-2-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman This is already supported by the driver, but is missing from the bindings. Signed-off-by: Ondrej Jirman Reviewed-by: Rob Herring --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 3fb0714e761e..304f244e9ab5 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -43,6 +43,10 @@ properties: Phandle to the device containing the EMAC or GMAC clock register + phy-supply: + description: + PHY regulator + required: - compatible - reg From patchwork Tue Aug 20 14:53:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150223 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="JQloAJ9J"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYhb0yRPz9sNC for ; Wed, 21 Aug 2019 00:53:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730098AbfHTOxt (ORCPT ); Tue, 20 Aug 2019 10:53:49 -0400 Received: from vps.xff.cz ([195.181.215.36]:60048 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729351AbfHTOxs (ORCPT ); Tue, 20 Aug 2019 10:53:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312825; bh=wIAxljKfYwADgH+42GDkJIwLygOIg7HG/xvcRvcY98U=; h=From:To:Cc:Subject:Date:References:From; b=JQloAJ9JgxomMDFTbsLxbkyZJgYGUbjBaehlsq8CDjjsR5kp8P2V0WYdgIg7+puj6 AFMc4kQ/MwZPB+37mMTvujOxThMU3fqh605btYUrm9Kj8JtaQRpcl2rhfqL4tJ35CM I13XbUfgxDkjIsR5LBRq5X2HaxW5C+MsAGAiCREI= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/6] dt-bindings: net: sun8i-a83t-emac: Add phy-io-supply property Date: Tue, 20 Aug 2019 16:53:39 +0200 Message-Id: <20190820145343.29108-3-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Some PHYs require separate power supply for I/O pins in some modes of operation. Add phy-io-supply property, to allow enabling this power supply. Signed-off-by: Ondrej Jirman --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 304f244e9ab5..782e202aa124 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -47,6 +47,10 @@ properties: description: PHY regulator + phy-io-supply: + description: + PHY I/O pins regulator + required: - compatible - reg From patchwork Tue Aug 20 14:53:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150229 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="YlHw2Dih"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYj26k77z9sPx for ; Wed, 21 Aug 2019 00:54:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730393AbfHTOxs (ORCPT ); Tue, 20 Aug 2019 10:53:48 -0400 Received: from vps.xff.cz ([195.181.215.36]:60066 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729918AbfHTOxr (ORCPT ); Tue, 20 Aug 2019 10:53:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312826; bh=BmUD9BF7ZWHwfIwmCa4uNboL8E51kehruNiRWEgChOs=; h=From:To:Cc:Subject:Date:References:From; b=YlHw2Dihm2NXzNp1zXkFKZN/lDdmrVAGr6ZDu+rY6O6dYeqmdgN0A83O/0NDFzmTa MwI3Lq5KMIkfmJzFuQPpfM1Q/zoE9oTxK8lsvn+/6iD+bOjPtAe8y5kVFdMvOwXQqw +2gulGYP98IVdqI8xiM7wtztu84yRSq4lyKyiv4s= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/6] net: stmmac: sun8i: Use devm_regulator_get for PHY regulator Date: Tue, 20 Aug 2019 16:53:40 +0200 Message-Id: <20190820145343.29108-4-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Use devm_regulator_get instead of devm_regulator_get_optional and rely on dummy supply. This avoids NULL checks before regulator_enable/disable calls. This path also improves error reporting, because we now report both use of dummy supply and error during registration with more detail, instead of generic info level message "No regulator found" that was reported previously on errors and lack of regulator property in DT. Finally, we'll be adding further optional regulators, and the overall code will be simpler. Signed-off-by: Ondrej Jirman --- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 23 ++++++++----------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 4083019c547a..3e951a11aec3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -528,12 +528,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) struct sunxi_priv_data *gmac = priv; int ret; - if (gmac->regulator) { - ret = regulator_enable(gmac->regulator); - if (ret) { - dev_err(&pdev->dev, "Fail to enable regulator\n"); - return ret; - } + ret = regulator_enable(gmac->regulator); + if (ret) { + dev_err(&pdev->dev, "Fail to enable regulator\n"); + return ret; } ret = clk_prepare_enable(gmac->tx_clk); @@ -992,8 +990,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) clk_disable_unprepare(gmac->tx_clk); - if (gmac->regulator) - regulator_disable(gmac->regulator); + regulator_disable(gmac->regulator); } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) @@ -1129,12 +1126,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } /* Optional regulator for PHY */ - gmac->regulator = devm_regulator_get_optional(dev, "phy"); + gmac->regulator = devm_regulator_get(dev, "phy"); if (IS_ERR(gmac->regulator)) { - if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) - return -EPROBE_DEFER; - dev_info(dev, "No regulator found\n"); - gmac->regulator = NULL; + ret = PTR_ERR(gmac->regulator); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get PHY regulator (%d)\n", ret); + return ret; } /* The "GMAC clock control" register might be located in the From patchwork Tue Aug 20 14:53:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150227 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="OUSQL0xW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYhz2L5xz9sPV for ; Wed, 21 Aug 2019 00:54:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730547AbfHTOyH (ORCPT ); Tue, 20 Aug 2019 10:54:07 -0400 Received: from vps.xff.cz ([195.181.215.36]:60092 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730088AbfHTOxs (ORCPT ); Tue, 20 Aug 2019 10:53:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312826; bh=fJp1/iHxqT8rIRrQhM5u30ZJqn3FLJCfRTqKNHdiDpk=; h=From:To:Cc:Subject:Date:References:From; b=OUSQL0xWoyyXiFXG3/LwHN+ZkRJ0/NRPLbNEZ28F4MzGzDOMyvlvwINEM5mFJYNBR be7A368YMVBuW/BTSfCfJpd3WPAJFNcr60QlNdWdrKPxhUsesiBpVmvMoqsy48u2/Q a46vrrjCQAzAMqZWEPxmeFnRIKmjGU0LoyfmSZ0s= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/6] net: stmmac: sun8i: Rename PHY regulator variable to regulator_phy Date: Tue, 20 Aug 2019 16:53:41 +0200 Message-Id: <20190820145343.29108-5-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman We'll be adding further optional regulators, and this makes it clearer what the regulator is for. Signed-off-by: Ondrej Jirman --- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 32 ++++++++++--------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 3e951a11aec3..e7df30d3cab1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -57,19 +57,21 @@ struct emac_variant { }; /* struct sunxi_priv_data - hold all sunxi private data - * @tx_clk: reference to MAC TX clock - * @ephy_clk: reference to the optional EPHY clock for the internal PHY - * @regulator: reference to the optional regulator - * @rst_ephy: reference to the optional EPHY reset for the internal PHY - * @variant: reference to the current board variant - * @regmap: regmap for using the syscon - * @internal_phy_powered: Does the internal PHY is enabled - * @mux_handle: Internal pointer used by mdio-mux lib + * @tx_clk: reference to MAC TX clock + * @ephy_clk: reference to the optional EPHY clock for + * the internal PHY + * @regulator_phy: reference to the optional regulator + * @rst_ephy: reference to the optional EPHY reset for + * the internal PHY + * @variant: reference to the current board variant + * @regmap: regmap for using the syscon + * @internal_phy_powered: Does the internal PHY is enabled + * @mux_handle: Internal pointer used by mdio-mux lib */ struct sunxi_priv_data { struct clk *tx_clk; struct clk *ephy_clk; - struct regulator *regulator; + struct regulator *regulator_phy; struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap_field *regmap_field; @@ -528,9 +530,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) struct sunxi_priv_data *gmac = priv; int ret; - ret = regulator_enable(gmac->regulator); + ret = regulator_enable(gmac->regulator_phy); if (ret) { - dev_err(&pdev->dev, "Fail to enable regulator\n"); + dev_err(&pdev->dev, "Fail to enable PHY regulator\n"); return ret; } @@ -990,7 +992,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) clk_disable_unprepare(gmac->tx_clk); - regulator_disable(gmac->regulator); + regulator_disable(gmac->regulator_phy); } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) @@ -1126,9 +1128,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } /* Optional regulator for PHY */ - gmac->regulator = devm_regulator_get(dev, "phy"); - if (IS_ERR(gmac->regulator)) { - ret = PTR_ERR(gmac->regulator); + gmac->regulator_phy = devm_regulator_get(dev, "phy"); + if (IS_ERR(gmac->regulator_phy)) { + ret = PTR_ERR(gmac->regulator_phy); if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to get PHY regulator (%d)\n", ret); return ret; From patchwork Tue Aug 20 14:53:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150226 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="XI5z9DBn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYht1CxWz9sPV for ; Wed, 21 Aug 2019 00:54:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730524AbfHTOyB (ORCPT ); Tue, 20 Aug 2019 10:54:01 -0400 Received: from vps.xff.cz ([195.181.215.36]:60114 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729888AbfHTOxt (ORCPT ); Tue, 20 Aug 2019 10:53:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312826; bh=4hhK28dgS8BmhfHSH/CC6uoVklNXHuscBoxMGcS+N/w=; h=From:To:Cc:Subject:Date:References:From; b=XI5z9DBnNdOUqFw25KNQyt9MWq35cijMPrMPxwWFujdoAioSTERrxgfz/4Bgv2BoY LnJJavS2Z5Ic3cP0TpH8b795HjbJ4uOUXZsAj60ug3CNw3S0q57v5h7TtLAQ7x87ID yLHJzWbAsNjcbG4da6MFfZ19DXmU85CokPZfpB3U= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/6] net: stmmac: sun8i: Add support for enabling a regulator for PHY I/O pins Date: Tue, 20 Aug 2019 16:53:42 +0200 Message-Id: <20190820145343.29108-6-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E. According to the phy datasheet, both regulators need to be enabled at the same time. Add support for the second optional regulator, "phy-io", to the glue driver. Signed-off-by: Ondrej Jirman --- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index e7df30d3cab1..e96337b7cd12 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -61,6 +61,8 @@ struct emac_variant { * @ephy_clk: reference to the optional EPHY clock for * the internal PHY * @regulator_phy: reference to the optional regulator + * @regulator_phy_io: reference to the optional regulator for + * PHY I/O pins * @rst_ephy: reference to the optional EPHY reset for * the internal PHY * @variant: reference to the current board variant @@ -72,6 +74,7 @@ struct sunxi_priv_data { struct clk *tx_clk; struct clk *ephy_clk; struct regulator *regulator_phy; + struct regulator *regulator_phy_io; struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap_field *regmap_field; @@ -530,21 +533,30 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) struct sunxi_priv_data *gmac = priv; int ret; + ret = regulator_enable(gmac->regulator_phy_io); + if (ret) { + dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n"); + return ret; + } + ret = regulator_enable(gmac->regulator_phy); if (ret) { dev_err(&pdev->dev, "Fail to enable PHY regulator\n"); - return ret; + goto err_disable_regulator_phy_io; } ret = clk_prepare_enable(gmac->tx_clk); if (ret) { - if (gmac->regulator) - regulator_disable(gmac->regulator); dev_err(&pdev->dev, "Could not enable AHB clock\n"); - return ret; + goto err_disable_regulator_phy; } return 0; +err_disable_regulator_phy: + regulator_disable(gmac->regulator_phy); +err_disable_regulator_phy_io: + regulator_disable(gmac->regulator_phy_io); + return ret; } static void sun8i_dwmac_core_init(struct mac_device_info *hw, @@ -993,6 +1005,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) clk_disable_unprepare(gmac->tx_clk); regulator_disable(gmac->regulator_phy); + regulator_disable(gmac->regulator_phy_io); } static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) @@ -1136,6 +1149,16 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) return ret; } + /* Optional regulator for PHY I/O pins */ + gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io"); + if (IS_ERR(gmac->regulator_phy_io)) { + ret = PTR_ERR(gmac->regulator_phy_io); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get PHY I/O regulator (%d)\n", + ret); + return ret; + } + /* The "GMAC clock control" register might be located in the * CCU address range (on the R40), or the system control address * range (on most other sun8i and later SoCs). From patchwork Tue Aug 20 14:53:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1150224 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="pr0wChX5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CYhd1DKDz9sNk for ; Wed, 21 Aug 2019 00:53:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730464AbfHTOxu (ORCPT ); Tue, 20 Aug 2019 10:53:50 -0400 Received: from vps.xff.cz ([195.181.215.36]:60112 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728283AbfHTOxt (ORCPT ); Tue, 20 Aug 2019 10:53:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1566312827; bh=/wCPaAVAhM9jkrpOgFjJQndvFQSZ3vor/dhJP6G9DqM=; h=From:To:Cc:Subject:Date:References:From; b=pr0wChX5ZN4OrzzMX3Txai82qwcOk2weMbp798hGCqayc02tBmkgal0EJDif4lKiO 0Z5ZyF08kJhi3AKPIG1VQOkAsPGnlq1Ffa9zqT3kRxYLJPaLRGt+jqjuSwbMnK0NXU NDc9zrMaKXcYD+Jlu6URuc8eMVTnKofwFD/p2/Bo= From: megous@megous.com To: "David S. Miller" , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin Cc: Ondrej Jirman , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/6] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Tue, 20 Aug 2019 16:53:43 +0200 Message-Id: <20190820145343.29108-7-megous@megous.com> In-Reply-To: <20190820145343.29108-1-megous@megous.com> References: <20190820145343.29108-1-megous@megous.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Ondrej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "phy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. The driver ensures the regulator enable ordering. The timing is set in DT via startup-delay-us. We also need to wait at least 30ms after power-up/reset, before accessing the PHY registers. All values of RX/TX delay were tested exhaustively and a middle one of the range of working values was chosen. Signed-off-by: Ondrej Jirman --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index eda9d5f640b9..18349e60b8c6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -15,6 +15,7 @@ aliases { serial0 = &uart0; + ethernet0 = &emac; }; chosen { @@ -56,6 +57,15 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; }; &cpu0 { @@ -74,6 +84,35 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-supply = <®_aldo2>; + phy-io-supply = <®_gmac_2v5>; + allwinner,rx-delay-ps = <1500>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; +}; + &hdmi { status = "okay"; }; @@ -136,6 +175,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; + regulator-enable-ramp-delay = <100000>; }; /* ALDO3 is shorted to CLDO1 */