From patchwork Tue Aug 20 11:13:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 1150045 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CTCp2WJhz9sBF for ; Tue, 20 Aug 2019 21:32:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729693AbfHTLcE (ORCPT ); Tue, 20 Aug 2019 07:32:04 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55446 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729428AbfHTLcE (ORCPT ); Tue, 20 Aug 2019 07:32:04 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1D0F81A0186; Tue, 20 Aug 2019 13:32:03 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CE7CC1A0040; Tue, 20 Aug 2019 13:31:57 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 5BBDA40314; Tue, 20 Aug 2019 19:31:51 +0800 (SGT) From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, fabio.estevam@nxp.com, linux-imx@nxp.com, kernel@pengutronix.de, Dong Aisheng , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH V4 01/11] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree Date: Tue, 20 Aug 2019 07:13:15 -0400 Message-Id: <1566299605-15641-2-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566299605-15641-1-git-send-email-aisheng.dong@nxp.com> References: <1566299605-15641-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There's a few limitations on the original one cell clock binding (#clock-cells = <1>) that we have to define some SW clock IDs for device tree to reference. This may cause troubles if we want to use common clock IDs for multi platforms support when the clock of those platforms are mostly the same. e.g. Current clock IDs name are defined with SS prefix. However the device may reside in different SS across CPUs, that means the SS prefix may not valid anymore for a new SoC. Furthermore, the device availability of those clocks may also vary a bit. For such situation, we want to eliminate the using of SW Clock IDs and change to use a more close to HW one instead. For SCU clocks usage, only two params required: Resource id + Clock Type. Both parameters are platform independent. So we could use two cells binding to pass those parameters, Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Acked-by: Shawn Guo Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- ChangeLog: v3->v4: * add some comments for various clock types v2->v3: * Changed to two cells binding and register all clocks in driver instead of parse from device tree. v1->v2: * changed to one cell binding inspired by arm,scpi.txt Documentation/devicetree/bindings/arm/arm,scpi.txt Resource ID is encoded in 'reg' property. Clock type is encoded in generic clock-indices property. Then we don't have to search all the DT nodes to fetch those two value to construct clocks which is relatively low efficiency. * Add required power-domain property as well. --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 12 ++++++----- include/dt-bindings/firmware/imx/rsrc.h | 23 ++++++++++++++++++++++ 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index a575e42..8cee5bf 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -89,7 +89,10 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" -- #clock-cells: Should be 1. Contains the Clock ID value. +- #clock-cells: Should be either + 2: Contains the Resource and Clock ID value. + or + 1: Contains the Clock ID value. (DEPRECATED) - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" @@ -184,7 +187,7 @@ firmware { clk: clk { compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; + #clock-cells = <2>; }; iomuxc { @@ -229,8 +232,7 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; }; diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 4e61f64..24c153d 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -547,4 +547,27 @@ #define IMX_SC_R_ATTESTATION 545 #define IMX_SC_R_LAST 546 +/* + * Defines for SC PM CLK + */ + +/* Normal device resource clock */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ + +/* Special clock types which do not belong to above normal clock types */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ + +/* Special clock types for CPU/PLL/BYPASS only */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + #endif /* __DT_BINDINGS_RSCRC_IMX_H */ From patchwork Tue Aug 20 11:13:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 1150046 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46CTCq5jhvz9sML for ; Tue, 20 Aug 2019 21:32:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729696AbfHTLcH (ORCPT ); Tue, 20 Aug 2019 07:32:07 -0400 Received: from inva020.nxp.com ([92.121.34.13]:55474 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729639AbfHTLcH (ORCPT ); Tue, 20 Aug 2019 07:32:07 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3FC7B1A0117; Tue, 20 Aug 2019 13:32:04 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E71C41A0275; Tue, 20 Aug 2019 13:31:58 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 74C8A40318; Tue, 20 Aug 2019 19:31:52 +0800 (SGT) From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, fabio.estevam@nxp.com, linux-imx@nxp.com, kernel@pengutronix.de, Dong Aisheng , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH V4 02/11] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree Date: Tue, 20 Aug 2019 07:13:16 -0400 Message-Id: <1566299605-15641-3-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566299605-15641-1-git-send-email-aisheng.dong@nxp.com> References: <1566299605-15641-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside in different subsystems across CPUs and also vary a bit on the availability. Same as SCU clock, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree and make us be able to write a fully generic lpcg clock driver. And we can also use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. Cc: Rob Herring Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng Acked-by: Shawn Guo Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- ChangeLog: v3->v4: * change bit-offset property to clock-indices * use constant macro to define clock indinces * drop hw-autogate property which is still not used by drivers v2->v3: * no changes v1->v2: * Update example * Add power domain property --- .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 36 ++++++++++++++++++---- include/dt-bindings/clock/imx8-lpcg.h | 14 +++++++++ 2 files changed, 44 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/imx8-lpcg.h diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa4..cad8fc4 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,6 +11,21 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- clock-indices: An integer array indicating the bit offset for each clock. + Refer to for the + supported LPCG clock indices. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock-indices property. +- power-domains: Should contain the power domain used by this clock. + +Legacy binding (DEPRECATED): - compatible: Should be one of: "fsl,imx8qxp-lpcg-adma", "fsl,imx8qxp-lpcg-conn", @@ -33,10 +48,19 @@ Examples: #include -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , + , + ; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; usdhc1: mmc@5b010000 { @@ -44,8 +68,8 @@ usdhc1: mmc@5b010000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, + <&sdhc0_lpcg IMX_LPCG_CLK_0>, + <&sdhc0_lpcg IMX_LPCG_CLK_5>; clock-names = "ipg", "per", "ahb"; }; diff --git a/include/dt-bindings/clock/imx8-lpcg.h b/include/dt-bindings/clock/imx8-lpcg.h new file mode 100644 index 0000000..df90aad --- /dev/null +++ b/include/dt-bindings/clock/imx8-lpcg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#define IMX_LPCG_CLK_0 0 +#define IMX_LPCG_CLK_1 4 +#define IMX_LPCG_CLK_2 8 +#define IMX_LPCG_CLK_3 12 +#define IMX_LPCG_CLK_4 16 +#define IMX_LPCG_CLK_5 20 +#define IMX_LPCG_CLK_6 24 +#define IMX_LPCG_CLK_7 28