From patchwork Tue Aug 6 15:08:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142839 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="BcgQMMcz"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 462ynN0SCsz9s3Z for ; Wed, 7 Aug 2019 01:13:11 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B5AC3C21E56; Tue, 6 Aug 2019 15:10:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 29810C21E47; Tue, 6 Aug 2019 15:09:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 40773C21E50; Tue, 6 Aug 2019 15:09:23 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id 4723FC21DA6 for ; Tue, 6 Aug 2019 15:09:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1565104144; bh=ZoVXYf8Tq4ja0IPFJz0BKuoDhw1DSLNmXMx5w32IXJc=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=BcgQMMcz9OgF8yLQJiGKbyFiMKsQewdcvOxPDXcth2dHiFaufewn2AjrmIiMRwwU5 /Gmc15+OS6wxr7yv2eBFfcpLi7wXn60UgGWR31gR0jlOTfw3Z+0ayS5+bVpzpo05BK Wh5VjZgK1yAMxq3E4dVOBVIDtqoh5kxNKzoySnGA= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.153.94]) by mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MTiTt-1hkwUM45lN-00U2az; Tue, 06 Aug 2019 17:09:04 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:45 +0200 Message-Id: <20190806150852.5527-2-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:t9F+d1a4mdTPtsQ+7nXFpeSsHFDnLE3KGB+O24Z+AxDY7Ox5dUK gILVjOd5iuHRcvWooSmli86AnS6FqiYtby78btrg/Zt7RuOq4rxKE/EwbMZJ3COUL5CRFeS 1+hfyB/lUQdX3wpRDpcLHPEQnLPvySO8rQ4hdWgxFqJ2GnxLNUhWu+vkmC38KdIewRJYYQg TAq3LkB5ybftTeLyzPapA== X-UI-Out-Filterresults: notjunk:1; V03:K0:lz9iMwYvMUA=:J1mhsHBLxiCMLrp3SnGVWy Av+ns6l1EDOAiHiLX+gcmaQ5ki9+evNsHlzPRVDFf99RkGWLYP75GNvFqoajULLlIe59yIcpz oecIiUfbHNzOYnM0SAUKEvA5FytEFf+AE+0JlaCqhp1z7DTm+0UPpR3GgLDOk9dQ5qAT+vi8Q LBrjiyuAXDVX/TCaan4ZhGypD+8U1rY3wcc4aefeWz6c3sTzp4mtqEuoE0IBSk5TFBFkzsVmF P53BYTTbdqoim3Nml+sWNpicPpTuVK3pu5olJMlugimRqgRL6M0GtCv+IY9exy5psIggwdRJF fl9O7FgGAOS2IfDZo4kpI/OoM3AQP1bLjpPuDsbL+VojSMlqpAU2HsN89D2ETfUajQ8ChGkqC vi8ndTwYAnkSgPsyBsNNbAGWprXmdHNpUZELU+uRgVfOkIq487vh9NB5qH8AdIEGaeBTzQvia Ot9/BvwxCLwuR3BoQOWie/QuQwIe/7LMoD+mrQ3ExdsLp5oXDd8HQpsDfYIbSztdtxmPWPqUT t/1Ft+o4cdYJV4AqEX2hFbG2qif7P+JQSwJOHGHtCqMHmkepNJ1O8A5+ns0M2alcGmcub44C4 JJfaEbUZkD+C4NxXMrw64solSIdJKetCGX5PILVj69rxdqzGEBFsLZ3l70zr4RZ6DgoL8IECa /gTVbnTxsodMWMJVzU23PhiJw/8RRGX3D/YYOqiwOSmw67gg8/yhNrxVc+rTNpcdDk5C3T2qu Si2gNm1bvqAeENrtPrIDvvqbX8XwL7wSQFrOChaIHFM+Zv0CUABwI89sSvdAtX4GW34l0NEcK GxfpWnzh8miLL09MVCyY3jlNw1asm6kJh80Gbbl8TjCLQqFs27KIoZjYSUi3M63O83C13g1b6 0ieJUWD24jCp+xsANuy/meeTr/J+8LnkPEV9tQsAN0R2HWkBwKg8iszaIKc791kUrOUDQF6ZA AnIBlKDlA3uMwU9moiBSqFbrwiGudTFeVK3A6O19golq1OOBJnjsapqFhUr5FaOvNMp+MCZ9i kF9mj8/dc2T4EJ46/Sb3jX92bMdPxejN1MYVPyP4aBtqqhvfIFCW/LAfniokjKTYYtCZ71I56 kPcBD5W7W+qT4UCvGib5HV4bhQL4sz6Duy85XPtoaleiieGnTrvR80U7A== Subject: [U-Boot] [PATCH v3 1/8] pci: mediatek: add PCIe controller support for MT7623 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe controller support for MT7623. This is adapted from the Linux version. changes since v2: - rename driver to "MediaTek PCIe Gen2 controller" - use clrsetbits_le32 instead of readl/writel Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- drivers/pci/Kconfig | 8 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_mediatek.c | 279 ++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/pci/pcie_mediatek.c -- 2.17.1 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 3fe38f7315..88df9001ee 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -145,4 +145,12 @@ config PCI_MVEBU Say Y here if you want to enable PCIe controller support on Armada XP/38x SoCs. +config PCIE_MEDIATEK + bool "MediaTek PCIe Gen2 controller" + depends on DM_PCI + depends on ARCH_MEDIATEK + help + Say Y here if you want to enable Gen2 PCIe controller, + which could be found on MT7623 SoC family. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index b5ebd50c85..7093d63918 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ pcie_layerscape_gen4_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o +obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c new file mode 100644 index 0000000000..a0dcb258b0 --- /dev/null +++ b/drivers/pci/pcie_mediatek.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek PCIe host controller driver. + * + * Copyright (c) 2017-2019 MediaTek Inc. + * Author: Ryder Lee + * Honghui Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCIe shared registers */ +#define PCIE_SYS_CFG 0x00 +#define PCIE_INT_ENABLE 0x0c +#define PCIE_CFG_ADDR 0x20 +#define PCIE_CFG_DATA 0x24 + +/* PCIe per port registers */ +#define PCIE_BAR0_SETUP 0x10 +#define PCIE_CLASS 0x34 +#define PCIE_LINK_STATUS 0x50 + +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_PERST(x) BIT(1 + (x)) +#define PCIE_PORT_LINKUP BIT(0) +#define PCIE_BAR_MAP_MAX GENMASK(31, 16) + +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ + ((((regn) >> 8) & GENMASK(3, 0)) << 24)) +#define PCIE_CONF_ADDR(regn, bdf) \ + (PCIE_CONF_REG(regn) | (bdf)) + +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) + +#define PCIE_FC_CREDIT 0x73c +#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) +#define PCIE_FC_CREDIT_VAL(x) ((x) << 16) + +struct mtk_pcie_port { + void __iomem *base; + struct list_head list; + struct mtk_pcie *pcie; + struct reset_ctl reset; + struct clk sys_ck; + struct phy phy; + u32 slot; +}; + +struct mtk_pcie { + void __iomem *base; + struct clk free_ck; + struct list_head ports; +}; + +static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct mtk_pcie *pcie = dev_get_priv(udev); + + writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); + + return 0; +} + +static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, mtk_pcie_config_address, + bdf, offset, valuep, size); +} + +static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, mtk_pcie_config_address, + bdf, offset, value, size); +} + +static const struct dm_pci_ops mtk_pcie_ops = { + .read_config = mtk_pcie_read_config, + .write_config = mtk_pcie_write_config, +}; + +static void mtk_pcie_port_free(struct mtk_pcie_port *port) +{ + list_del(&port->list); + free(port); +} + +static int mtk_pcie_startup_port(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie = port->pcie; + u32 slot = PCI_DEV(port->slot << 11); + u32 val; + int err; + + /* assert port PERST_N */ + setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot)); + /* de-assert port PERST_N */ + clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot)); + + /* 100ms timeout value should be enough for Gen1/2 training */ + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, + !!(val & PCIE_PORT_LINKUP), 100000); + if (err) + return -ETIMEDOUT; + + /* disable interrupt */ + clrbits_le32(pcie->base + PCIE_INT_ENABLE, + PCIE_PORT_INT_EN(port->slot)); + + /* map to all DDR region. We need to set it before cfg operation. */ + writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + port->base + PCIE_BAR0_SETUP); + + /* configure class code and revision ID */ + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); + + /* configure FC credit */ + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK, + PCIE_FC_CREDIT_VAL(0x806c)); + + /* configure RC FTS number to 250 when it leaves L0s */ + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK, + PCIE_FTS_NUM_L0(0x50)); + + return 0; +} + +static void mtk_pcie_enable_port(struct mtk_pcie_port *port) +{ + int err; + + err = clk_enable(&port->sys_ck); + if (err) + goto exit; + + err = reset_assert(&port->reset); + if (err) + goto exit; + + err = reset_deassert(&port->reset); + if (err) + goto exit; + + err = generic_phy_init(&port->phy); + if (err) + goto exit; + + err = generic_phy_power_on(&port->phy); + if (err) + goto exit; + + if (!mtk_pcie_startup_port(port)) + return; + + pr_err("Port%d link down\n", port->slot); +exit: + mtk_pcie_port_free(port); +} + +static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port; + char name[10]; + int err; + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + snprintf(name, sizeof(name), "port%d", slot); + port->base = dev_remap_addr_name(dev, name); + if (!port->base) + return -ENOENT; + + snprintf(name, sizeof(name), "sys_ck%d", slot); + err = clk_get_by_name(dev, name, &port->sys_ck); + if (err) + return err; + + err = reset_get_by_index(dev, slot, &port->reset); + if (err) + return err; + + err = generic_phy_get_by_index(dev, slot, &port->phy); + if (err) + return err; + + port->slot = slot; + port->pcie = pcie; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int mtk_pcie_probe(struct udevice *dev) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port, *tmp; + ofnode subnode; + int err; + + INIT_LIST_HEAD(&pcie->ports); + + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + + err = clk_get_by_name(dev, "free_ck", &pcie->free_ck); + if (err) + return err; + + /* enable top level clock */ + err = clk_enable(&pcie->free_ck); + if (err) + return err; + + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; + u32 slot = 0; + + if (!ofnode_is_available(subnode)) + continue; + + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr); + if (err) + return err; + + slot = PCI_DEV(addr.phys_hi); + + err = mtk_pcie_parse_port(dev, slot); + if (err) + return err; + } + + /* enable each port, and then check link status */ + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + mtk_pcie_enable_port(port); + + return 0; +} + +static const struct udevice_id mtk_pcie_ids[] = { + { .compatible = "mediatek,mt7623-pcie", }, + { } +}; + +U_BOOT_DRIVER(pcie_mediatek) = { + .name = "pcie_mediatek", + .id = UCLASS_PCI, + .of_match = mtk_pcie_ids, + .ops = &mtk_pcie_ops, + .probe = mtk_pcie_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pcie), +}; From patchwork Tue Aug 6 15:08:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142834 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="YrmvoODX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 462ymH6XSpz9s3Z for ; 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Tue, 06 Aug 2019 17:09:05 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:46 +0200 Message-Id: <20190806150852.5527-3-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:0YWLzwpfX4gRAchHxeGfUEsRj6/VtNStuBFTKKST7rMYjihr+Xl xoIdn/vdnieJ4X/3uNhQv1dVq6JQTTe8K8JHJMZuQlqgTNrSNnrHKw/BR9klTP+BDGmFOiC +UhY/UNqG/KcefoiZU31oD7urFLc7NNd+tKg54XhBLyow2N9L5vSy7NgLPfYAgaXbcqB6/R qHXAPyv8mQovO31rSVhAQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:2jcqb00M2HI=:LHbPVVzGyk9T3gA9GHbBnY mTAjgLhFmGNAKF7GNXPe2VA4YirsTxDp7JiXXWxDyjTNjZQCWZ20TYT9c4z9NlVAp0k0TwPbr 7cna8uiDbtALf/hVzyPkaEC2r2mmPP63oVANfbbfevsKRu/q5GDRBjJxTc5ZGcu9Zb7oaNEOn p+e2bP6Gw/vBkCfhHQwGQPqGkfi4p2Vjq5qfF1kkpsQUXN+Q1BBJP9ZpUNuhkyr+5VWaQE8Od k7ZmnYlvnHLw4xLXblejtkbupczDoLVRiDEiITLtJqVoDotD5mU+6imjWN5elhu628rdHfUrw /ezN7h1xMtZiNagD7FNm8khqgm48IOaEgRcfzrgJTTegZ1Zw6+EtCAMSM5p2YoeyIYILwbepi UoCQO622PqYTquGHwVZnGnSFyL2sg05slm1UMUlQQgjpGnamK3ieadNMEqiyGOJSZCpb5ehdQ t5pea48y7AyYoh75GuccHuzOXNSIqHjoIW/Ckz4XdZK6S7I2MZXRLJaqn8R7P2HPouriwRkXJ IJ6v/WITlFxDMDAGmaBH5bz5asOivuv2Zvy3P4z5LRmBH+Boh9QQNnrA9Qz8NTQd3A3pagTxp 1pXTbSh7y7EoL8l2HmbsBfxOleu2dE9KpFXLYe/XvY0nhXTkpu/WZjnBjUKzMlKUZY07n2KXx uEB/3oD40fUHnXQVws+IoUx8uch3qhoooPqIGMvMzwwo/PM0RxAd5xpH1fPJrcGtmzvKFnWTQ PXtRe3/4BVrzd+Swx9UAYIJwRzipbvzpZuUgLwdI9MdlNCPnkdl1JW4jRJ/ODdfZr9/4SdED9 WT4s6Ciafn0DS+mYecPLqIqfeLKGUXNnMhs9hozQmlT0d5riiZ4DcKPoTXs0CdBrUxapbPnI0 fE6DF6uiM2ef0V23uWhN+dkOytOTf8iajVuzNnisf0ln+bqTgUD9zC25EEYASx3O9XGvUAisb G6uU5Ayv4Xqd0dBaH+B3hN2YdgMlTLiI7Ey+HQDjbXA3RCDWEoOVcW/RLBCyN+seTK89TZfOw zBCcL6RvJR3chIbeZxRZHYc8ElYctZ4lrbQMAK7RFpIULZysm2GxaHJ8wMs9ClMSe3G4I5C1w FoMhppj8FOjrTlv0M9W5Ryv/FCnbwyGqbb5BqgRRE3UbEVJF3zplYgwHg== Subject: [U-Boot] [PATCH v3 2/8] phy: mediatek: add MediaTek T-PHY support for PCIe X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. changes since v2: - use clrsetbits_le32 instead of readl/writel - change SSC-delta Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- drivers/phy/Kconfig | 11 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-mtk-tphy.c | 362 +++++++++++++++++++++++++++++++++++++ 3 files changed, 374 insertions(+) create mode 100644 drivers/phy/phy-mtk-tphy.c -- 2.17.1 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 957efb3984..2099dd9547 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -190,4 +190,15 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config PHY_MTK_TPHY + bool "MediaTek T-PHY Driver" + depends on PHY + depends on ARCH_MEDIATEK + help + MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and + SATA, and meanwhile supports two version T-PHY which have + different banks layout, the T-PHY with shared banks between + multi-ports is first version, otherwise is second veriosn, + so you can easily distinguish them by banks layout. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 90646ca55b..15b4d58a2d 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c new file mode 100644 index 0000000000..3701481256 --- /dev/null +++ b/drivers/phy/phy-mtk-tphy.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 - 2019 MediaTek Inc. + * Author: Chunfeng Yun + * Ryder Lee + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* version V1 sub-banks offset base address */ +/* banks shared by multiple phys */ +#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ +#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V1_U3PHYD 0x000 +#define SSUSB_SIFSLV_V1_U3PHYA 0x200 + +#define U3P_U3_CHIP_GPIO_CTLD 0x0c +#define P3C_REG_IP_SW_RST BIT(31) +#define P3C_MCU_BUS_CK_GATE_EN BIT(30) +#define P3C_FORCE_IP_SW_RST BIT(29) + +#define U3P_U3_CHIP_GPIO_CTLE 0x10 +#define P3C_RG_SWRST_U3_PHYD BIT(25) +#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) + +#define U3P_U3_PHYA_REG0 0x000 +#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) +#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) + +#define U3P_U3_PHYA_REG1 0x004 +#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) +#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) + +#define U3P_U3_PHYA_DA_REG0 0x100 +#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) +#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) +#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) +#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) +#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) + +#define U3P_U3_PHYA_DA_REG4 0x108 +#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) +#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) +#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) + +#define U3P_U3_PHYA_DA_REG5 0x10c +#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) +#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) +#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) +#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) + +#define U3P_U3_PHYA_DA_REG6 0x110 +#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG7 0x114 +#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG20 0x13c +#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) +#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG25 0x148 +#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) +#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) + +#define U3P_U3_PHYD_RXDET1 0x128 +#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) +#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) + +#define U3P_U3_PHYD_RXDET2 0x12c +#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) +#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) + +struct u3phy_banks { + void __iomem *spllc; + void __iomem *chip; + void __iomem *phyd; /* include u3phyd_bank2 */ + void __iomem *phya; /* include u3phya_da */ +}; + +struct mtk_phy_instance { + void __iomem *port_base; + const struct device_node *np; + + struct u3phy_banks u3_banks; + + /* reference clock of anolog phy */ + struct clk ref_clk; + u32 index; + u8 type; +}; + +struct mtk_tphy { + void __iomem *sif_base; + struct mtk_phy_instance **phys; + int nphys; +}; + +static void pcie_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, + P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, + P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | + P3A_RG_XTAL_EXT_PE2H_VAL(0x2)); + + /* ref clk drive */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, + P3A_RG_CLKDRV_AMP_VAL(0x4)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, + P3A_RG_CLKDRV_OFF_VAL(0x1)); + + /* SSC delta -5000ppm */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20, + P3A_RG_PLL_DELTA1_PE2H, + P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25, + P3A_RG_PLL_DELTA_PE2H, + P3A_RG_PLL_DELTA_PE2H_VAL(0x36)); + + /* change pll BW 0.6M */ + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5, + P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, + P3A_RG_PLL_BR_PE2H_VAL(0x1) | + P3A_RG_PLL_IC_PE2H_VAL(0x1)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4, + P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, + P3A_RG_PLL_BC_PE2H_VAL(0x3)); + + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6, + P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2)); + clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7, + P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa)); + + /* Tx Detect Rx Timing: 10us -> 5us */ + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, + P3D_RG_RXDET_STB2_SET, + P3D_RG_RXDET_STB2_SET_VAL(0x10)); + clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, + P3D_RG_RXDET_STB2_SET_P3, + P3D_RG_RXDET_STB2_SET_P3_VAL(0x10)); + + /* wait for PCIe subsys register to active */ + udelay(3000); +} + +static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *bank = &instance->u3_banks; + + clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); + clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); +} + +static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + +{ + struct u3phy_banks *bank = &instance->u3_banks; + + setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); + setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); +} + +static void phy_v1_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_PCIE: + u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; + u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; + break; + default: + return; + } +} + +static int mtk_phy_init(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + int ret; + + /* we may use a fixed-clock here */ + ret = clk_enable(&instance->ref_clk); + if (ret && ret != -ENOSYS) + return ret; + + switch (instance->type) { + case PHY_TYPE_PCIE: + pcie_phy_instance_init(tphy, instance); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_phy_power_on(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_on(tphy, instance); + + return 0; +} + +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + pcie_phy_instance_power_off(tphy, instance); + + return 0; +} + +static int mtk_phy_exit(struct phy *phy) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = tphy->phys[phy->id]; + + clk_disable(&instance->ref_clk); + + return 0; +} + +static int mtk_phy_xlate(struct phy *phy, + struct ofnode_phandle_args *args) +{ + struct mtk_tphy *tphy = dev_get_priv(phy->dev); + struct mtk_phy_instance *instance = NULL; + const struct device_node *phy_np = ofnode_to_np(args->node); + u32 index; + + if (!phy_np) { + dev_err(phy->dev, "null pointer phy node\n"); + return -EINVAL; + } + + if (args->args_count < 1) { + dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); + return -EINVAL; + } + + for (index = 0; index < tphy->nphys; index++) + if (phy_np == tphy->phys[index]->np) { + instance = tphy->phys[index]; + break; + } + + if (!instance) { + dev_err(phy->dev, "failed to find appropriate phy\n"); + return -EINVAL; + } + + phy->id = index; + instance->type = args->args[1]; + if (!(instance->type == PHY_TYPE_USB2 || + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SATA)) { + dev_err(phy->dev, "unsupported device type\n"); + return -EINVAL; + } + + phy_v1_banks_init(tphy, instance); + + return 0; +} + +static const struct phy_ops mtk_tphy_ops = { + .init = mtk_phy_init, + .exit = mtk_phy_exit, + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, + .of_xlate = mtk_phy_xlate, +}; + +static int mtk_tphy_probe(struct udevice *dev) +{ + struct mtk_tphy *tphy = dev_get_priv(dev); + ofnode subnode; + int index = 0; + + dev_for_each_subnode(subnode, dev) + tphy->nphys++; + + tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), + GFP_KERNEL); + if (!tphy->phys) + return -ENOMEM; + + tphy->sif_base = dev_read_addr_ptr(dev); + if (!tphy->sif_base) + return -ENOENT; + + dev_for_each_subnode(subnode, dev) { + struct mtk_phy_instance *instance; + fdt_addr_t addr; + int err; + + instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); + if (!instance) + return -ENOMEM; + + addr = ofnode_get_addr(subnode); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + instance->port_base = map_sysmem(addr, 0); + instance->index = index; + instance->np = ofnode_to_np(subnode); + tphy->phys[index] = instance; + index++; + + err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk); + if (err) + return err; + } + + return 0; +} + +static const struct udevice_id mtk_tphy_id_table[] = { + { .compatible = "mediatek,generic-tphy-v1", }, + { } +}; + +U_BOOT_DRIVER(mtk_tphy) = { + .name = "mtk-tphy", + .id = UCLASS_PHY, + .of_match = mtk_tphy_id_table, + .ops = &mtk_tphy_ops, + .probe = mtk_tphy_probe, + .priv_auto_alloc_size = sizeof(struct mtk_tphy), +}; From patchwork Tue Aug 6 15:08:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142832 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id 83E5FC21DD7 for ; Tue, 6 Aug 2019 15:09:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1565104146; bh=4H55wuVxhFeffQx4Lo0XQLMAUa8cUCRE87ISCRPqyOM=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=bUQ1TXoCpz7X5Jv49Zx6cjJ4Gl/MIn+d7/0svZxIXtkG6xyufF71IZiWDUOzeQP6o 9BqyCCsSPel9TgZzLdfv7ikRO5aDKatnN0RTrkGL4zn6yDO6MJ4oKgSY4jurG3tzkW h7izJGQut7mkkD13n5Jqa1+fOH9c4whSgnHksH6o= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.153.94]) by mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MfHEJ-1iWWtN08lP-00golX; Tue, 06 Aug 2019 17:09:06 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:47 +0200 Message-Id: <20190806150852.5527-4-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:lPTAAx1rw4ADrj4ME7iMuHwFMx/rhzuUKEs15P17zJvhINM0k6g nHu303/ztDGP93uw0XUvgLI1urZFVeKqT37B3RQ87DJ7jEu5+u2zbwyJVPHjTAhtM7eT5Kw 31I8wazkYjoW6wSJkgQjbt1QWkMI5x5okTzM0Mi+Znnuv+URBfwUxEpr0b+xGwDadThR6SJ VfS6PVUdXNeKlrYUoSaaA== X-UI-Out-Filterresults: notjunk:1; V03:K0:hsM176S0LqY=:ncmZMHRJg8rQc8WZSnWmf+ zvVWV8ca7DbUTw7PXXbfjt+uh/kjmM12yvnr3lBC9JIaqHuHr8A1DByOlWu8sndvX/JGQ2hJ9 DEUt1Y6cZIQYOXT7vlIExrPGtN6/F0mH38djKLtaLws5anzT2ClGGzXKt46VA4IWNskgFQ+WE E1V8fdNjI1u5LqSqhNOqdXTKoqGRrKM3CS6x4Nwq7Mn09wDqHWr4t74FKejfwB/F1j55oXr1G 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controller for MT7623 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe and its PHY nodes for MT7623. changes since v2: none Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 128 +++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 29 +++++ 2 files changed, 157 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bf..3a868ea2ee 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "skeleton.dtsi" @@ -255,6 +256,133 @@ #reset-cells = <1>; }; + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index 51628bb639..b0c86219b6 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -172,6 +172,13 @@ }; }; + pcie_default: pcie-default { + mux { + function = "pcie"; + groups = "pcie0_0_perst", "pcie1_0_perst"; + }; + }; + uart0_pins_a: uart0-default { mux { function = "uart"; @@ -201,6 +208,28 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From patchwork Tue Aug 6 15:08:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142840 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="awXno6Y1"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 462ynj0SXqz9s3Z for ; Wed, 7 Aug 2019 01:13:28 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 96CA5C21E15; Tue, 6 Aug 2019 15:10:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DECABC21E56; Tue, 6 Aug 2019 15:09:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9CBA7C21E68; Tue, 6 Aug 2019 15:09:30 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lists.denx.de (Postfix) with ESMTPS id 95431C21E62 for ; Tue, 6 Aug 2019 15:09:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1565104147; bh=2FDwBVXKdUanYnCgbJG/6TDT6kT7M3tSaUvAwQNb3Ys=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=awXno6Y1Jtf2z9Elc5AI2az9Qoirq2rtuaqbYSL1Cbe5znNKsCQyO7wdH3lL3Gvcm YFWrexMGml54qHmbs4Z/T8zHHKtzt4torrxL4m2tHeHDcrbr3DxGz1oXKaozEE6sfb y+3N6HVfQz7oL7MUNuJOunLYPFaCBQbU7G8oQRUc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.153.94]) by mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MBlxM-1i2kKU40U8-00C6Em; Tue, 06 Aug 2019 17:09:07 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:48 +0200 Message-Id: <20190806150852.5527-5-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 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2Na2sYIdHeRrpnPRmnVm5S8cLBxWe2nJJ8VF9MUQr7Tbumf44lOgIlRwJgIhHexh7tHq1Nfab 7kJ6WiPhrJeYk4sAjotgv9KDFUBd87jwu6RuKal7qgkuafGod38OKJYrA1W7kuECWHy2y7Opd xq2+sLcEyFpgxNcacg/qHtw9WkwdRyapkD6fV3POCIWbRuLQJd/USrLZWw7/Itcvv149SuBDr Y/NaeMQi2X7HsNX1C9HDxASgG+43dBRIFfnKYJBIUkT4jZztLGEDgfDC02Rxz0r4V8AUQ8bcL ceky8c/OhU4gvYSDygCFNXDwekMmSq1cGoi2eh491ZoMCbr8/vW0N4mfjsrGzExcTnzGOixV7 vxNAqbioo0adwJwNDo3Cc1w9v8hQFlhYcfBkBUjErH9LBGPF7dq8lQcjaWtyYT1JQTockJDOO V8JbpqgI6Xr+E10CoMA8x55FAOtiERRBKgfiYxplyLQPNRABmhDk+zKmyu1NbmeQYTRDbDCq5 sJliQi3e4ib+uUmEWWxVE5sGKLVHBbU2C0pS/Dz6RlHhXyXQfVf3aMyDV1gQx10tSgPMMUuAt vbjMBdfFCFzLus6hs+ovtaRlJUtRsImPw2hXUSmc4NrpJFAAgkAwhPQzA== Subject: [U-Boot] [PATCH v3 4/8] arm: dts: split mtk-reset.h into per-chip header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This follows the linux header rules to avoid conflict bitfields. changes since v2: none Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7623.dtsi | 2 +- arch/arm/dts/mt7629.dtsi | 2 +- .../reset/{mtk-reset.h => mt7623-reset.h} | 4 +-- include/dt-bindings/reset/mt7629-reset.h | 36 +++++++++++++++++++ 4 files changed, 39 insertions(+), 5 deletions(-) rename include/dt-bindings/reset/{mtk-reset.h => mt7623-reset.h} (88%) create mode 100644 include/dt-bindings/reset/mt7629-reset.h -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 3a868ea2ee..1135b1e1ae 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index ecbd29d7ae..3c9eab9770 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mt7623-reset.h similarity index 88% rename from include/dt-bindings/reset/mtk-reset.h rename to include/dt-bindings/reset/mt7623-reset.h index 78fcdab009..a859a5b26a 100644 --- a/include/dt-bindings/reset/mtk-reset.h +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -6,11 +6,9 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* ETHSYS */ +/* ETHSYS resets */ #define ETHSYS_PPE_RST 31 -#define ETHSYS_EPHY_RST 24 #define ETHSYS_GMAC_RST 23 -#define ETHSYS_ESW_RST 16 #define ETHSYS_FE_RST 6 #define ETHSYS_MCM_RST 2 #define ETHSYS_SYS_RST 0 diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 0000000000..8f1634f7a6 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe Subsystem resets */ +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ From patchwork Tue Aug 6 15:08:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142835 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mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MxDkm-1iEinD3x04-00xevY; Tue, 06 Aug 2019 17:09:08 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:49 +0200 Message-Id: <20190806150852.5527-6-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:PK36jK/Ooscsq6XUVrKZII3BLRPZFjH5aDWG6mfclE5HXCcOyqg CDvfXNegXw0LQGQEP695G0BkdJD32JIlpvJ70RSJp73iw2enxSZCvhY5Xg3NlRVQ/oTLvVq 7Bf1flHzt90zKeIEXnb3PLoK5fXebWw6k8asT9IbgCoOBsRtlgTTkilyQ7+00GreUmyYz98 KpCnAwvfw8j83qpkUhd1w== X-UI-Out-Filterresults: notjunk:1; V03:K0:GHIpwfTTZ0Q=:R9gF8BT1iGCj8wAkKePZrg 9tqB9te0+U6PUVNx4c5sNP4R4nGW1erODX1qBJ3KXM3mMGvoCmPnFUAgc9wZISUhez2BxgKkn Q7OVI3OPSLR29d60P+81Rc6gBf28QZjiYFhxkIrvTxx3A4xzh+u/LFTrTXDTS2FiMSx5Ys60p dkcLw0mIQbMap5kJLNmw/MSXUrPStUJRtq9OLs7BcrJF7byNlqobttzFoxC7yXS+KufPNfGE7 2wlini5LCkPv9HIkDm66XclYhDxvF0D7AuXeR3pPB5eKHbTEjlOcYs/ObvIdxOWZvr0c3yjT+ MvzPVsUO7sQL3sYPNji48YipePhjt+f5ErNsiFTof6QpF8y1wwNf4RX/R6sKccY7lBXxPSL3E DL+bl7IZVePu5Ni+2BfuO+AT538uCGK3zUNm6LSzWMGAiAyDGfl55tJ07XKsuZcFXoXvxY6nv CziD71qW3qtw9rmomeiv2cczl/c1proEjw6nJMubwFm+TKd3X0panCy0p8LGVzfGwxCiqBza1 GXROgb49BCX1mH9Sxn/TOUxyCBRVOeqsHe+HCTQQP4Gyd83jBNSVX4T9EhXOm9uq7evwNMUvf dGBgOGO1bHkVJ8/i7/S90OZy9Yk8FS8T/a8A5oQT1zrTdkXntkEZhLycG7uxIyO80XyglbRPN 2bf1OfcxHHE7Aq4gUgf+Ot1KHAit8zgijnhUnaJjMzteDWL6JhhDedqaFqdNJxh8S776D+g7C 4A+TPUZmqolVzPCWEijlU2rMDhiEt7qjRUt3BviLSYDLEzpczL/uYG+z9hkMaIJR6SKMvFDqh IHrHRkhSkcRYhWaNS/RejLMdW1jr9MQm8TN1OYl0sidtS9yUoQv7z3pHdnYnQHKHY/N9CGe+a wHMAY9/cwLylVAh5ytlA9nchWnhwkjeUlYibVASEKZQE1T4m1qM9Zz6KIL+5xsn0MEkgJmAFx HkIHDOTUlW94YalwJ8/Dq23hdu7c2LRw9AP6Pr85Cm+F9Ugr+fCmMpfJDY8GDnQ99Bs6po9zC amA9Fvk3dabK0atcBCER+r6pCRbkJsxSzVtE5HfbsYTNdmJULqVtxnW93U/6rSifBPgLgi8XZ UW9bZdbx//8umQgm7shLaF3RdTkHd2FuKpujWz+Bq/7LPaMCysFwRwMxg== Subject: [U-Boot] [PATCH v3 5/8] dt-bindings: pcie: add a document for MT7623 PCIe controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds a document for MT7623 PCIe controller. changes since v2: dt-bindings added with v3 Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- .../pci/mediatek-pcie.txt | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 doc/device-tree-bindings/pci/mediatek-pcie.txt -- 2.17.1 diff --git a/doc/device-tree-bindings/pci/mediatek-pcie.txt b/doc/device-tree-bindings/pci/mediatek-pcie.txt new file mode 100644 index 0000000000..2f9f549b7a --- /dev/null +++ b/doc/device-tree-bindings/pci/mediatek-pcie.txt @@ -0,0 +1,122 @@ +MediaTek Gen2 PCIe controller + +Required properties: +- compatible: Should contain one of the following strings: + "mediatek,mt7623-pcie" +- device_type: Must be "pci" +- reg: Base addresses and lengths of the PCIe subsys and root ports. +- reg-names: Names of the above areas to use during resource lookup. +- #address-cells: Address representation for root ports (must be 3) +- #size-cells: Size representation for root ports (must be 2) +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: + Mandatory entries: + - sys_ckN :transaction layer and data link layer clock + Required entries for MT7623: + - free_ck :for reference clock of PCIe subsys + where N starting from 0 to one less than the number of root ports. +- phys: List of PHY specifiers (used by generic PHY framework). +- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the + number of PHYs as specified in *phys* property. +- power-domains: A phandle and power domain specifier pair to the power domain + which is responsible for collapsing and restoring power to the peripheral. +- bus-range: Range of bus numbers associated with this controller. +- ranges: Ranges for the PCI memory and I/O regions. + +Required properties for MT7623: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + +In addition, the device tree node must have sub-nodes describing each +PCIe port interface, having the following mandatory properties: + +Required properties: +- device_type: Must be "pci" +- reg: Only the first four bytes are used to refer to the correct bus number + and device number. +- #address-cells: Must be 3 +- #size-cells: Must be 2 +- #interrupt-cells: Must be 1 +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- ranges: Sub-ranges distributed from the PCIe controller node. An empty + property is sufficient. + +Examples for MT7623: + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */ + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + }; From patchwork Tue Aug 6 15:08:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142833 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="ahNYcMl9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 462ylm70m3z9sMr for ; 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Tue, 06 Aug 2019 17:09:08 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:50 +0200 Message-Id: <20190806150852.5527-7-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:ThxfnUDQrPo5l6OrqLe5QGo3zbI5QeboUj6IebeuzQrSCYw9SqW hYxza4rczOCPomRMM3io8u/d596UivvXfybW+OYa506i4g8HdTbW9WT+/XPsGFM/sfF1R6c 7FzRDxGtVndQRe7GZz9v7XuwuUN4hq/GIIhzOSPZI8pSmqLSXf40tmEx30YS0Hlif8M/j8c ZZY2YR+6CDUQrYGnb5F1w== X-UI-Out-Filterresults: notjunk:1; V03:K0:W8jfFoWM6zY=:awm7O9Bw+7x642mqMcY4iA yA0KdZxuZUtGn8j3PlzDvrSOuFcbOtP3DuTVOtAmlWm4sZGJoRWclMtm/Ojjib/63QM8sFaok m3khDn7eHJ1Xzb8yqraGrYPF/y/eQDjzwqS3Nc//FVoi1KQv/VMvA6MBcQ24qugxLUVeGaU+4 1jaKnFJqO1NMs4D0Fs4NDQHWUpdYBo45UBfp+WtC+0UKrCFgIiL3adnDg1fZL8QqrW4+Du/fT suWOUJOMNaGD/HYEG6ghXTtFnZiqctfBYNjEAtuJFep30FAEY62ANuy1OOWWhNmnmFujrfH3I ZlCM7hG4PE2bSai0EuzbP+D0vs2L/pjiwfsqCehG5ZL2KvNQQFJ5eyS5tl3dIlSH2Gt8hNHEh QMTPhkglhQLTqN3krmeKEGCAUlP4qgUl7eOXO6NaFQ5r+npZH6z8GuPGJ3LSuT1pLfMpLyKDp NnddkzFXdi4C5HyiApu346LEoKvy4QHyK8qtMnLg2dzyUouOAZFiS9wFfrtGZzD6E6GMHI0u1 PGVfe0ed9fo92Lw7pedIfXR+iOvVhdjt6FCMlG/R1fqbnBQ6YxboRnUN+KyL6wn6xoz8K01OG WVPfrk6JtB/VenyO42d83yf/Z7b9hBGF3tgntEZBJ4vpNu+296oEcV1gvFBKPXyuY7Ym84J/a YL51aNhqkfLUkXRq1SF8FKlElElmZMi3T/zGCzpdeDCpdpWdZ7h/dMy6xh5OmLvbIuFsoTKNn 9RDXV9b3u6YSM6YKtvYGwXywXEcg/xU3JW1Z6WWimyGE88Bm/S0qFj/JEq1EwR8mhDRbs4q7+ ZumT2Cs5JrsrZ2KOXofg4mseEj09E3cDA5auNz9WwmsHsZEPdff574NXnLOUnsTewJKv7dwuC AZ21PUkYQosTHzIXIxaARXZ7PS1ykF10q/ww78gW++MewOQx6G3DA9MbGD7ki9w2yR8wldYv8 BGAyAvC/JduQMITQxU3w5QeEGueBTaX6s9F7G1vSEmofz+HdobjcX5AGYqI9vJp9ydhzIxJvn u++oKJLJDjx0KAu3VrIaBlaHRZ2YEjVtY17nYFR+kMTUflNz8q9fZcfZ0Z0oSutZeREb1O7J6 l9A+BqCnxjR1OAelh0S9qcZMcpzi1juswCQ9Uchz5ubWSUs0t6QOcYlcQ== Subject: [U-Boot] [PATCH v3 6/8] dt-bindings: phy: add a document for MediaTek tphy X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds a document for tphy which supports physical layer functionality for a number of controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. changes since v2: dt-bindings added with v3 Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt -- 2.17.1 diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt new file mode 100644 index 0000000000..037c5a4be5 --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt @@ -0,0 +1,86 @@ +MediaTek T-PHY binding +-------------------------- + +T-phy controller supports physical layer functionality for a number of +controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. + +Required properties (controller (parent) node): + - compatible : should be one of + "mediatek,generic-tphy-v1" + - clocks : (deprecated, use port's clocks instead) a list of phandle + + clock-specifier pairs, one for each entry in clock-names + - clock-names : (deprecated, use port's one instead) must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : must contain + "ref": 48M reference clock for HighSpeed analog phy; and 26M + reference clock for SuperSpeed analog phy, sometimes is + 24M, 25M or 27M, depended on platform. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + - PHY_TYPE_PCIE + - PHY_TYPE_SATA + +Example: + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; + ... +}; From patchwork Tue Aug 6 15:08:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142830 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="Cjn00tMB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 462yjD14qyz9sMr for ; Wed, 7 Aug 2019 01:09:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id EEF9CC21E1B; Tue, 6 Aug 2019 15:09:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7D06AC21DC1; Tue, 6 Aug 2019 15:09:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D48FFC21DC1; Tue, 6 Aug 2019 15:09:21 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id A1863C21DB6 for ; Tue, 6 Aug 2019 15:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1565104150; bh=GguadG3w2IJcokSfhlh7cc4rIYGiCkxs+RvAnR8PBXI=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=Cjn00tMBF3FdGS8Ai+pbzyQdkiGz5lA+fYi7g/b83POEw+2Z5AevSz3df5NHwP4fq IMpETUK9/eCbH6/d5kfCdfzFRag0jLvGQSe2aq8E52YictdGwZawPs3F7IQyqYElIo IfpbVs4xo0ooQG4gggN/gVaTjwHuARZ7drKqik/I= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.153.94]) by mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N2V4J-1iKYUk3HiR-013ve3; Tue, 06 Aug 2019 17:09:09 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:51 +0200 Message-Id: <20190806150852.5527-8-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:9792Kusw18sbU7ivF1h8lMaNB8hm678VNen8qp6CIJM7aRZBx5j tHM2V3rsYJfR625szm1pfGxmnmDDx0OOW8AHxd5b6eRSU7EG20tFcKbGQLtHweaq4D4v9Zn EhycD1WrpxCxh5zvopzTrNReA0Vkb6IC+w9uKhAQ4ptZRWSeE+YXXqyqN7vSxoKKWcwCddi KNiyS5rAOzPeAvMhz1yyA== X-UI-Out-Filterresults: notjunk:1; V03:K0:DKvzzCNdudA=:IrGk9jrpQOBB5UX1fzUqfV /DSzYuvyyO/iSus7Ge/sG7q/xRZSHUBL5zTO+9uvxv+R1BX3RD66vg4PEB2iWjbDSDnUQNDyZ RwYSLOhQdyXU6BARFkJbuUZ1abDtERvDNewZLoP7owqsHK1eBLyXL6IYlaW5NdV7y5bZ7OKBg hhzoHWVpVIZ++lqqMAQ3ePmJQoToscuMmPC0oQeSZ/sNjpLSKtRsV4jBGVcjHaDRCegazAT/s IVBE1XUV5MdFc8WKsx44YCMSGbQ/5EzUjh0IN4KHdqELE1gWCJQQADAgtPGCkxsOxlD5ZI9iw 1vQR6YTE7i6WLiGkAZ0LNJEMCKV42qQKUIDIqCZzQ0Y0OQo7mf4yhxkdi7EeoF1XgAIv+dtWm x5Xi5t11FWOQW4BFd6i70b+/X5Jnl55vk5canxVf9qG+EcfdyISkBy/c7B45FaX3C+ew9CkSw 8HrY013jSG0cR2F/K6ESNX9Bcjdj9naRmYZC2lV0pWKHqXQKzajxeR+33GhVTSKUsoAW2bre0 lqytXcvJjRndyxw7edoEcCu1lZvE+qKMnzCoruq2CfAIG43wQ7adfcsl0nCD2Roh9ihACmXAQ vnOEdzT1ImXgc50iCqEYizF6JlWSiiAvKFVOFLg6uLF0FT8oTCb7YRdGdjUpZ1Qxfl4LCcWy/ CjaggitX1CIXURfAGz33190d7RNhJLbCq90VEjYvsvIf5b3m1fTrvnLbLM8UIKgvUrPGaZg+n GTES7LJZG+Tv6Yhm8JpAxIXbvL3dl4444HqJDgm4uq6IyeVYP2cczKFa7AsK1ok6k23CdlflM Djbg3okm0oWNapO2bnY89lIm7kKVQbXXHyDAunU5x6uPCjxV9bwbqL/g+DFmfXiEySqKIUqtw s3xMzGFgo7/V673ENTMpkCLhef3nZtMMm6H4/PKuIqLOXRWsF0L4M5lt6n/bACkeWNwsm5I/l LeUDbzPrmFptz5/81gxaVJwUIOBkKVQryK6EsNrYqd9MCTRonYBOmqVROi98Qx5v9rzYmWVJQ 44rPlHpK3xT/OV3ABBUYNXb+2c5kMmHa0nx+mYMrXce8JiH+J++KAzMYOWT2Yc/bXYz7G9hk8 I2T9wCYjyoeYLDwD7sVxbq+e8usv7kwcoSwyHDLZxh+WE3RQPEQ4Wqw5A== Subject: [U-Boot] [PATCH v3 7/8] ahci-pci: ASM1061 report wrong class, but support AHCI. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko changes since v2: none Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci-pci.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 1ca439d3fa..11ec98b56f 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, + { PCI_DEVICE(0x1b21, 0x0611) }, {}, }; From patchwork Tue Aug 6 15:08:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1142831 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 6 Aug 2019 15:09:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E2EDBC21DA6; Tue, 6 Aug 2019 15:09:21 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id 69DA3C21DA6 for ; Tue, 6 Aug 2019 15:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1565104150; bh=7bUzHwqMVLepKto/4yYbHA2y6a2MB1auAf2MQlDP3cA=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=VQ9HAIPe7yagwfBDuoWOSsvsa+3THBdsyVvU4I/A9aY5yvxFlRy459NnWbXI67fCz WND3zjGo4m+mOvd6Knl5SYJehkarVxlN7akIpvEd12PRugZy+hwAG3+SP0PvFMsmwy 0YKH8aygl6zKhiuCYnp+6PbFVVdNjSDYjRVQA7sA= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.153.94]) by mail.gmx.com (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MoO24-1if5Li34W0-00okye; Tue, 06 Aug 2019 17:09:10 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:52 +0200 Message-Id: <20190806150852.5527-9-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:wre2rZ4lhVmEzPZptc7J3b7jUDApWe4bYaV+egtyPfKRfAVX1cS GuwXpUNPo6bjbm8OL70bn3D4hFMPfjqyqL5JW65X0ohKc/q4pBEuKDUivnIjIoRHaOX/bqg f0Pvheb2xPaAUV4VFe6xAV7vr0C5K80KZblHypokHFffXtR5LnY4gGzkBGUefTb92k5O5yj BNXWyKxAeRQNKpIoFl+4A== X-UI-Out-Filterresults: notjunk:1; V03:K0:+cAmSK81ito=:o/bwFThX3aaiHUe3gnC0Ec A2sVvMAMxjK0gaD5Slz31bx7NIF35J/5zvAs24tv8zMGTUlSJyg2vUnY+VEL163rvC5QbK8Sw F9CMcCfanGKTrKmifv0sUix98f+GgWLJFIf86bJBUcOGJZQgBvJjeRjb7Sv4LmzgIx7GBw7gY gjleWFR6ugK0jpI+uww2rAz2twiI7Rve2BsA7qqOElmDgO9Sxx7zAf7M8RN+sWGDbwbXUUd3z epeSiFxyfPX6/GhGvx4UExjDjs7KkkKtNO2z6f791QWtVGuxJf8Y94z7G3bhqvQwpSf3pAWPQ 75519WwUCM3C3HPCrGN5jeI8wOaBhppYx9fEiVuoqEIVepXE+BMsmJLoPWgMdaLvbLLtrgnec Lr3x0cdQp21lrMmCv+6WPYigeH2gTy+V0HrNzz9fplxs0ckFKObKdc469MkCGtmgBRonsdmZb Y+3iHe9luEcMCvcy39G905H3+Fv+9gdfkCMP9T4oCvs3zNn1hUNfwZrxCC2RJruu4o/54uawx +Aj6Tx9GGh3YFsDnmHrbUjvWTzJPuqUsfOClGbJTUE/B5VxBIw8zSq+mrWCPAdLSTPYtNeU4b iL6sKjKXPE3HDnP1vWSA3VW/cDEZWoQ5fRW8EGQeUElgT7NcO8g13ATHX0Mx29UQnhvqYpCyc Z1oToiiKXK8QENnesrrEVCWmqzbX6le6//D1NSevS7ydr+l+M2j2PTosnNCRCvDxfJprroX+V D4NA320zfRt7UQQ8uz9EP2ZHRbfSb8mozMMWjNV6bX/i+tIb36jA2lTdnC+yd/ls7Z/2/EbpD cqA5FljHti4TmiEq1eSWmtuJYvMZwG5vn53xFxVYwn+q4v4mrdt3imD9vKtu3QjyF9jBjAt25 rM9HlfwsZ2oho5h/UQKJkAritQmARk8IqTzAL8A8Cm9UXGtqswqBDewKNczEzjuJ78CnBU7nd 9scUYhAty5j1Y0nxdEdIlm3B6FmYGvqJC8hkqvKvfiBnPy3mWyywN+eSzdu97IL4XO8LeDzs1 pxIOaALsjr0DJEygiZ5c+irhznz4WDhm1zcsXZBeoKYuWwblRB2eWotoxzOjWotVWwTs4dlwZ tXkphWA+ePydauA5Pacq3bkL8LESCWjMQqvTHYZLmEasjG7BknJmBEW0Q== Subject: [U-Boot] [PATCH v3 8/8] ata: ahci: Don't forget to clear upper address regs. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Oleksandr Rybalko In 32bits mode upper bits need to be set to 0, otherwise controller will try to DMA into not existing memory and stops with error. changes since v2: none Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Oleksandr Rybalko --- drivers/ata/ahci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index e3135bb75f..716f9c1c7e 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -593,10 +593,15 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, - port_mmio + PORT_LST_ADDR); + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI); +#endif writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); +#ifndef CONFIG_PHYS_64BIT + writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI); +#endif #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio);