From patchwork Thu Jul 25 10:41:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1136821 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ZLmJvOdi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45vTL56J6Kz9s00 for ; Thu, 25 Jul 2019 20:42:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387982AbfGYKl7 (ORCPT ); Thu, 25 Jul 2019 06:41:59 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:42672 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387873AbfGYKl7 (ORCPT ); Thu, 25 Jul 2019 06:41:59 -0400 Received: by mail-lj1-f194.google.com with SMTP id t28so47516931lje.9 for ; Thu, 25 Jul 2019 03:41:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HkR5c7pg+yPuBi2NQ0G3gtI0G9f3RBJtD6x7Jmgjehc=; b=ZLmJvOdiUYFEJm4i4mbuyrMY2o6mclBz5DhrFLFaBKoorOt5B6ZiY2psz1JuTtwaFZ 5kxpMa2cjNwA8rRi8P5H/op90KLl/aDbsFG69P0RY+FnENSQN1Xf2mdDymrZHkplNyRg uK5KguUErED95Wmi4b3Ok+n5HeY/cSZEjPm+UMupvLcjVs7VJadZySzkdqoJDY9DOSKA LFk5vCN6UOEQ/tjgt/gFuQQdJMvCeLuja7fHjZm8GWioL6xwxmQMzVvNPskaG9fzT/0B 85I2zrX1TaqE8klv4DrcceVpijzG3OYw4sIEM5/16ijVOGfz0sZjxMakrjAc++87GIQP EuGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HkR5c7pg+yPuBi2NQ0G3gtI0G9f3RBJtD6x7Jmgjehc=; b=jwGLvNV8akelEndRAExCukBM3ZL9orJ38SaV0TRqzU5CMW0WUitC4GpAXyqZU00d/b QE0V+MQ4l/DxunEe7BJTGUsx3svl+yxbIMjo/1y+kbKgUlsmemIG1lNE6HCvfQ3fwtAv i11Cr1ZAwK+dlRcz1sdQATJMMNV6N6bwwzT/jZtv+Q/r2ItFcnjicDMWm9mM+l/IyPpu dAxf1wUdAhIpURt06MKPmQaJUxtTD5ybMvzRrVSiQahBt1IXftfXIkTegZz238NyIMKA oYuhivdpDW07sWW8Th+i98BLXOfiHL5ESnjIRSEUR+0a87sAEoMBCXsTYjDMyqfi364B ma6g== X-Gm-Message-State: APjAAAWIq06DqAorsCtUiMNupS3LZOXmTezSIGpT5ElbLjRiyV5glb0H yn+9Y1NFLgw5gul2BnBxgcMwXw== X-Google-Smtp-Source: APXvYqwWe8bFQsIaLQgq5TXU6wZZZIiHgi37mSb0dZrMRLQLsCPq/8RZD9nqMFtCDrB3yErElssZRw== X-Received: by 2002:a2e:534a:: with SMTP id t10mr8150715ljd.109.1564051317095; Thu, 25 Jul 2019 03:41:57 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-44-230.bbcust.telenor.se. [83.226.44.230]) by smtp.gmail.com with ESMTPSA id b6sm8268306lfa.54.2019.07.25.03.41.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:41:56 -0700 (PDT) From: Niklas Cassel To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Andy Gross , Ilia Lin Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Sricharan R , Niklas Cassel , Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Date: Thu, 25 Jul 2019 12:41:30 +0200 Message-Id: <20190725104144.22924-3-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sricharan R The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R [niklas.cassel@linaro.org: split dt-binding into a separate patch and do not rename the compatible string.] Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin Reviewed-by: Rob Herring --- Changes since V1: -Picked up tags. .../opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%) diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt similarity index 98% rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c2127b96805a..198441e80ba8 100644 --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -1,13 +1,13 @@ -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 -that have KRYO processors, the CPU ferequencies subset and voltage value -of each OPP varies based on the silicon variant in use. +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, +the CPU frequencies subset and voltage value of each OPP varies based on +the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. From patchwork Thu Jul 25 10:41:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1136823 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Jc4jwUeo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45vTLd0csMz9sND for ; Thu, 25 Jul 2019 20:42:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389134AbfGYKmb (ORCPT ); Thu, 25 Jul 2019 06:42:31 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:33666 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388358AbfGYKmQ (ORCPT ); Thu, 25 Jul 2019 06:42:16 -0400 Received: by mail-lf1-f67.google.com with SMTP id x3so34273602lfc.0 for ; Thu, 25 Jul 2019 03:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TpKb4VV72yRVAf7yb1K/qNrZx1PQ6/zj42Sv4qoKxfU=; b=Jc4jwUeowngvAFR3LX2W1/kDI10qMd8LfPEIU08SrKmCtk+2usu+5+U+uUsonvMdyi cloQgHAyJZVlsXpVdBZvjk9ZeuUYkRE8n0e2pVvhrRB83DD5BrCzaUd3FIPfmHXim6kz yn2RQb79KNc7N5jzwU5TXU0dYc4jyJE4/XavMRXVd0Gbv4SXQl4mrktwT3WO8YJpvAKT GaF6Mcxr8VgsTSmfXOGqry85Dpr5T+Jh3SdhOJXwgpv54sG/qwS/cQhWD9vGgUcCyseq Ce2qxwTBZr8Yc8PvgL2IeXitU3Ui86u9ckAhqpfMe54fyPKnBNGg8TsF48oiYEBAcZWh Q8HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TpKb4VV72yRVAf7yb1K/qNrZx1PQ6/zj42Sv4qoKxfU=; b=q+L+kl8wdgchRZW55NlweJ5UbZdmEGRjmXhP4uvXJNyQLqg2omuyDnLZrRyf+R6p7J z2P5Elb/GtbSljpS76ZEc6V6/63IAREFkSgH0Oj5zuFPs1OvTm2IQEeuukf+UwSksX/4 Crx8eG2aSuDzqSsiN51bPoW0crc9FHuueiq5OcsSYLGqRT2QcYXEumNStov7PDDGvL7b 2PTAckv8KEu0Crx8NpV/yR9U2YuRj6LEKoIneXn18QV5BZJrt0pY2Vo9q63/VUdY1uDb 2ADJI9I5VbgLegzoqaQLK7y9A+FVZ9OuE4lUb9AGzN6DjFMfVWq4tb/HzMLo05voJO4y /Bug== X-Gm-Message-State: APjAAAWqW42hhLSJFVTiM654NRo+oB60O0UsxwfY45rU64Bh+DK7+Mhn 7Gsw5PQNUmVO2VimrLWzgUQ0yw== X-Google-Smtp-Source: APXvYqzOQ29X1ibchVTw5wCsSyM2R71I8q3iJTM9pm9V+nxEdnazgwjsrGUrRAu07gExbAbgydMpOA== X-Received: by 2002:ac2:5336:: with SMTP id f22mr39514270lfh.180.1564051334342; Thu, 25 Jul 2019 03:42:14 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-44-230.bbcust.telenor.se. [83.226.44.230]) by smtp.gmail.com with ESMTPSA id h1sm7451290lfj.21.2019.07.25.03.42.13 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:13 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Date: Thu, 25 Jul 2019 12:41:32 +0200 Message-Id: <20190725104144.22924-5-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Not all Qualcomm platforms need to care about the speedbin efuse, nor the value blown into the speedbin efuse. Therefore, make the nvmem-cells and opp-supported-hw properties optional. Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin Reviewed-by: Rob Herring --- Changes since V1: -Picked up tags. Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index 198441e80ba8..c5ea8b90e35d 100644 --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -20,6 +20,10 @@ In 'cpus' nodes: In 'operating-points-v2' table: - compatible: Should be - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. + +Optional properties: +-------------------- +In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage From patchwork Thu Jul 25 10:41:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1136824 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="csVHpCLA"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45vTLf4yFmz9sDQ for ; Thu, 25 Jul 2019 20:42:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389550AbfGYKme (ORCPT ); Thu, 25 Jul 2019 06:42:34 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:40807 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388358AbfGYKmd (ORCPT ); Thu, 25 Jul 2019 06:42:33 -0400 Received: by mail-lj1-f193.google.com with SMTP id m8so13919287lji.7 for ; Thu, 25 Jul 2019 03:42:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3GNalLtrTqW5s+BFJJMMFnFc3aO7NBuze3htvzi00W0=; b=csVHpCLA5Pk3GDmRAP9m1Ka9VSO+6NzJzZMzdJorVAdGE3hwGdBVrpgI7dNWlxKh5+ gp2Jnqh1jTzEYKZ2cuAO9fNIysTEyilMqkvBZ7Es/sttkX11gsh4pt17Bq5V5ikLgcPZ 07h4eMoW6kC1kiC/JWESg9NsKm9MS3EWFMcEDENNY4HnbldWLbbmD0U/xtAOPCaINXcP lwBrhC+T1897IM+jvEohanzwbCHC/BLsmnRGCTZu41aQcIjP8uexSxkp2ORA4s2orTNl d0Daf2zOXzOT9wsg3Vk0S0kKM6dwDOTBAegabpvisdrX3oBYB2iPQrG5HICwn2pT+Pt0 Cx0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3GNalLtrTqW5s+BFJJMMFnFc3aO7NBuze3htvzi00W0=; b=uj98CmQH2BtKtRULhQ4GRIZw13K+8NS0pliFGDMjyfbJjPow8no+IeZTjaJJoTr6Ac 1geOVNifwOIXkvAVhUl8vNI7rLsz5Bn9AezI7053pIv/yWUTDGjnt/bEjKr2E0jNc3j1 v6N2DHV0NzeWaMjZ6nxmezmp9fwoN3NXNPMI477SjsZkl2YYsiQXFD9rCNh3YdfiI3ze UMu98Qea74J6kPbCJ6sTPa8Y098hIHDoGLI9vlKAGkQ6CCaxGUARxm7/ADmPyITT3t/J mf4xCThKqh6CdA3nSxJrBOdulgnaknsgWcZDji3pBwanJ43ywtwrgG0/lP6jgdNpEZz0 wggg== X-Gm-Message-State: APjAAAUptDoEKTWTNJYMQps42RNs9wpTKsO2zBDhuDx6fDe0q0AUWxbh oMUU1XMcyMSnHdlY+1pRAm1oKQ== X-Google-Smtp-Source: APXvYqyHvHkP+AWTOyXPquqI0XYCPqA34oDmByMsp0Rt6v7ofJrmE5t2XRx7pQR6v1/c4yYOJ+NJ7g== X-Received: by 2002:a2e:8849:: with SMTP id z9mr6421628ljj.203.1564051351281; Thu, 25 Jul 2019 03:42:31 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-44-230.bbcust.telenor.se. [83.226.44.230]) by smtp.gmail.com with ESMTPSA id k124sm7461299lfd.60.2019.07.25.03.42.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:30 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Date: Thu, 25 Jul 2019 12:41:34 +0200 Message-Id: <20190725104144.22924-7-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Qualcomm SoCs have support for Core Power Reduction (CPR). On these platforms, we need to attach to the power domain provider providing the performance states, so that the leaky device (the CPU) can configure the performance states (which represent different CPU clock frequencies). Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring --- .../bindings/opp/qcom-nvmem-cpufreq.txt | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c5ea8b90e35d..e19a95318e98 100644 --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -23,6 +23,15 @@ In 'operating-points-v2' table: Optional properties: -------------------- +In 'cpus' nodes: +- power-domains: A phandle pointing to the PM domain specifier which provides + the performance states available for active state management. + Please refer to the power-domains bindings + Documentation/devicetree/bindings/power/power_domain.txt + and also examples below. +- power-domain-names: Should be + - 'cpr' for qcs404. + In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the @@ -682,3 +691,105 @@ soc { }; }; }; + +Example 2: +--------- + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cpr_opp1>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cpr_opp2>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + .... + }; + cpr_opp2: opp2 { + opp-level = <2>; + .... + }; + cpr_opp3: opp3 { + opp-level = <3>; + .... + }; + }; + +.... + +soc { +.... + cprpd: cpr@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + .... + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + .... + }; +}; From patchwork Thu Jul 25 10:41:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1136825 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.226.44.230]) by smtp.gmail.com with ESMTPSA id e62sm9035045ljf.82.2019.07.25.03.42.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:48 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Date: Thu, 25 Jul 2019 12:41:37 +0200 Message-Id: <20190725104144.22924-10-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add qcom-opp bindings with properties needed for Core Power Reduction (CPR). CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and msm8996. CPR was first introduced in msm8974. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../devicetree/bindings/opp/qcom-opp.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..f204685d029c --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,19 @@ +Qualcomm OPP bindings to describe OPP nodes + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom-level" + +* OPP Node + +Optional properties: +- qcom,opp-fuse-level: A positive value representing the fuse corner/level + associated with this OPP node. Sometimes several corners/levels shares + a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, + min uV, and max uV. From patchwork Thu Jul 25 10:41:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1136826 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Xv5Uave8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45vTM75Zm4z9s00 for ; Thu, 25 Jul 2019 20:42:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388076AbfGYKmw (ORCPT ); Thu, 25 Jul 2019 06:42:52 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:42870 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390192AbfGYKmw (ORCPT ); Thu, 25 Jul 2019 06:42:52 -0400 Received: by mail-lf1-f65.google.com with SMTP id s19so34180754lfb.9 for ; Thu, 25 Jul 2019 03:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PiCimMlECSuSC3p9Tf5td0HbmG6WHhr2fDE9h4PjuDA=; b=Xv5Uave8H9XOovGyb9lcztVjF/oEuGRQL39AqbpSjmmMF1wvJBODiMZmkcnTeu/k8a pxHzHAZ3239Hd0lJMDZpcfiAqOfDJ/Wjf2gE1ofurYy2pdiXvbj9KsJ57+YYTI3sePlI P5wdKFlTC/cl5tcRYytLbXqsqPDeDN2L9cjvecjzfPUmtY83QV+mr3RzTcTw0z1C33a9 rwwTTeKEowqggXwgN3JhfmCAYOjvlQbFnEVyfetO8aUdRb4nt6yKTF++g5mkGgICKxhR LlFhtcTOCR8LALTa8y35zlkFa9pW2NLdT1vvOb81UsWaXuyoQbjHmLpW5aV7jK9lOxUv BLhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PiCimMlECSuSC3p9Tf5td0HbmG6WHhr2fDE9h4PjuDA=; b=bR4z3gRWGH3eT4wJ8Hs6Jg9+KG9MmYsC3vnaYW7xXOqDepAKTTeaThW+DlLktBnhNv m/GzC+YR2NGtukiuXoTa1CCAtChib5i/QUKY4MpU4W9+fNGUm5dCCorlwyuy5xy08MuA xrpf5Q7cDYZTEm/v5NNM2fsIeChnYPwJxjN2xt9qpGPe64Z/u+K34wvZrHIwgn9dHi1L HFOuxIFKXN6JCwxK0I2UbvR4tOfWf1EXQ5WsSjt6cwh7fJbCp93FDbIKMTscj6k3rwkW KNx3ivwAGDiuuMo5cmTuADDAXlPzIxauaEX6CySTJs/IZBqL66SR+Uigwk7SOBiG2sa1 qrIg== X-Gm-Message-State: APjAAAX88OXmuw5bCe7SHlZs2Sxpwr1F1tMEqM/raHY4DNkvBLKTYeh1 nB6HOp4JBPDUDK+vc/WTuo5MhA== X-Google-Smtp-Source: APXvYqwuemIlhiDoQ8VJnBGzwlpCiV36cLa8WrJS/hDozVNhFd/bOdMjfvdG7HvT5pD0k4dNtI97KQ== X-Received: by 2002:a19:4f42:: with SMTP id a2mr1168480lfk.23.1564051370665; Thu, 25 Jul 2019 03:42:50 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-44-230.bbcust.telenor.se. [83.226.44.230]) by smtp.gmail.com with ESMTPSA id e62sm9035045ljf.82.2019.07.25.03.42.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:50 -0700 (PDT) From: Niklas Cassel To: Niklas Cassel , Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Date: Thu, 25 Jul 2019 12:41:38 +0200 Message-Id: <20190725104144.22924-11-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring --- Changes since V1: -Picked up tags. .../bindings/power/avs/qcom,cpr.txt | 193 ++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..93be67fa8f38 --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,193 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: + Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 + +- reg: + Usage: required + Value type: + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: + Definition: should specify the CPR interrupt + +- clocks: + Usage: required + Value type: + Definition: phandle to the reference clock + +- clock-names: + Usage: required + Value type: + Definition: must be "ref" + +- vdd-apc-supply: + Usage: required + Value type: + Definition: phandle to the vdd-apc-supply regulator + +- #power-domain-cells: + Usage: required + Value type: + Definition: should be 0 + +- operating-points-v2: + Usage: required + Value type: + Definition: A phandle to the OPP table containing the + performance states supported by the CPR + power domain + +- acc-syscon: + Usage: optional + Value type: + Definition: phandle to syscon for writing ACC settings + +- nvmem-cells: + Usage: required + Value type: + Definition: phandle to nvmem cells containing the data + that makes up a fuse corner, for each fuse corner. + As well as the CPR fuse revision. + +- nvmem-cell-names: + Usage: required + Value type: + Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", + "cpr_quotient_offset3", "cpr_init_voltage1", + "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", + "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", + "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" + for qcs404. + +- qcom,cpr-timer-delay-us: + Usage: required + Value type: + Definition: delay in uS for the timer interval + +- qcom,cpr-timer-cons-up: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing an up + interrupt + +- qcom,cpr-timer-cons-down: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing a down + interrupt + +- qcom,cpr-up-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping up + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping down + +- qcom,cpr-idle-clocks: + Usage: optional + Value type: + Definition: Idle clock cycles ring oscillator can be in + +- qcom,cpr-gcnt-us: + Usage: required + Value type: + Definition: The time for gate count in uS + +- qcom,vdd-apc-step-up-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling up + +- qcom,vdd-apc-step-down-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling down + +Example: + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + .... + }; + cpr_opp2: opp2 { + opp-level = <2>; + .... + }; + cpr_opp3: opp3 { + opp-level = <3>; + .... + }; + }; + + cpr@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + + qcom,cpr-timer-delay-us = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <3>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-us = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + };