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Wed, 17 Jul 2019 03:50:33 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer , Peng Fan , Jagan Teki , Oleksandr Zhadan and Michael Durrant Thread-Topic: [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags Thread-Index: AQHVPFLJ0KEn/XiHgUiUWArsUXll8A== Date: Wed, 17 Jul 2019 03:50:33 +0000 Message-ID: <20190717035006.16634-2-anup.patel@wdc.com> References: <20190717035006.16634-1-anup.patel@wdc.com> In-Reply-To: <20190717035006.16634-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d773c9b1-407a-4dd8-5d64-08d70a69eb57 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SCL:1; SRVR:MN2PR04MB5630; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: lrMERLi1hh4iJRZy+5laDirk2JiNq6lbnGkWOzuuHOIAQaLH9yPUIsDYRF/+2xr2kSIh9kMu7BIzvAvkAhixVt3PI6jBTMs1KN7VUtvzEXz+AhF11ZyqjxAhUJON9RrvUIkeFihdxrpho28ir6ifH1qw4uaSVGr9LB39umQuGb28R+kXpX/ettJFqfirex1w06wJPekSpKcFIGYMswmWqrwGO4LZBy/DTJfsT0+6eXfyaPR/liSMZZM0Cfg4QaVwY0yz/0iG31iVIdfUp/EmB4ihn+jsRW3JhKRnAXLRT/6ewAPQrqTQFsuhoA3xYnOhG/Rhhhgvcsx5gjq994QSEjNZhDHfEIWVb9Rvzj2JNMztoTiTDozpZ26lEiZRb6s8RWjsYC5feszvK797UIzjcZz69tdTLUXz/cr+DA9A+hk= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d773c9b1-407a-4dd8-5d64-08d70a69eb57 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 03:50:33.6367 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5630 Cc: Palmer Dabbelt , U-Boot Mailing List Subject: [U-Boot] [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Most DM based SPI host controller drivers use SPI_XFER_BEGIN and SPI_XFER_END flags to enable/disable slave chip select. This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when MMC command is send at start and pass SPI_XFER_END flag using a dummy transfer (of bitlen = 0) at the end of MMC command. Suggested-by: Jagan Teki Signed-off-by: Anup Patel Reviewed-by: Jagan Teki --- drivers/mmc/mmc_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index f3d687ae80..350812a04b 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev, cmdo[4] = cmdarg >> 8; cmdo[5] = cmdarg; cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01; - ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0); + ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN); if (ret) return ret; @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd, } done: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); return ret; From patchwork Wed Jul 17 03:50:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1133071 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 17 Jul 2019 03:50:38 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer , Peng Fan , Jagan Teki , Oleksandr Zhadan and Michael Durrant Thread-Topic: [PATCH v5 2/4] spi: Add SiFive SPI driver Thread-Index: AQHVPFLLW34lQDyj1UmcjFd/D3KNWw== Date: Wed, 17 Jul 2019 03:50:38 +0000 Message-ID: <20190717035006.16634-3-anup.patel@wdc.com> References: <20190717035006.16634-1-anup.patel@wdc.com> In-Reply-To: <20190717035006.16634-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fe31746e-092a-4594-0a22-08d70a69ee50 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5630; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: LXnfpfWobKPs1TSNAsyFiqc7ppMgZwKImuLyTYFp3dJx03ylb6VlrUD9fPqJx0V2UZmC5De0j5ePw6sF1Rs59NNMm6/lBOKqlyjrDSWJh6mpjF8p/SUXVO3Lssyt19CGmb7nKWK7BL2YI1R2VeYPn96doi5I5zI+KTwGG9RmtdCmkurbQTzUpcAYBu+i54Qh/gl+PxafE+Ro2bHaj6DKr9Qlk9G2ZFA3fllXa21D1h4Wg7NPNU4EDlJbSzDaK88XIFcDj43/yW3eIwwrOmySBlVAl4HU74iiug47V3nZiPrO3wEssNAAUgdx2sn9Mf5OYS4Yqr/sWkvGryeYkPCvStI9kFsztqOyYOpNu6TWZl+8llHi2xC7Mk/UKJ4fBGkfx1D6bAOC2dsKt0dwLiM+A4rLx0tsfhwF7E4qM+sB6yA= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: fe31746e-092a-4594-0a22-08d70a69ee50 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 03:50:38.4769 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5630 Cc: Palmer Dabbelt , U-Boot Mailing List Subject: [U-Boot] [PATCH v5 2/4] spi: Add SiFive SPI driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Bhargav Shah This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 375 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 drivers/spi/spi-sifive.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..030f3377d4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; }; +config SPI_SIFIVE + bool "SiFive SPI driver" + help + This driver supports the SiFive SPI IP. If unsure say N. + Enable the SiFive SPI controller driver. + + The SiFive SPI controller driver is found on various SiFive SoCs. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..a53b9f4217 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 0000000000..08f30f3f21 --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah + * + * SiFive SPI controller driver (master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS 8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U +#define SIFIVE_SPI_FMT_PROTO_MASK 3U +#define SIFIVE_SPI_FMT_ENDIAN BIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) + +/* rxdata bits */ +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31) + +/* ie and ip bits */ +#define SIFIVE_SPI_IP_TXWM BIT(0) +#define SIFIVE_SPI_IP_RXWM BIT(1) + +struct sifive_spi { + void *regs; /* base address of the registers */ + u32 fifo_depth; + u32 bits_per_word; + u32 cs_inactive; /* Level of the CS pins when inactive*/ + u32 freq; + u32 num_cs; +}; + +static void sifive_spi_prep_device(struct sifive_spi *spi, + struct dm_spi_slave_platdata *slave) +{ + /* Update the chip select polarity */ + if (slave->mode & SPI_CS_HIGH) + spi->cs_inactive &= ~BIT(slave->cs); + else + spi->cs_inactive |= BIT(slave->cs); + writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); + + /* Select the correct device */ + writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID); +} + +static int sifive_spi_set_cs(struct sifive_spi *spi, + struct dm_spi_slave_platdata *slave) +{ + u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD; + + if (slave->cs > spi->num_cs) + return -EINVAL; + + if (slave->mode & SPI_CS_HIGH) + cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO; + + writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE); + + return 0; +} + +static void sifive_spi_clear_cs(struct sifive_spi *spi) +{ + writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE); +} + +static void sifive_spi_prep_transfer(struct sifive_spi *spi, + bool is_rx_xfer, + struct dm_spi_slave_platdata *slave) +{ + u32 cr; + + /* Modify the SPI protocol mode */ + cr = readl(spi->regs + SIFIVE_SPI_REG_FMT); + + /* Bits per word ? */ + cr &= ~SIFIVE_SPI_FMT_LEN_MASK; + cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word); + + /* LSB first? */ + cr &= ~SIFIVE_SPI_FMT_ENDIAN; + if (slave->mode & SPI_LSB_FIRST) + cr |= SIFIVE_SPI_FMT_ENDIAN; + + /* Number of wires ? */ + cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; + if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD)) + cr |= SIFIVE_SPI_FMT_PROTO_QUAD; + else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL)) + cr |= SIFIVE_SPI_FMT_PROTO_DUAL; + else + cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; + + /* SPI direction in/out ? */ + cr &= ~SIFIVE_SPI_FMT_DIR; + if (!is_rx_xfer) + cr |= SIFIVE_SPI_FMT_DIR; + + writel(cr, spi->regs + SIFIVE_SPI_REG_FMT); +} + +static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr) +{ + u32 data; + + do { + data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA); + } while (data & SIFIVE_SPI_RXDATA_EMPTY); + + if (rx_ptr) + *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK; +} + +static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr) +{ + u32 data; + u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK : + SIFIVE_SPI_TXDATA_DATA_MASK; + + do { + data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA); + } while (data & SIFIVE_SPI_TXDATA_FULL); + + writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA); +} + +static int sifive_spi_claim_bus(struct udevice *dev) +{ + /* Nothing to do here. */ + return 0; +} + +static int sifive_spi_release_bus(struct udevice *dev) +{ + /* Nothing to do here. */ + return 0; +} + +static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct sifive_spi *spi = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + const unsigned char *tx_ptr = dout; + u8 *rx_ptr = din; + u32 remaining_len; + int ret; + + if (flags & SPI_XFER_BEGIN) { + sifive_spi_prep_device(spi, slave); + + ret = sifive_spi_set_cs(spi, slave); + if (ret) + return ret; + } + + sifive_spi_prep_transfer(spi, true, slave); + + remaining_len = bitlen / 8; + + while (remaining_len) { + int n_words, tx_words, rx_words; + + n_words = min(remaining_len, spi->fifo_depth); + + /* Enqueue n_words for transmission */ + if (tx_ptr) { + for (tx_words = 0; tx_words < n_words; ++tx_words) { + sifive_spi_tx(spi, tx_ptr); + sifive_spi_rx(spi, NULL); + tx_ptr++; + } + } + + /* Read out all the data from the RX FIFO */ + if (rx_ptr) { + for (rx_words = 0; rx_words < n_words; ++rx_words) { + sifive_spi_tx(spi, NULL); + sifive_spi_rx(spi, rx_ptr); + rx_ptr++; + } + } + + remaining_len -= n_words; + } + + if (flags & SPI_XFER_END) + sifive_spi_clear_cs(spi); + + return 0; +} + +static int sifive_spi_set_speed(struct udevice *bus, uint speed) +{ + struct sifive_spi *spi = dev_get_priv(bus); + u32 scale; + + if (speed > spi->freq) + speed = spi->freq; + + /* Cofigure max speed */ + scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1) + & SIFIVE_SPI_SCKDIV_DIV_MASK; + writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV); + + return 0; +} + +static int sifive_spi_set_mode(struct udevice *bus, uint mode) +{ + struct sifive_spi *spi = dev_get_priv(bus); + u32 cr; + + /* Switch clock mode bits */ + cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) & + ~SIFIVE_SPI_SCKMODE_MODE_MASK; + if (mode & SPI_CPHA) + cr |= SIFIVE_SPI_SCKMODE_PHA; + if (mode & SPI_CPOL) + cr |= SIFIVE_SPI_SCKMODE_POL; + + writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE); + + return 0; +} + +static void sifive_spi_init_hw(struct sifive_spi *spi) +{ + u32 cs_bits; + + /* probe the number of CS lines */ + spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); + writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF); + cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); + writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); + if (!cs_bits) { + printf("Could not auto probe CS lines\n"); + return; + } + + spi->num_cs = ilog2(cs_bits) + 1; + if (spi->num_cs > SIFIVE_SPI_MAX_CS) { + printf("Invalid number of spi slaves\n"); + return; + } + + /* Watermark interrupts are disabled by default */ + writel(0, spi->regs + SIFIVE_SPI_REG_IE); + + /* Set CS/SCK Delays and Inactive Time to defaults */ + writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1), + spi->regs + SIFIVE_SPI_REG_DELAY0); + writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0), + spi->regs + SIFIVE_SPI_REG_DELAY1); + + /* Exit specialized memory-mapped SPI flash mode */ + writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL); +} + +static int sifive_spi_probe(struct udevice *bus) +{ + struct sifive_spi *spi = dev_get_priv(bus); + struct clk clkdev; + int ret; + + spi->regs = (void *)(ulong)dev_remap_addr(bus); + if (!spi->regs) + return -ENODEV; + + spi->fifo_depth = dev_read_u32_default(bus, + "sifive,fifo-depth", + SIFIVE_SPI_DEFAULT_DEPTH); + + spi->bits_per_word = dev_read_u32_default(bus, + "sifive,max-bits-per-word", + SIFIVE_SPI_DEFAULT_BITS); + + ret = clk_get_by_index(bus, 0, &clkdev); + if (ret) + return ret; + spi->freq = clk_get_rate(&clkdev); + + /* init the sifive spi hw */ + sifive_spi_init_hw(spi); + + return 0; +} + +static const struct dm_spi_ops sifive_spi_ops = { + .claim_bus = sifive_spi_claim_bus, + .release_bus = sifive_spi_release_bus, + .xfer = sifive_spi_xfer, + .set_speed = sifive_spi_set_speed, + .set_mode = sifive_spi_set_mode, +}; + +static const struct udevice_id sifive_spi_ids[] = { + { .compatible = "sifive,spi0" }, + { } +}; + +U_BOOT_DRIVER(sifive_spi) = { + .name = "sifive_spi", + .id = UCLASS_SPI, + .of_match = sifive_spi_ids, + .ops = &sifive_spi_ops, + .priv_auto_alloc_size = sizeof(struct sifive_spi), + .probe = sifive_spi_probe, +}; From patchwork Wed Jul 17 03:50:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1133072 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 17 Jul 2019 03:50:43 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer , Peng Fan , Jagan Teki , Oleksandr Zhadan and Michael Durrant Thread-Topic: [PATCH v5 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers Thread-Index: AQHVPFLOFgz2u/hYk0ScXwVzySo+Lg== Date: Wed, 17 Jul 2019 03:50:43 +0000 Message-ID: <20190717035006.16634-4-anup.patel@wdc.com> References: <20190717035006.16634-1-anup.patel@wdc.com> In-Reply-To: <20190717035006.16634-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2fe7e635-4a28-44bd-2d43-08d70a69f137 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SFP:1102; SCL:1; SRVR:MN2PR04MB5630; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: D16F9BdQyy7wfjM6PCbVlk03/LWo6KKoqSwEwr+VF/hxRjqyb0On90wmRhmCTaOH58fw0jNv4/f9nf2HUEIVx6lAtviRy/oA7p2BVE/pnFU6F/BTuRXtcATjRfJVi2HBxjBkddBmjtz2nLk0IWv4/smtPVsz03lJAlDDElEh23Rw3C7CkLqECkveeC+ob51fBChoSTpDRaEpQ87mcc7PeAHtD2eIPSjyWNKTpsuT2hFNHjmhZi4HHxjE0ddrX9IynTKxtrMYvlZAZvX1V553JH/LV/iVo56lYVCI0UjTjIFqeS/F1ylvnoudb3u1IvejfjXnhg6leBN2TvJste0PSSFY+7qwnxJf1DEnfLjOIvLgpbyuzVqKPqTomclKalu4PniApVhdul4PDKuBui1UhA1p3Bx/uHNdMB9lyzsSTck= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2fe7e635-4a28-44bd-2d43-08d70a69f137 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 03:50:43.4531 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5630 Cc: Palmer Dabbelt , U-Boot Mailing List Subject: [U-Boot] [PATCH v5 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Bhargav Shah This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Jagan Teki --- board/sifive/fu540/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d..5d65080429 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -38,6 +38,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC imply SIFIVE_SERIAL + imply SPI + imply SPI_SIFIVE + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC imply SMP endif From patchwork Wed Jul 17 03:50:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1133073 X-Patchwork-Delegate: van.freenix@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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Wed, 17 Jul 2019 03:50:49 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer , Peng Fan , Jagan Teki , Oleksandr Zhadan and Michael Durrant Thread-Topic: [PATCH v5 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers Thread-Index: AQHVPFLSDhiXwpidrkWejOPWJQ1eaQ== Date: Wed, 17 Jul 2019 03:50:49 +0000 Message-ID: <20190717035006.16634-5-anup.patel@wdc.com> References: <20190717035006.16634-1-anup.patel@wdc.com> In-Reply-To: <20190717035006.16634-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5cd0f6b1-752d-44e6-8093-08d70a69f494 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SFP:1102; SCL:1; SRVR:MN2PR04MB5630; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: USLoVUFqybAr5jhO5d1S3jsNtp5hMu6ZBoNi9h+Fgohk7fKKLPG0LZmJGrDDm7KU/V4Q+KLi7U7rCP4qyIH8HfgDkKeKC5tl1VERqpyISiUsgaE+glVZ41tSaymXJio/3w/JBU0J6dVJay153q1xMhwcmafOIOc8fCii7OGHjTyL3dXxrSqAib9Ex14Tz/E/XGx+LvC7j3jYEYB21728+F8c67l8HXpvcnbKnlWfrMLxP8b5R8SEhr8w5VZ+AcSigD67qJ9fN1oU6ocAcCdlPEKfO92z1onjLBwQWEML8TYKZJWLc0n65QJ7uQL57Qyv8duSe5eEZnU9/zbw5y/1u/8U8A4fzYhDc6y1gxZpfU07X5ycB+KP0te+Gm3E9FJDCUwf5PtLgdmkUnCHiu3CVqDo8bS2b4ytxpWJOelwvOU= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5cd0f6b1-752d-44e6-8093-08d70a69f494 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 03:50:49.1019 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Anup.Patel@wdc.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5630 Cc: Palmer Dabbelt , U-Boot Mailing List Subject: [U-Boot] [PATCH v5 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch removes SiFive SPI driver and MMC SPI drive from the TODO list in SiFive FU540 README. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- doc/README.sifive-fu540 | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540 index 33e03dc861..944ba1c8a0 100644 --- a/doc/README.sifive-fu540 +++ b/doc/README.sifive-fu540 @@ -13,9 +13,7 @@ The support for following drivers are already enabled: 3. Cadence MACB ethernet driver for networking support. TODO: -1. SPI host driver is still missing. -2. SPI MMC driver does not compile and needs a re-write using U-Boot DM. -2. U-Boot expects the serial console device entry to be present under /chosen +1. U-Boot expects the serial console device entry to be present under /chosen DT node. Example: chosen { stdout-path = "/soc/serial@10010000:115200";