From patchwork Wed Jul 10 15:23:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 1130460 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45kNHV58fWz9sMQ for ; Thu, 11 Jul 2019 01:23:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 467CDC21F95; Wed, 10 Jul 2019 15:23:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D938AC21D8E; Wed, 10 Jul 2019 15:23:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 99719C21D65; Wed, 10 Jul 2019 15:23:09 +0000 (UTC) Received: from mx.tkos.co.il (guitar.tcltek.co.il [192.115.133.116]) by lists.denx.de (Postfix) with ESMTPS id 3D6DFC21DED for ; Wed, 10 Jul 2019 15:23:07 +0000 (UTC) Received: from sapphire.lan (unknown [192.168.100.188]) by mx.tkos.co.il (Postfix) with ESMTP id 1249F440271; Wed, 10 Jul 2019 18:23:06 +0300 (IDT) From: Baruch Siach To: u-boot@lists.denx.de, Stefan Roese Date: Wed, 10 Jul 2019 18:23:04 +0300 Message-Id: X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Cc: Baruch Siach , Dennis Gilmore , Gauthier Provost , Aditya Prayoga , Chris Packham , Chris Packham Subject: [U-Boot] [PATCH v2] arm: mvebu: set 38x and 39x AVS on lower frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Reduce Auto Voltage Scaling VDD limit when core frequency is lower than 1600MHz. This reduces core voltage level from 1.25V to 1.15V, which saves power. The code is taken from Marvell's U-Boot 2013.01 revision 18.06. Reviewed-by: Chris Packham Tested-by: Chris Packham Signed-off-by: Baruch Siach --- v2: Fix build for Armada XP --- arch/arm/mach-mvebu/include/mach/cpu.h | 7 +++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 26 +++++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 4 +++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 40 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index e6140d67293e..2e2d72aac892 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -163,6 +163,13 @@ int serdes_phy_config(void); */ int ddr3_init(void); +/* Auto Voltage Scaling */ +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) +void mv_avs_init(void); +#else +static inline void mv_avs_init(void) {} +#endif + /* * get_ref_clk * diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index d387893af37d..e9dd096ad0f5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -256,3 +256,29 @@ u8 sys_env_device_rev_get(void) value = reg_read(DEV_VERSION_ID_REG); return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; } + +void mv_avs_init(void) +{ + u32 sar_freq; + + if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X))) + return; + + reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); + reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); + + sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); + sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK; + + /* Set AVS value only for core frequency of 1600MHz or less. + * For higher frequency leave the default value. + */ + if (sar_freq <= 0xd) { + u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL); + + avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK + | AVS_HIGH_VDD_LIMIT_MASK); + avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL; + reg_write(AVS_ENABLED_CONTROL, avs_reg_data); + } +} diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 365332d2b048..1774a5b780ca 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -33,6 +33,8 @@ #define DEV_ID_REG_DEVICE_ID_OFFS 16 #define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000 +#define SAR_FREQ_OFFSET 10 +#define SAR_FREQ_MASK 0x1f #define SAR_DEV_ID_OFFS 27 #define SAR_DEV_ID_MASK 0x7 @@ -155,10 +157,12 @@ #define AVS_LOW_VDD_LIMIT_OFFS 4 #define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS) +#define AVS_LOW_VDD_SLOW_VAL (0x23 << AVS_LOW_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_OFFS 12 #define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS) #define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS) +#define AVS_HIGH_VDD_SLOW_VAL (0x23 << AVS_HIGH_VDD_LIMIT_OFFS) /* Board ID numbers */ #define MARVELL_BOARD_ID_MASK 0x10 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index d54de5195624..3cb27b7f4b20 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -126,6 +126,9 @@ void board_init_f(ulong dummy) ddr3_init(); #endif + /* Initialize Auto Voltage Scaling */ + mv_avs_init(); + /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool.