From patchwork Fri Jul 5 09:57:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1127911 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="MWycKuBR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45g9JP5Hkfz9sPF for ; Fri, 5 Jul 2019 19:57:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728375AbfGEJ5s (ORCPT ); Fri, 5 Jul 2019 05:57:48 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:44978 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728188AbfGEJ5r (ORCPT ); Fri, 5 Jul 2019 05:57:47 -0400 Received: by mail-lf1-f66.google.com with SMTP id r15so5925666lfm.11 for ; Fri, 05 Jul 2019 02:57:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aR9uAvgeaPzmKk1YhWutKX7D15M3aAKx9HHCruqrY3s=; b=MWycKuBRX+yk7xrNtRuZUKiQquKUSF3f8BCs3i94Tg0jpBzZZSvrg/KD7XjF4dZzSj WSrqJ6zerqnMOvMfSPwSVX3FvQGTSplMbTnriDo9DNz+qLIXcuuEsZ5lpvxuokKTpCBK 91jIzkvGtmoB8LaQtWv0mH8JH43enZMRtsDRSFjZY/Lh4IBxpsbtWgkEWI2FSsmU2vRs e5akyZHNQOVUmjeUAH2tLlxyWfr/pDHyCokuz1SLnr7wKHi8quESwtQgQdlN8CW0Eqlp is8yXlOGy337hHmkBlxu5b/sOae3LXt5VVrrXfKPDVNivJ+s5X4AhNns1P5oip54DDm6 UzjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aR9uAvgeaPzmKk1YhWutKX7D15M3aAKx9HHCruqrY3s=; b=emhoGdCOxp6R3CbFUjkS0oCcmk3fZ2OGDBfpwKsQNJEIuDvhRzYfW48KBTZiPoFYfV GG0+7AquHOh1kZozqC/kSHU13gJl20725xOyzXKdFsYPBCgvQjXScHl081XgdD9PqX8c KQt0JjvQGt4whwK+N8urjyakofgpziJnRG6OQA5FjG0hJMBRhVkfVS8TnclNrsSGTPVo RjhNlB4xpOnYmcdPjgvsQg0OMLTWG7jYdwcq7NSCJoZAfqUoIzjCeK7th32flodCyQF5 JsLVeWCEDbPDs8aCwb7KgirR2O5MkGqUczDtukE5gyuHvDFvLGP0ve5dxpEhxs0PdysU +3tQ== X-Gm-Message-State: APjAAAU3S9mFCoYJMisl/4SuWUUSV7UALZ/D3qoGFnRAY3/6NMG0BrYx msZIOKRCywYWJD1SuezgNS/v7A== X-Google-Smtp-Source: APXvYqzKvDyiKWeIXmJyoQuAirsIgVLFmJHimarCgDX5CCLbzQQDbDzznUGhL8wvlYup85IAH62Q6Q== X-Received: by 2002:a19:7709:: with SMTP id s9mr1485305lfc.86.1562320665755; Fri, 05 Jul 2019 02:57:45 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-34-119.bbcust.telenor.se. [83.226.34.119]) by smtp.gmail.com with ESMTPSA id q2sm1298364lfj.25.2019.07.05.02.57.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 05 Jul 2019 02:57:45 -0700 (PDT) From: Niklas Cassel To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Ilia Lin , Andy Gross Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Sricharan R , Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/13] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Date: Fri, 5 Jul 2019 11:57:12 +0200 Message-Id: <20190705095726.21433-2-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org> References: <20190705095726.21433-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sricharan R The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R [niklas.cassel@linaro.org: split dt-binding into a separate patch and do not rename the compatible string.] Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin Reviewed-by: Rob Herring --- Changes since RFC: -Made DT bindings a separate patch. -Keep the original compatible string, since renaming it breaks DT backwards compatibility. .../opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%) diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt similarity index 98% rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c2127b96805a..198441e80ba8 100644 --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -1,13 +1,13 @@ -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 -that have KRYO processors, the CPU ferequencies subset and voltage value -of each OPP varies based on the silicon variant in use. +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, +the CPU frequencies subset and voltage value of each OPP varies based on +the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. From patchwork Fri Jul 5 09:57:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1127916 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="yF9Y4TXd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45g9LD5V7rz9sPF for ; Fri, 5 Jul 2019 19:59:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727753AbfGEJ7b (ORCPT ); Fri, 5 Jul 2019 05:59:31 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:38529 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728399AbfGEJ6F (ORCPT ); Fri, 5 Jul 2019 05:58:05 -0400 Received: by mail-lj1-f193.google.com with SMTP id r9so8689856ljg.5 for ; Fri, 05 Jul 2019 02:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VUCWK2MsD9fKCW5H56U5T5vRzO2k7QDz1z157zPKgz4=; b=yF9Y4TXdbukUm95Tym+SSRRKXOgy30rcUTY/I/w2ob/pI2Xk6mM2EFws9z/z9Jy5cn 5yH51ejAX7BSHtxlej6Sietfapi0cefT59q9jJN1ifMQjBqWA/apLst7ul9igPrQzDk2 drpnxdar+aTtUDEWi3y8Cvaxy3V5c8w9TqANXQggoaL7EEGMCiDWenolNKnmfMlIz6hF LA7dy1MeKgwm/taneDq3mE/Cww1ynKWrGI+PksCPx8K3tIZOtjsxbHUhCVxP0us659eW TmBrcMnTRQnSIVFZY+/4qysi0crgRy02/xmt3FLPdAsn0bXiaXQyjMv1jXGLbzNsj4go eyAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VUCWK2MsD9fKCW5H56U5T5vRzO2k7QDz1z157zPKgz4=; b=Ztnnrd6Mzya01OBp/tPMMoH0Ykbmy4EXo2aY+rURpjLGdaEXewH5aH6U6utMionRUg OLg16eF7FpbFo4xvThRBv4ATRq53ZX9tmPI32mtrFXMzeWJF5J0GwROHajuc7yRCo0P/ 9nqZg9ujYqRu1Kc/zR9FA7VnPAWJowJiwMUiDmjRjJEFQ8zKczqB3EyXMnSV23GMPwaJ IaM4JREnX4VXmbsP+wrKWF0aIvshXZUW7JaYCXCVC0mKdZeVqcEGDKOAtbx1ClA0x9qu PBkbwQxmoHFFIoPcLJ94e3jzvyWXu7vjpWegDvjpfkJEaedh+22gWkjQggESw+jUV0vW lbAQ== X-Gm-Message-State: APjAAAUBx+enoWxwyKwjeqs+2o/oERdyUvVQaDNf82qH+VC5qygRptJm hVuzBBVL6mkpYoxDLi/mIWuTIA== X-Google-Smtp-Source: APXvYqx0ZiI7NUTcCSAcDJg+m43On7JBoo/yMllTvC1H2ViTfIYfM/r31p51tmof/TzmGg/DplB8aw== X-Received: by 2002:a2e:9758:: with SMTP id f24mr1723330ljj.58.1562320683615; Fri, 05 Jul 2019 02:58:03 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-34-119.bbcust.telenor.se. [83.226.34.119]) by smtp.gmail.com with ESMTPSA id 25sm1692704ljn.62.2019.07.05.02.58.02 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 05 Jul 2019 02:58:02 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/13] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Date: Fri, 5 Jul 2019 11:57:14 +0200 Message-Id: <20190705095726.21433-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org> References: <20190705095726.21433-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Not all Qualcomm platforms need to care about the speedbin efuse, nor the value blown into the speedbin efuse. Therefore, make the nvmem-cells and opp-supported-hw properties optional. Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index 198441e80ba8..c5ea8b90e35d 100644 --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -20,6 +20,10 @@ In 'cpus' nodes: In 'operating-points-v2' table: - compatible: Should be - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. + +Optional properties: +-------------------- +In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage From patchwork Fri Jul 5 09:57:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1127913 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="hmExekYi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45g9Jt10z2z9sP7 for ; Fri, 5 Jul 2019 19:58:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727764AbfGEJ6U (ORCPT ); Fri, 5 Jul 2019 05:58:20 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:43026 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728429AbfGEJ6I (ORCPT ); Fri, 5 Jul 2019 05:58:08 -0400 Received: by mail-lf1-f65.google.com with SMTP id c19so313921lfm.10 for ; Fri, 05 Jul 2019 02:58:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3GNalLtrTqW5s+BFJJMMFnFc3aO7NBuze3htvzi00W0=; b=hmExekYi60+hf8c4YDeaGqFYkUdJGMndPOTAz0wzT5VaYrhc79TdPrC82wL7SI1HMS 4B9mDD2JiVa++vAEXHVQb0+EI7rCDihpO7F40mAaBXF7Uk9HbWS/PAUzo7lcLs1D+Z+5 +VCR+V4xb6J4WTh8C16gju5+rR5NbyRcecrcUSwIsPl0ZzwWjh9zoIUlEBYwFgv9gE9s YZU+4liOcFjYB4deygvG/JxyDYUhIx9AambMTyv7d4zxy7I1buYsHQHlCwGBegiQVp1R vigjgZqTKy8zqnB1XSWpP3VssMyj7Beg5ro1l+jhu2Vwbsl++Xdy1jq8OMNcv8pL3J7+ 4otA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3GNalLtrTqW5s+BFJJMMFnFc3aO7NBuze3htvzi00W0=; b=oDp9zibe20DjofM2M7pCyD2fJlQYpBcNdjb1qST7iDajISwVKVhE/yCDKfdO32YdLN /jr7cCEBBZ5WWr7c4kYfCUSR6abrZzGvrfQVdINhBz4l73B3p26A0d+aO492j3MdY1ZX TR8u7Ajab0SffCQzECOpT8Yq+DTqZRyVOW004h+rRKwHaGtmAOq/becESWnuYFmK8LBC b7VnkFA+LeKcDtDOt9wCzTHDH3dZdsakrLtXGLn+iFcH+8scgfkCaTYdaKyfbDD6F2oC iQx0PCGsV22w7bjq62asEHM0enwjpe7DJtdHsOrQRcKy1h6e+yVAdBtuMYj1d3eavl7X M51A== X-Gm-Message-State: APjAAAV8LNDr8piLbmhbbZr6oWEBEvjpSrJmJUgYAK34e7rYy4x4uOoY Iwz5I8sVErCnVVRYa1yJCnH0bA== X-Google-Smtp-Source: APXvYqwE4CIl8CEAtpIJlQJkbUer2Z0hhINHb7uHx65wmIJHGa6qKcwuuJ0HkO9FENk2/2/WJUlxRg== X-Received: by 2002:ac2:4a6e:: with SMTP id q14mr1583691lfp.154.1562320686116; Fri, 05 Jul 2019 02:58:06 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-34-119.bbcust.telenor.se. [83.226.34.119]) by smtp.gmail.com with ESMTPSA id 25sm1692704ljn.62.2019.07.05.02.58.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 05 Jul 2019 02:58:05 -0700 (PDT) From: Niklas Cassel To: Ilia Lin , Andy Gross , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/13] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Date: Fri, 5 Jul 2019 11:57:16 +0200 Message-Id: <20190705095726.21433-6-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org> References: <20190705095726.21433-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some Qualcomm SoCs have support for Core Power Reduction (CPR). On these platforms, we need to attach to the power domain provider providing the performance states, so that the leaky device (the CPU) can configure the performance states (which represent different CPU clock frequencies). Signed-off-by: Niklas Cassel --- .../bindings/opp/qcom-nvmem-cpufreq.txt | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c5ea8b90e35d..e19a95318e98 100644 --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -23,6 +23,15 @@ In 'operating-points-v2' table: Optional properties: -------------------- +In 'cpus' nodes: +- power-domains: A phandle pointing to the PM domain specifier which provides + the performance states available for active state management. + Please refer to the power-domains bindings + Documentation/devicetree/bindings/power/power_domain.txt + and also examples below. +- power-domain-names: Should be + - 'cpr' for qcs404. + In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the @@ -682,3 +691,105 @@ soc { }; }; }; + +Example 2: +--------- + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + .... + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + power-domains = <&cprpd>; + power-domain-names = "cpr"; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cpr_opp1>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cpr_opp2>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cpr_opp3>; + }; + }; + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + .... + }; + cpr_opp2: opp2 { + opp-level = <2>; + .... + }; + cpr_opp3: opp3 { + opp-level = <3>; + .... + }; + }; + +.... + +soc { +.... + cprpd: cpr@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + .... + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + .... + }; +}; From patchwork Fri Jul 5 09:57:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1127914 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="quRGeLJj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45g9K46H9zz9sPF for ; Fri, 5 Jul 2019 19:58:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728511AbfGEJ61 (ORCPT ); Fri, 5 Jul 2019 05:58:27 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:40621 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728505AbfGEJ60 (ORCPT ); Fri, 5 Jul 2019 05:58:26 -0400 Received: by mail-lf1-f67.google.com with SMTP id b17so2342414lff.7 for ; Fri, 05 Jul 2019 02:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T9WpS+HVMWD8ur8SuhCnKoutTiVOWrWJ89RfcZ9PQgs=; b=quRGeLJjnlYqiflrezgM9kTuvWWmR1zElFnf5iYvD6ljqXJwm3FmkqeRkRI8tu9o55 pxGzSYze1Z/rEWljHvZYqpXsWpx0qSEKUk12LrEB7Dorbpjf/PwlfpvkyEy2KxeCXbgF xAnbDlYHPjDVY9wr1ilAS6D1dP/LI6zC06Idbk+lP67Giqvc/CZ1Oj+40YW484PcRmQl FMV4k0tkNpGw5VEtUwmeq5FghK2vS5XB7cIrrenYBqeOjWPjuZ6tZ9LnfRtRn0QTnFXD 1db1A99zKgpkWI/fh8808GVMPvpVu64sB7wCPFfXjDKzA0vIO7cWiSzMlfzeZZhuk8oN tMzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T9WpS+HVMWD8ur8SuhCnKoutTiVOWrWJ89RfcZ9PQgs=; b=Jc+yZCuYbPXW+2CBtOft9uLv1OMLoWARk+LP1SMLDBTgbH9ekqoUgHiklenYGfO/zk wAQAok1Xz0aDiM5YJklEUbYRz2xhdMR2zkmo5P3QYfo3XvEfc6jVB5/tzNh+eyDk8zZB mMk69RcfKGno0p42fqUMz84OQkqRHf4IL2/UPbgxFFkUV1BwKG20gRh+3WwKg12Q+Z+y oDqFZY7lJdK68Ob6ALmFFUPbEw9G8p71i8L2lWGlOLe2CfZK92isgeMJqTjkzoLDeFqg /Mq08B1jHty7MEAgQtzpT6hRPm//g8DB2h+3aThLThfZ8htXu3fA2Os04thQt3qIK1f2 0MAw== X-Gm-Message-State: APjAAAXi4A+UNx60G1r+sVcDD3MXmLF6HWv7EERDprVbkBzW02aickKG QTOg7iJEx7pe2SQOMzL29XQLSw== X-Google-Smtp-Source: APXvYqzGZq9cBAG/9YdbDllNDNna+6azYgs4EKNX4aNr+IHo7Lltk3lagnCn4o+pTRCRoswpV++XEw== X-Received: by 2002:a05:6512:288:: with SMTP id j8mr1701505lfp.181.1562320704609; Fri, 05 Jul 2019 02:58:24 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-34-119.bbcust.telenor.se. [83.226.34.119]) by smtp.gmail.com with ESMTPSA id o24sm1674955ljg.6.2019.07.05.02.58.23 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 05 Jul 2019 02:58:23 -0700 (PDT) From: Niklas Cassel To: Andy Gross , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/13] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Date: Fri, 5 Jul 2019 11:57:19 +0200 Message-Id: <20190705095726.21433-9-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org> References: <20190705095726.21433-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add qcom-opp bindings with properties needed for Core Power Reduction (CPR). CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and msm8996. CPR was first introduced in msm8974. Changes since RFC: -Removed opp-hz. It is already an optional property in opp.txt so no need to specify it with the same definition here. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../devicetree/bindings/opp/qcom-opp.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..f204685d029c --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,19 @@ +Qualcomm OPP bindings to describe OPP nodes + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom-level" + +* OPP Node + +Optional properties: +- qcom,opp-fuse-level: A positive value representing the fuse corner/level + associated with this OPP node. Sometimes several corners/levels shares + a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, + min uV, and max uV. From patchwork Fri Jul 5 09:57:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 1127915 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="eOccLffm"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45g9Km2rHQz9sNs for ; Fri, 5 Jul 2019 19:59:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727275AbfGEJ7G (ORCPT ); Fri, 5 Jul 2019 05:59:06 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:45959 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728541AbfGEJ6v (ORCPT ); Fri, 5 Jul 2019 05:58:51 -0400 Received: by mail-lf1-f68.google.com with SMTP id u10so5922454lfm.12 for ; Fri, 05 Jul 2019 02:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BouLqQLTHVtW6gFNYbo0Duh1Donpb8dO1sfN++w1gqU=; b=eOccLffmHigtjDuidT0JUO5zFObHn2WpwcWTuU72p0WEJ2F32za6U/ywDevYSzdSpz vYKgDSFPO7O6Jf3MeaCgP/S9Aejb5L28A8tElumX/rJiPrQ9b5PBgQ4s873/Bg7vTnj2 i7P2yfv6c6SQr6Q7uGBpObvLBErMaqGHpeudyBS2/vljXpRHKWSDwUb9qQUzlPKHDF48 +mt34SXz7xsgOeZQEPwOCn9UXzNVqkxrg3ul2P3VXHjgTYbR9IQzJRJDvxU7lz8RODW5 JuONCzE44IK0ED0Z6Vopbd9bej2zo2qPbyn5LD5do4YsP8LjHBJXO/QhOzYzvxWQ59EX kb7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BouLqQLTHVtW6gFNYbo0Duh1Donpb8dO1sfN++w1gqU=; b=gvGpZQQzFnApD4j4rawFx8ouEHfPSnyHg0UbJPg4nYankynoTdROa3NtVCYUQ6jTtb KQRXXErSmIVt8TABFp88gytHxgmLohTWYN+2V3coxRtOssDa6mDpw5mzw5x+Fl8y4IRJ dliSET56POswmsScQrj0KD9mKXBXwiIJXwXS89B5rTsGBThlGG7XDd34+kOsFyxVCvfK rPuGqfnWmvxTzKqc/OGonypY3NBSGxBkO+e4h1gpsemb4GfXJ2ojcXTRkQaTPb5PNcrJ Dg1mLrPnA7ujoOTkoLcVQSCzPkdVkUWVR9cVy0TDtrst4KgQxiKBI2wqoQ6aU4YtKjW3 xfzA== X-Gm-Message-State: APjAAAWkmb+cu0rUElmUfQObeP72rnzdi4cHxGONfXERDljXqGnv+iIi 2mwFc+GF5qhg8ajI7K0s/pOKMQ== X-Google-Smtp-Source: APXvYqxwBj6+cx9oMqstKNbcYa5jdZwb9JBq6Hbs2rtLoooEU8TMHSnjKOAdQW1aCbt6OG+HWNAsOQ== X-Received: by 2002:ac2:5b09:: with SMTP id v9mr1562324lfn.22.1562320728034; Fri, 05 Jul 2019 02:58:48 -0700 (PDT) Received: from localhost.localdomain (ua-83-226-34-119.bbcust.telenor.se. [83.226.34.119]) by smtp.gmail.com with ESMTPSA id m5sm1152111lfa.47.2019.07.05.02.58.39 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 05 Jul 2019 02:58:47 -0700 (PDT) From: Niklas Cassel To: Niklas Cassel , Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/13] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Date: Fri, 5 Jul 2019 11:57:20 +0200 Message-Id: <20190705095726.21433-10-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190705095726.21433-1-niklas.cassel@linaro.org> References: <20190705095726.21433-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs. Changes since RFC: -Make compatible string SoC specific. -Changed interrupt definition. -Use clock binding for reference clock. -Clarified qcom,vdd-apc-step-up-limit description. -Added missing properties. -Updated the example. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring --- .../bindings/power/avs/qcom,cpr.txt | 193 ++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..93be67fa8f38 --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,193 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: + Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 + +- reg: + Usage: required + Value type: + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: + Definition: should specify the CPR interrupt + +- clocks: + Usage: required + Value type: + Definition: phandle to the reference clock + +- clock-names: + Usage: required + Value type: + Definition: must be "ref" + +- vdd-apc-supply: + Usage: required + Value type: + Definition: phandle to the vdd-apc-supply regulator + +- #power-domain-cells: + Usage: required + Value type: + Definition: should be 0 + +- operating-points-v2: + Usage: required + Value type: + Definition: A phandle to the OPP table containing the + performance states supported by the CPR + power domain + +- acc-syscon: + Usage: optional + Value type: + Definition: phandle to syscon for writing ACC settings + +- nvmem-cells: + Usage: required + Value type: + Definition: phandle to nvmem cells containing the data + that makes up a fuse corner, for each fuse corner. + As well as the CPR fuse revision. + +- nvmem-cell-names: + Usage: required + Value type: + Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", + "cpr_quotient_offset3", "cpr_init_voltage1", + "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", + "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", + "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" + for qcs404. + +- qcom,cpr-timer-delay-us: + Usage: required + Value type: + Definition: delay in uS for the timer interval + +- qcom,cpr-timer-cons-up: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing an up + interrupt + +- qcom,cpr-timer-cons-down: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing a down + interrupt + +- qcom,cpr-up-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping up + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping down + +- qcom,cpr-idle-clocks: + Usage: optional + Value type: + Definition: Idle clock cycles ring oscillator can be in + +- qcom,cpr-gcnt-us: + Usage: required + Value type: + Definition: The time for gate count in uS + +- qcom,vdd-apc-step-up-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling up + +- qcom,vdd-apc-step-down-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling down + +Example: + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + .... + }; + cpr_opp2: opp2 { + opp-level = <2>; + .... + }; + cpr_opp3: opp3 { + opp-level = <3>; + .... + }; + }; + + cpr@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + + qcom,cpr-timer-delay-us = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <3>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-us = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + };