From patchwork Mon Jul 1 18:44:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1125563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504120-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45cxBH72sYz9s8m for ; Tue, 2 Jul 2019 04:44:48 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=sGjxhv6YUSH7dxnFb/Nlf2Y0Pf2+a6j+n3vFbCRLAbQnvx 0xWJVl0V37bkWgVC0S1/6c4ykqSUgHIPRYh0Jdal3Uc07iXwYen9Fepxwkcsq9YM 3ZS6jDQjJhcnzWx6jGnH/wUrLY9VfGs2WWfD18PxBEmfnCR1eHiwv0ajJRuF8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=V8y+v1cymGDftC+cQ0vxKTNme2w=; b=VFZtsld82WgBT98Jpymc Ve11JhVO38nucidIF5KVkO2TZbOy76T6EdovHWBi84HpLldnvOCwsjJWDIise60g xlUp9NDzUs6qdYUyArIsopqLW0HAhvhljxncoPPpYlLAc6WiCWGoUOdpELOmYDLd qJxAosrSzkCmRhJKkHZA16c= Received: (qmail 54228 invoked by alias); 1 Jul 2019 18:44:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 54220 invoked by uid 89); 1 Jul 2019 18:44:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-io1-f41.google.com Received: from mail-io1-f41.google.com (HELO mail-io1-f41.google.com) (209.85.166.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Jul 2019 18:44:40 +0000 Received: by mail-io1-f41.google.com with SMTP id w25so31098467ioc.8 for ; Mon, 01 Jul 2019 11:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=QL8cXhYZdxcs1bmUhFy/prwZgO9JcYYC+teCYL+0dWg=; b=Gob6GefDtHcNEk1G8sa1aw0cpZ4p5MGmNO/3q9xVqCo54vIxiDVOy0meIA7LiiMO75 K+Hk2sWxvC284AsvZESjrJGNi/Xy0BNCsJxT3ndCT0d/D5pFxKA4N4x6v22feYrM6d6g 0Ii+etaLFU9aSraDtzsmVpp+neEXjtMgkwrAXAn2dN7EUx1/Kgs0B0iyhpM7U9h18xvd DjI7hN/Cglx4C0SaD0/v4OPhvNj/UjodtRmrgp/RvvVxKClvPBa0ZNIzDWrentc9y7Hs VQRrjGK2o3E0oTOxIYo4lngevCRCbDPm6ePSnRD8Qn9ogkLLxApmwuNE5+exMZBivtT7 VRaQ== MIME-Version: 1.0 From: Uros Bizjak Date: Mon, 1 Jul 2019 20:44:27 +0200 Message-ID: Subject: [PATCH, i386]: Also use and split insns with SSE operands for 32bit MMX targets To: "gcc-patches@gcc.gnu.org" Attached patch uses and splits a couple of instructions with SSE operands for 32bit MMX targets. 2019-07-01 Uroš Bizjak * config/i386/i386.md ("isa" attribute): Add sse_noavx. ("enabled" attribute): Handle sse_noavx isa attribute. * config/i386/mmx.md (*vec_dupv2sf): Add "isa" attribute. Use TARGET_SSE && SSE_REGNO_P in split condition. (*vec_dupv2sf): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c362a72411a2..c401deb5eb00 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -794,7 +794,7 @@ ;; Used to control the "enabled" attribute on a per-instruction basis. (define_attr "isa" "base,x64,x64_sse2,x64_sse4,x64_sse4_noavx,x64_avx,nox64, - sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, + sse_noavx,sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, avx512bw,noavx512bw,avx512dq,noavx512dq, avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw" @@ -820,6 +820,8 @@ (symbol_ref "TARGET_64BIT && TARGET_AVX512BW") (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT") (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2") + (eq_attr "isa" "sse_noavx") + (symbol_ref "TARGET_SSE && !TARGET_AVX") (eq_attr "isa" "sse2_noavx") (symbol_ref "TARGET_SSE2 && !TARGET_AVX") (eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3") diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 70413349390c..9ff86ba0eecc 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -590,12 +590,16 @@ punpckldq\t%0, %0 # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(set (match_dup 0) (vec_duplicate:V4SF (match_dup 1)))] - "operands[0] = lowpart_subreg (V4SFmode, operands[0], - GET_MODE (operands[0]));" - [(set_attr "mmx_isa" "native,sse_noavx,avx") +{ + operands[0] = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); +} + [(set_attr "isa" "*,sse_noavx,avx") + (set_attr "mmx_isa" "native,*,*") (set_attr "type" "mmxcvt,ssemov,ssemov") (set_attr "mode" "DI,TI,TI")]) @@ -1560,12 +1564,16 @@ # # #" - "TARGET_MMX_WITH_SSE && reload_completed" + "TARGET_SSE && reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" [(set (match_dup 0) (vec_duplicate:V4SI (match_dup 1)))] - "operands[0] = lowpart_subreg (V4SImode, operands[0], - GET_MODE (operands[0]));" - [(set_attr "mmx_isa" "native,sse_noavx,avx,avx") +{ + operands[0] = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); +} + [(set_attr "isa" "*,sse_noavx,avx,avx") + (set_attr "mmx_isa" "native,*,*,*") (set_attr "type" "mmxcvt,ssemov,ssemov,ssemov") (set_attr "mode" "DI,TI,TI,TI")])