From patchwork Mon Jun 24 14:52:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ren=C3=A9_van_Dorst?= X-Patchwork-Id: 1121368 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=vdorst.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=vdorst.com header.i=@vdorst.com header.b="GJtV9xSq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45XXND692qz9s4Y for ; Tue, 25 Jun 2019 00:53:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729044AbfFXOxQ (ORCPT ); Mon, 24 Jun 2019 10:53:16 -0400 Received: from mx.0dd.nl ([5.2.79.48]:33466 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbfFXOxQ (ORCPT ); Mon, 24 Jun 2019 10:53:16 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 716AE5FAF1; Mon, 24 Jun 2019 16:53:13 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="GJtV9xSq"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 39F131CC6F02; Mon, 24 Jun 2019 16:53:13 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 39F131CC6F02 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1561387993; bh=ntWgRRFlEq74/wAxR4H5vmKgfUgKV2R2TR8EFS2knZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GJtV9xSq5TWbzBPby9kcGLiQan+Oux2wVD+O029i8Azb1b0jjj+qO+2H3LwBsdIBS +9nEV06p6Hvs5pbIxf0Jxxr6YZ/0swVAt/76lVqTBmN2vfTzsteHJV1usROUCDShIz BvJqQSmb0pjB+V2vjH8yh1qgT8JfMnj//hcRJD9fPfjhPFnAwH9m1WfPDaJzxRbp77 zDmGWhq3joBb/yP+UjwIgClM/5MrxOJcL2bQYLsiVYpsgPTObN/CZPnMO/VbCZTTB6 Ud2S4d9MfGFRYQCqpxOEP5evtZCURTgXSUMpEMgtwoqPBGSi0Sappe/WdC2pfcIpRn uMr1yUu5nQNmQ== From: =?utf-8?q?Ren=C3=A9_van_Dorst?= To: sean.wang@mediatek.com, f.fainelli@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, matthias.bgg@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com Cc: frank-w@public-files.de, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [PATCH RFC net-next 1/5] net: dsa: mt7530: Convert to PHYLINK API Date: Mon, 24 Jun 2019 16:52:47 +0200 Message-Id: <20190624145251.4849-2-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190624145251.4849-1-opensource@vdorst.com> References: <20190624145251.4849-1-opensource@vdorst.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Convert mt7530 to PHYLINK API Signed-off-by: René van Dorst --- drivers/net/dsa/mt7530.c | 237 +++++++++++++++++++++++++++++---------- drivers/net/dsa/mt7530.h | 9 ++ 2 files changed, 187 insertions(+), 59 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 3181e95586d6..9c5e4dd00826 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -633,63 +633,6 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) return ARRAY_SIZE(mt7530_mib); } -static void mt7530_adjust_link(struct dsa_switch *ds, int port, - struct phy_device *phydev) -{ - struct mt7530_priv *priv = ds->priv; - - if (phy_is_pseudo_fixed_link(phydev)) { - dev_dbg(priv->dev, "phy-mode for master device = %x\n", - phydev->interface); - - /* Setup TX circuit incluing relevant PAD and driving */ - mt7530_pad_clk_setup(ds, phydev->interface); - - if (priv->id == ID_MT7530) { - /* Setup RX circuit, relevant PAD and driving on the - * host which must be placed after the setup on the - * device side is all finished. - */ - mt7623_pad_clk_setup(ds); - } - } else { - u16 lcl_adv = 0, rmt_adv = 0; - u8 flowctrl; - u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; - - switch (phydev->speed) { - case SPEED_1000: - mcr |= PMCR_FORCE_SPEED_1000; - break; - case SPEED_100: - mcr |= PMCR_FORCE_SPEED_100; - break; - } - - if (phydev->link) - mcr |= PMCR_FORCE_LNK; - - if (phydev->duplex) { - mcr |= PMCR_FORCE_FDX; - - if (phydev->pause) - rmt_adv = LPA_PAUSE_CAP; - if (phydev->asym_pause) - rmt_adv |= LPA_PAUSE_ASYM; - - lcl_adv = linkmode_adv_to_lcl_adv_t( - phydev->advertising); - flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); - - if (flowctrl & FLOW_CTRL_TX) - mcr |= PMCR_TX_FC_EN; - if (flowctrl & FLOW_CTRL_RX) - mcr |= PMCR_RX_FC_EN; - } - mt7530_write(priv, MT7530_PMCR_P(port), mcr); - } -} - static int mt7530_cpu_port_enable(struct mt7530_priv *priv, int port) @@ -1323,6 +1266,178 @@ mt7530_setup(struct dsa_switch *ds) return 0; } +static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct mt7530_priv *priv = ds->priv; + u32 mcr = PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | + PMCR_BACKPR_EN | PMCR_TX_EN | PMCR_RX_EN; + + switch (port) { + case 0: /* Internal phy */ + case 1: + case 2: + case 3: + case 4: + if (state->interface != PHY_INTERFACE_MODE_GMII) + goto unsupported; + break; + /* case 5: Port 5 is not supported! */ + case 6: /* 1st cpu port */ + if (state->interface != PHY_INTERFACE_MODE_RGMII && + state->interface != PHY_INTERFACE_MODE_TRGMII) + goto unsupported; + + /* Setup TX circuit incluing relevant PAD and driving */ + mt7530_pad_clk_setup(ds, state->interface); + + if (priv->id == ID_MT7530) { + /* Setup RX circuit, relevant PAD and driving on the + * host which must be placed after the setup on the + * device side is all finished. + */ + mt7623_pad_clk_setup(ds); + } + break; + default: + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); + return; + } + + if (!state->an_enabled || mode == MLO_AN_FIXED) { + mcr |= PMCR_FORCE_MODE; + + if (state->speed == SPEED_1000) + mcr |= PMCR_FORCE_SPEED_1000; + if (state->speed == SPEED_100) + mcr |= PMCR_FORCE_SPEED_100; + if (state->duplex == DUPLEX_FULL) + mcr |= PMCR_FORCE_FDX; + if (state->link || mode == MLO_AN_FIXED) + mcr |= PMCR_FORCE_LNK; + if (state->pause || phylink_test(state->advertising, Pause)) + mcr |= PMCR_TX_FC_EN | PMCR_RX_FC_EN; + if (state->pause & MLO_PAUSE_TX) + mcr |= PMCR_TX_FC_EN; + if (state->pause & MLO_PAUSE_RX) + mcr |= PMCR_RX_FC_EN; + } + + mt7530_write(priv, MT7530_PMCR_P(port), mcr); + + return; + +unsupported: + dev_err(ds->dev, "%s: P%d: Unsupported phy_interface mode: %d (%s)\n", + __func__, port, state->interface, phy_modes(state->interface)); +} + +static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + /* Do nothing */ +} + +static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev) +{ + /* Do nothing */ +} + +static void mt7530_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + switch (port) { + case 0: /* Internal phy */ + case 1: + case 2: + case 3: + case 4: + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != PHY_INTERFACE_MODE_GMII) + goto unsupported; + break; + /* case 5: Port 5 not supported! */ + case 6: /* 1st cpu port */ + if (state->interface != PHY_INTERFACE_MODE_RGMII && + state->interface != PHY_INTERFACE_MODE_TRGMII) + goto unsupported; + break; + default: + linkmode_zero(supported); + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); + return; + } + + phylink_set(mask, Autoneg); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + phylink_set(mask, MII); + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); + return; + +unsupported: + linkmode_zero(supported); + dev_err(ds->dev, "%s: unsupported interface mode: [0x%x] %s\n", + __func__, state->interface, phy_modes(state->interface)); +} + +static int +mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, + struct phylink_link_state *state) +{ + struct mt7530_priv *priv = ds->priv; + u32 pmsr; + + if (port < 0 || port >= MT7530_NUM_PORTS) + return -EINVAL; + + pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); + + state->link = (pmsr & PMSR_LINK); + state->an_complete = state->link; + state->duplex = (pmsr & PMSR_DPX) >> 1; + + switch (pmsr & (PMSR_SPEED_1000 | PMSR_SPEED_100)) { + case 0: + state->speed = SPEED_10; + break; + case PMSR_SPEED_100: + state->speed = SPEED_100; + break; + case PMSR_SPEED_1000: + state->speed = SPEED_1000; + break; + default: + state->speed = SPEED_UNKNOWN; + break; + } + + state->pause = 0; + if (pmsr & PMSR_RX_FC) + state->pause |= MLO_PAUSE_RX; + if (pmsr & PMSR_TX_FC) + state->pause |= MLO_PAUSE_TX; + + return 1; +} + static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt7530_setup, @@ -1331,7 +1446,6 @@ static const struct dsa_switch_ops mt7530_switch_ops = { .phy_write = mt7530_phy_write, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, - .adjust_link = mt7530_adjust_link, .port_enable = mt7530_port_enable, .port_disable = mt7530_port_disable, .port_stp_state_set = mt7530_stp_state_set, @@ -1344,6 +1458,11 @@ static const struct dsa_switch_ops mt7530_switch_ops = { .port_vlan_prepare = mt7530_port_vlan_prepare, .port_vlan_add = mt7530_port_vlan_add, .port_vlan_del = mt7530_port_vlan_del, + .phylink_validate = mt7530_phylink_validate, + .phylink_mac_link_state = mt7530_phylink_mac_link_state, + .phylink_mac_config = mt7530_phylink_mac_config, + .phylink_mac_link_down = mt7530_phylink_mac_link_down, + .phylink_mac_link_up = mt7530_phylink_mac_link_up, }; static const struct of_device_id mt7530_of_match[] = { diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index bfac90f48102..41d9a132ac70 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -198,6 +198,7 @@ enum mt7530_vlan_port_attr { #define PMCR_FORCE_SPEED_100 BIT(2) #define PMCR_FORCE_FDX BIT(1) #define PMCR_FORCE_LNK BIT(0) +#define PMCR_FORCE_LNK_DOWN PMCR_FORCE_MODE #define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ PMCR_TX_EN | PMCR_RX_EN | \ @@ -218,6 +219,14 @@ enum mt7530_vlan_port_attr { PMCR_TX_FC_EN | PMCR_RX_FC_EN) #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) +#define PMSR_EEE1G BIT(7) +#define PMSR_EEE100M BIT(6) +#define PMSR_RX_FC BIT(5) +#define PMSR_TX_FC BIT(4) +#define PMSR_SPEED_1000 BIT(3) +#define PMSR_SPEED_100 BIT(2) +#define PMSR_DPX BIT(1) +#define PMSR_LINK BIT(0) /* Register for MIB */ #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) From patchwork Mon Jun 24 14:52:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ren=C3=A9_van_Dorst?= X-Patchwork-Id: 1121369 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=vdorst.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=vdorst.com header.i=@vdorst.com header.b="GL9iPASw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45XXNM3C8bz9s6w for ; Tue, 25 Jun 2019 00:53:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729222AbfFXOxW (ORCPT ); Mon, 24 Jun 2019 10:53:22 -0400 Received: from mx.0dd.nl ([5.2.79.48]:33492 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbfFXOxW (ORCPT ); Mon, 24 Jun 2019 10:53:22 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 775D55FEAA; Mon, 24 Jun 2019 16:53:19 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="GL9iPASw"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 41A5D1CC6F11; Mon, 24 Jun 2019 16:53:19 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 41A5D1CC6F11 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1561387999; bh=XQGc2L2tciEqhY0p8FDpM7GmACEvSx7FvJD+Y7Cy7oM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GL9iPASwY4YHDdgaltRtMfUc6NFKBnvaQ5z3/gDvHCuSnGsy4+jwDeJ2KY9nlBBoq alpgYLUVqQ6nCUatu4CYCL60Wdmn/8mbM4C26pUq7zkkn/rtj6emfqct2h8gB1jABw GnaiNDAaSNY0hk66FWFPjV25D7fEyqFJzcnc2cnuMEqmEKF2mGQMxjmcZ6aR7PKRso l5MLyGHChYBUbqMVHMk9Ycf2Ydh44Kef6/j40NNYXcuwLvxKrHiOUiY0bjy1qr0tfs iRW6HLLgdl3aF4uln2yzFDMIbCNNVub9cxWwIl6KU8gdQEr4Usi4ier7ss4ypkCt0M Uk/Qisf3oyRDQ== From: =?utf-8?q?Ren=C3=A9_van_Dorst?= To: sean.wang@mediatek.com, f.fainelli@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, matthias.bgg@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com Cc: frank-w@public-files.de, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, =?utf-8?q?Ren=C3=A9_van_Dorst?= , devicetree@vger.kernel.org Subject: [PATCH RFC net-next 2/5] dt-bindings: net: dsa: mt7530: Add support for port 5 Date: Mon, 24 Jun 2019 16:52:48 +0200 Message-Id: <20190624145251.4849-3-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190624145251.4849-1-opensource@vdorst.com> References: <20190624145251.4849-1-opensource@vdorst.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org MT7530 port 5 has many modes/configurations. Update the documentation how to use port 5. Signed-off-by: René van Dorst CC: devicetree@vger.kernel.org --- .../devicetree/bindings/net/dsa/mt7530.txt | 215 ++++++++++++++++++ 1 file changed, 215 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt index 47aa205ee0bd..f3486780f2c2 100644 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt @@ -35,6 +35,39 @@ Required properties for the child nodes within ports container: - phy-mode: String, must be either "trgmii" or "rgmii" for port labeled "cpu". +Port 5 of the switch is muxed between: +1. GMAC5: GMAC5 can interface with another external MAC or PHY. +2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC + of the SOC. Used in many setups where port 0/4 becomes the WAN port. + +Port 5 modes/configurations: +1. Port 5 is disabled and isolated: An external phy can interface to the 2nd + GMAC of the SOC. + In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd + GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! +2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. + It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode + and RGMII delay. +3. Port 5 is muxed to GMAC5 and can interface to an external phy. + Port 5 becomes an extra switch port. + Only works on platform where external phy TX<->RX lines are swapped. + Like in the Ubiquiti ER-X-SFP. +4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. + Currently a 2nd CPU port is not supported by DSA code. + +Depending on how the external PHY is wired: +1. normal: The PHY can only connect to 2nd GMAC but not to the switch +2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as + a ethernet port. But can't interface to the 2nd GMAC. + +Based on the DT the port 5 mode is configured. + +Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. +When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. +phy-mode must be set, see also example 2 below! + * mt7621: phy-mode = "rgmii-txid"; + * mt7623: phy-mode = "rgmii"; + See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional required, optional properties and how the integrated switch subnodes must be specified. @@ -94,3 +127,185 @@ Example: }; }; }; + +Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii-txid"; + phy-handle = <&phy4>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* Internal phy */ + phy4: ethernet-phy@4 { + reg = <4>; + }; + + mt7530: switch@1f { + compatible = "mediatek,mt7621"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1f>; + pinctrl-names = "default"; + mediatek,mcm; + + resets = <&rstctrl 2>; + reset-names = "mcm"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + +/* Commented out. Port 4 is handled by 2nd GMAC. + port@4 { + reg = <4>; + label = "lan4"; + }; +*/ + + cpu_port0: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* External phy */ + ephy5: ethernet-phy@7 { + reg = <7>; + }; + + mt7530: switch@1f { + compatible = "mediatek,mt7621"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1f>; + pinctrl-names = "default"; + mediatek,mcm; + + resets = <&rstctrl 2>; + reset-names = "mcm"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan5"; + phy-mode = "rgmii"; + phy-handle = <&ephy5>; + }; + + cpu_port0: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; From patchwork Mon Jun 24 14:52:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ren=C3=A9_van_Dorst?= X-Patchwork-Id: 1121371 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=vdorst.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=vdorst.com header.i=@vdorst.com header.b="ap3bsTdE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45XXNX1BBLz9s6w for ; Tue, 25 Jun 2019 00:53:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729495AbfFXOxb (ORCPT ); Mon, 24 Jun 2019 10:53:31 -0400 Received: from mx.0dd.nl ([5.2.79.48]:33532 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbfFXOxb (ORCPT ); Mon, 24 Jun 2019 10:53:31 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 2F1965FEAA; Mon, 24 Jun 2019 16:53:28 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="ap3bsTdE"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id ED9D11CC6F19; Mon, 24 Jun 2019 16:53:27 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com ED9D11CC6F19 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1561388008; bh=inaANzeGYZ3EgYB3duDullrdCzEiKUVwyGOseNfS7s0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ap3bsTdEAExFgwd28a/2Ei5ujPioBtPz7GbITjiNFpvN8ANMKdeOyom6Lrl5H+qad IUXB7QwPwrmAQQd6WVMFQuWPA9GM4e0C8KqVbMdo2YE0K2fG4ghHlXh46kl1fg8WBG qrKcC9Cb0C4aD2/3nv7cV639hfQAQJwQdNFmNMa+RdDENL5eqV31SNp+O3HNNbjg+k xw10bNKteewYxO/PNAPwyLH0K4CBhdP5NbEJ+Oi4rUydphcHrCK3u451Vpv7blb5Ft qyEG1UMHMtXF2wN+6YC82zXvTYqiA7fos1/6pCm5oclbA6sSR0GX8C3aDm5KFTTBkn PF2y0axaSgNFg== From: =?utf-8?q?Ren=C3=A9_van_Dorst?= To: sean.wang@mediatek.com, f.fainelli@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, matthias.bgg@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com Cc: frank-w@public-files.de, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [PATCH RFC net-next 3/5] net: dsa: mt7530: Add support for port 5 Date: Mon, 24 Jun 2019 16:52:49 +0200 Message-Id: <20190624145251.4849-4-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190624145251.4849-1-opensource@vdorst.com> References: <20190624145251.4849-1-opensource@vdorst.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Adding support for port 5. Port 5 ca muxed/interface to: - internal 5th GMAC of the switch; can be used as 2nd CPU port or as extra port with an external phy for a 6th ethernet port. - internal PHY of port 0 or 4; Used in most applications so that port 0 or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC. Signed-off-by: René van Dorst --- drivers/net/dsa/mt7530.c | 135 +++++++++++++++++++++++++++++++++++++-- drivers/net/dsa/mt7530.h | 28 ++++++++ 2 files changed, 159 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9c5e4dd00826..838a921ca83e 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -633,6 +633,74 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) return ARRAY_SIZE(mt7530_mib); } +static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) +{ + struct mt7530_priv *priv = ds->priv; + u8 tx_delay = 0; + int val; + + mutex_lock(&priv->reg_mutex); + + val = mt7530_read(priv, MT7530_MHWTRAP); + + val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; + + switch (priv->p5_mode) { + case P5_MODE_GPHY_P0: + /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ + val |= MHWTRAP_PHY0_SEL; + /* fall through */ + case P5_MODE_GPHY_P4: + /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ + val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + + /* Setup the MAC by default for the cpu port */ + mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); + break; + case P5_MODE_GMAC: + /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ + val &= ~MHWTRAP_P5_DIS; + break; + case P5_MODE_DISABLED: + interface = PHY_INTERFACE_MODE_NA; + break; + default: + dev_err(ds->dev, "Unsupported p5_mode %d\n", priv->p5_mode); + goto unlock_exit; + } + + /* Setup RGMII settings */ + if (phy_interface_mode_is_rgmii(interface)) { + val |= MHWTRAP_P5_RGMII_MODE; + + /* P5 RGMII RX Clock Control: delay setting for 1000M */ + mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); + + /* Don't set delay in DSA mode */ + if (!dsa_is_dsa_port(priv->ds, 5) && + (interface == PHY_INTERFACE_MODE_RGMII_TXID || + interface == PHY_INTERFACE_MODE_RGMII_ID)) + tx_delay = 4; /* n * 0.5 ns */ + + /* P5 RGMII TX Clock Control: delay x */ + mt7530_write(priv, MT7530_P5RGMIITXCR, + CSR_RGMII_TXC_CFG(0x10 + tx_delay)); + + /* reduce P5 RGMII Tx driving, 8mA */ + mt7530_write(priv, MT7530_IO_DRV_CR, + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + } + + mt7530_write(priv, MT7530_MHWTRAP, val); + + dev_info(ds->dev, "Setup P5, HWTRAP=0x%x, port-mode=%s, phy-mode=%s\n", + val, p5_modes(priv->p5_mode), phy_modes(interface)); + +unlock_exit: + mutex_unlock(&priv->reg_mutex); +} + static int mt7530_cpu_port_enable(struct mt7530_priv *priv, int port) @@ -1173,6 +1241,10 @@ mt7530_setup(struct dsa_switch *ds) u32 id, val; struct device_node *dn; struct mt7530_dummy_poll p; + phy_interface_t interface; + struct device_node *mac_np; + struct device_node *phy_node; + const __be32 *_id; /* The parent node of master netdev which holds the common system * controller also is the container for two GMACs nodes representing @@ -1258,6 +1330,40 @@ mt7530_setup(struct dsa_switch *ds) mt7530_port_disable(ds, i); } + /* Setup port 5 */ + priv->p5_mode = P5_MODE_DISABLED; + interface = PHY_INTERFACE_MODE_NA; + + if (!dsa_is_unused_port(ds, 5)) { + priv->p5_mode = P5_MODE_GMAC; + interface = of_get_phy_mode(ds->ports[5].dn); + } else { + /* Scan the ethernet nodes. Look for GMAC1, Lookup used phy */ + for_each_child_of_node(dn, mac_np) { + if (!of_device_is_compatible(mac_np, + "mediatek,eth-mac")) + continue; + _id = of_get_property(mac_np, "reg", NULL); + if (be32_to_cpup(_id) != 1) + continue; + + interface = of_get_phy_mode(mac_np); + phy_node = of_parse_phandle(mac_np, "phy-handle", 0); + + if (phy_node->parent == priv->dev->of_node->parent) { + _id = of_get_property(phy_node, "reg", NULL); + id = be32_to_cpup(_id); + if (id == 0) + priv->p5_mode = P5_MODE_GPHY_P0; + if (id == 4) + priv->p5_mode = P5_MODE_GPHY_P4; + } + break; + } + } + + mt7530_setup_port5(ds, interface); + /* Flush the FDB table */ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) @@ -1283,7 +1389,20 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port, if (state->interface != PHY_INTERFACE_MODE_GMII) goto unsupported; break; - /* case 5: Port 5 is not supported! */ + case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_MII) + goto unsupported; + if (priv->p5_mode != P5_MODE_GMAC) { + priv->p5_mode = P5_MODE_GMAC; + mt7530_port_disable(ds, port); + mt7530_setup_port5(ds, state->interface); + mt7530_port_enable(ds, port, NULL); + } + /* We are connected to external phy */ + if (dsa_is_user_port(ds, 5)) + mcr |= PMCR_EXT_PHY; + break; case 6: /* 1st cpu port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_TRGMII) @@ -1364,7 +1483,12 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port, state->interface != PHY_INTERFACE_MODE_GMII) goto unsupported; break; - /* case 5: Port 5 not supported! */ + case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_NA) + goto unsupported; + break; case 6: /* 1st cpu port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && state->interface != PHY_INTERFACE_MODE_TRGMII) @@ -1385,8 +1509,11 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port, phylink_set(mask, 10baseT_Full); phylink_set(mask, 100baseT_Half); phylink_set(mask, 100baseT_Full); - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); + + if (state->interface != PHY_INTERFACE_MODE_MII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 41d9a132ac70..f2a84ef48548 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -186,6 +186,7 @@ enum mt7530_vlan_port_attr { /* Register for port MAC control register */ #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) +#define PMCR_EXT_PHY BIT(17) #define PMCR_MAC_MODE BIT(16) #define PMCR_FORCE_MODE BIT(15) #define PMCR_TX_EN BIT(14) @@ -260,6 +261,7 @@ enum mt7530_vlan_port_attr { /* Register for hw trap modification */ #define MT7530_MHWTRAP 0x7804 +#define MHWTRAP_PHY0_SEL BIT(20) #define MHWTRAP_MANUAL BIT(16) #define MHWTRAP_P5_MAC_SEL BIT(13) #define MHWTRAP_P6_DIS BIT(8) @@ -417,6 +419,30 @@ struct mt7530_port { u16 pvid; }; +/* Port 5 Mode definitions */ +enum p5_mode { + P5_MODE_DISABLED = 0, + P5_MODE_GPHY_P0, + P5_MODE_GPHY_P4, + P5_MODE_GMAC, +}; + +static const char *p5_modes(unsigned int p5_mode) +{ + switch (p5_mode) { + case P5_MODE_DISABLED: + return "DISABLED"; + case P5_MODE_GPHY_P0: + return "PHY P0"; + case P5_MODE_GPHY_P4: + return "PHY P4"; + case P5_MODE_GMAC: + return "GMAC"; + default: + return "unknown"; + } +} + /* struct mt7530_priv - This is the main data structure for holding the state * of the driver * @dev: The device pointer @@ -432,6 +458,7 @@ struct mt7530_port { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers + * @p5_mode: PORT 5 mode status */ struct mt7530_priv { struct device *dev; @@ -444,6 +471,7 @@ struct mt7530_priv { struct gpio_desc *reset; unsigned int id; bool mcm; + unsigned int p5_mode; struct mt7530_port ports[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ From patchwork Mon Jun 24 14:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ren=C3=A9_van_Dorst?= X-Patchwork-Id: 1121373 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=vdorst.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=vdorst.com header.i=@vdorst.com header.b="aHJxS3uu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45XXNc050zz9s4Y for ; Tue, 25 Jun 2019 00:53:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729760AbfFXOxf (ORCPT ); Mon, 24 Jun 2019 10:53:35 -0400 Received: from mx.0dd.nl ([5.2.79.48]:33562 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726414AbfFXOxe (ORCPT ); Mon, 24 Jun 2019 10:53:34 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 61D4A5FAF1; Mon, 24 Jun 2019 16:53:31 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="aHJxS3uu"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 2E4551CC6F1E; Mon, 24 Jun 2019 16:53:31 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 2E4551CC6F1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1561388011; bh=Rc7laVn7CqDBL7FM7QjwXQ1rHS2zM32M0Cm10zc19Gk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aHJxS3uu1+92MqYd/r/xagYnsN0+KSH5+4ViLZ/CmvCWR2ca8v/Apd26181O2MVA5 bV/qnuUxIF9s07xlB92277nGONGZ8q8Fu3xRLzJoceo8JeIZUzLfhs1sW6BYwIPyft sVlTE9wyHiJwr8/OD8XVR+HpHbxM2WMkytfHZA6VhUOU+ZxEIRzsUmU27CJLi3OU3s yL+9liUBUSxFMON6aGHhVH/iEDMzTd9bFjEsx5+Py/iierirZQY+eC0vLvnqsIcFCR cDaIFSwz/ACf8f9Hkn+79xlS/U8xQENIhm3AxEKXG405RxGcSw48kW6LouYbjfI8ZV +k1SPpC44mWHw== From: =?utf-8?q?Ren=C3=A9_van_Dorst?= To: sean.wang@mediatek.com, f.fainelli@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, matthias.bgg@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com Cc: frank-w@public-files.de, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [PATCH RFC net-next 4/5] dt-bindings: net: dsa: mt7530: Add mediatek, ephy-handle to isolate ext. phy Date: Mon, 24 Jun 2019 16:52:50 +0200 Message-Id: <20190624145251.4849-5-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190624145251.4849-1-opensource@vdorst.com> References: <20190624145251.4849-1-opensource@vdorst.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On some platforum the external phy can only interface to the port 5 of the switch because the RGMII TX and RX lines are swapped. But it still can be useful to use the internal phy of the switch to act as a WAN port which connectes to the 2nd GMAC. This gives WAN port dedicated bandwidth to the SOC. This increases the LAN and WAN routing. By adding the optional property mediatek,ephy-handle, the external phy is put in isolation mode when internal phy is connected to 2nd GMAC via phy-handle property. Signed-off-by: René van Dorst --- .../devicetree/bindings/net/dsa/mt7530.txt | 116 +++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt index f3486780f2c2..1e79fba5a774 100644 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt @@ -60,10 +60,20 @@ Depending on how the external PHY is wired: 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as a ethernet port. But can't interface to the 2nd GMAC. +Optional property: + +- mediatek,ephy-handle: Phandle of the external phy. In case you want to use + P0/4 as WAN port and have an external phy attached. + With this property the external phy is put in isolation + and powerdown mode in mode 2. + Based on the DT the port 5 mode is configured. Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. -When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. +When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2 and when +propertly "mediatek,ephy-handle" is valid it puts the externel phy in isolation +mode. + phy-mode must be set, see also example 2 below! * mt7621: phy-mode = "rgmii-txid"; * mt7623: phy-mode = "rgmii"; @@ -309,3 +319,107 @@ Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. }; }; }; + +Example 4: MT7621: Port 4 is WAN port: 2nd GMAC -> P5 -> PHY P4 + with an external phy. + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii-txid"; + phy-handle = <&phy4>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* Internal phy 4 */ + phy4: ethernet-phy@4 { + reg = <4>; + }; + + /* external phy addr 0x07 */ + ephy5: ethernet-phy@7 { + reg = <7>; + }; + + mt7530: switch@1f { + compatible = "mediatek,mt7621"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1f>; + pinctrl-names = "default"; + mediatek,mcm; + + /* Put this external phy in power-down and isolation + * when port 5 is used in PHY P0/P4 or DSA mode. Because + * external phy and port 5 share same bus to 2nd GMAC. + */ + mediatek,ephy-handle = <&ephy5>; + + resets = <&rstctrl 2>; + reset-names = "mcm"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + +/* Commented out. Port 4 is handled by 2nd GMAC. + port@4 { + reg = <4>; + label = "lan4"; + }; +*/ + + cpu_port0: port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; From patchwork Mon Jun 24 14:52:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ren=C3=A9_van_Dorst?= X-Patchwork-Id: 1121372 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=vdorst.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=vdorst.com header.i=@vdorst.com header.b="Z97OrP5c"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45XXNZ4phcz9s4Y for ; Tue, 25 Jun 2019 00:53:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729666AbfFXOxe (ORCPT ); Mon, 24 Jun 2019 10:53:34 -0400 Received: from mx.0dd.nl ([5.2.79.48]:33586 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729539AbfFXOxd (ORCPT ); Mon, 24 Jun 2019 10:53:33 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 88C895FEAA; Mon, 24 Jun 2019 16:53:31 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="Z97OrP5c"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 4BAB41CC6F20; Mon, 24 Jun 2019 16:53:31 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 4BAB41CC6F20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1561388011; bh=o1+uw8+JtKHBlTBA6PNZjG1cJU17dwIWI/clg9n7HZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z97OrP5cGmQX9952lOXduXvxBEa8mKL3zNXH/prknAEZgxU7TxHAkKWBjfD2AOFRs JgOSZW8l0lzWzb7mcAW8G29OKHfm12FYROoygcYQAImUFrLA2brWX6N8f3TZZ5gQHY 0f8KhGNnHx1Wrgp1UHT+yzApmejZpmpPbD7HZqv6W4gnLvmT8qp3U09zaIWEDMj0p5 jn+++VqeoezFH5Ttcqr6PQBc/ukG7UrSqccbuDuerqafROJTvXukRYVWuRoKJVxtSN xsYnhwAzcH2QTNoDevIkYC01TgllsQdqoiKQmsv5sAKm6ywfje2UhrpKPkNGOXZfMh vCjkLVw56pUqA== From: =?utf-8?q?Ren=C3=A9_van_Dorst?= To: sean.wang@mediatek.com, f.fainelli@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, matthias.bgg@gmail.com, andrew@lunn.ch, vivien.didelot@gmail.com Cc: frank-w@public-files.de, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, =?utf-8?q?Ren=C3=A9_van_Dorst?= Subject: [PATCH RFC net-next 5/5] net: dsa: mt7530: Add mediatek, ephy-handle to isolate external phy Date: Mon, 24 Jun 2019 16:52:51 +0200 Message-Id: <20190624145251.4849-6-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190624145251.4849-1-opensource@vdorst.com> References: <20190624145251.4849-1-opensource@vdorst.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On some platforms the external phy can only interface with the port 5 of the switch because the xMII TX and RX lines are swapped. But it still can be useful to use the internal phy of the switch to act as a WAN port which connectes to the 2nd GMAC. This gives the SOC a double the bandwidth between LAN and WAN. Because LAN and WAN don't share the same interface anymore. By adding an optional property mediatek,ephy-handle, the external phy is put in isolation mode when internal phy is linked with 2nd GMAC via phy-handle property. Signed-off-by: René van Dorst --- drivers/net/dsa/mt7530.c | 28 ++++++++++++++++++++++++++++ drivers/net/dsa/mt7530.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 838a921ca83e..25b0f35df75b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -633,6 +633,26 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) return ARRAY_SIZE(mt7530_mib); } +static int mt7530_isolate_ephy(struct dsa_switch *ds, + struct device_node *ephy_node) +{ + struct phy_device *phydev = of_phy_find_device(ephy_node); + int ret; + + if (!phydev) + return 0; + + ret = phy_modify(phydev, MII_BMCR, 0, (BMCR_ISOLATE | BMCR_PDOWN)); + if (ret) + dev_err(ds->dev, "Failed to put phy %s in isolation mode!\n", + ephy_node->full_name); + else + dev_info(ds->dev, "Phy %s in isolation mode!\n", + ephy_node->full_name); + + return ret; +} + static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; @@ -655,6 +675,10 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; + /* Isolate the external phy */ + if (priv->ephy_node) + if (mt7530_isolate_ephy(ds, priv->ephy_node) < 0) + goto unlock_exit; /* Setup the MAC by default for the cpu port */ mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); break; @@ -1330,6 +1354,10 @@ mt7530_setup(struct dsa_switch *ds) mt7530_port_disable(ds, i); } + /* Get external phy phandle */ + priv->ephy_node = of_parse_phandle(priv->dev->of_node, + "mediatek,ephy-handle", 0); + /* Setup port 5 */ priv->p5_mode = P5_MODE_DISABLED; interface = PHY_INTERFACE_MODE_NA; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index f2a84ef48548..eb079e81a8e8 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -459,6 +459,7 @@ static const char *p5_modes(unsigned int p5_mode) * @reg_mutex: The lock for protecting among process accessing * registers * @p5_mode: PORT 5 mode status + * @ephy_node: External phy of_node. */ struct mt7530_priv { struct device *dev; @@ -472,6 +473,7 @@ struct mt7530_priv { unsigned int id; bool mcm; unsigned int p5_mode; + struct device_node *ephy_node; struct mt7530_port ports[MT7530_NUM_PORTS]; /* protect among processes for registers access*/