From patchwork Sun Jun 23 09:17:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1120766 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="BOBJJhra"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="PIj07/yC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Wn096jkkz9sBb for ; Sun, 23 Jun 2019 19:18:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726481AbfFWJSN (ORCPT ); Sun, 23 Jun 2019 05:18:13 -0400 Received: from mx0a-0014ca01.pphosted.com ([208.84.65.235]:15302 "EHLO mx0a-0014ca01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726050AbfFWJSM (ORCPT ); Sun, 23 Jun 2019 05:18:12 -0400 Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5N9H8wD003477; Sun, 23 Jun 2019 02:17:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=proofpoint; bh=Zz0R3kN3GGrXIkiPvrUVgQphwkH/BrIDfu0S3R2jme4=; b=BOBJJhraOe4jFAF73zynV7QRiEjx3/63zRBoZDGM9h2D8oxiUnnILwpEXzUshB5IpefK LNXoY/pq4NhYolx9Bl8C5C1VxvMxeLNDmJ+Bc601/m/bOhTCvciEAyIAnFYmXERWyt6m 6bFhSG23JSyQxR4nMfv/8e/s73w/jVfRP/pTxdS80VNXdy2JPV6DGuNrIgBlj3kqo8dz z/6bEsbo9G86PTxRZrgcOFoyc/0gkkB/qbCkbvsg6flDXNm1yeHGZr16G39ekplKXwk6 JIGctXXn9PzfacTsbNi8ofqmTWDZ79FgGTJTNPIGZn8p7s8rhxsfTGhUjZm0KjiwGONg 2Q== Authentication-Results: cadence.com; spf=pass smtp.mailfrom=pthombar@cadence.com Received: from nam04-co1-obe.outbound.protection.outlook.com (mail-co1nam04lp2056.outbound.protection.outlook.com [104.47.45.56]) by mx0a-0014ca01.pphosted.com with ESMTP id 2t9gvs2na0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Jun 2019 02:17:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Zz0R3kN3GGrXIkiPvrUVgQphwkH/BrIDfu0S3R2jme4=; b=PIj07/yCwAUc7e4lZh+vUl4YIy+H66zo+uVQEgFeNzMcbPw/hz75jVz2XdAUNaKvPdetJTdB+6S0KBqPSFsGPRwZ0jDIvDE2YSCjSGVJohykhnp1j2UnmB1ybaE6bVDXBVLdaCQq55d2ZB8jMuIk1objuQz+nQ+RQWYUPS49buo= Received: from MN2PR07CA0023.namprd07.prod.outlook.com (2603:10b6:208:1a0::33) by DM6PR07MB6971.namprd07.prod.outlook.com (2603:10b6:5:1eb::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.13; Sun, 23 Jun 2019 09:17:52 +0000 Received: from CO1NAM05FT035.eop-nam05.prod.protection.outlook.com (2a01:111:f400:7e50::209) by MN2PR07CA0023.outlook.office365.com (2603:10b6:208:1a0::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2008.16 via Frontend Transport; Sun, 23 Jun 2019 09:17:52 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning cadence.com discourages use of 158.140.1.28 as permitted sender) Received: from sjmaillnx2.cadence.com (158.140.1.28) by CO1NAM05FT035.mail.protection.outlook.com (10.152.96.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2032.6 via Frontend Transport; Sun, 23 Jun 2019 09:17:51 +0000 Received: from maileu3.global.cadence.com (maileu3.cadence.com [10.160.88.99]) by sjmaillnx2.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9Hkux010655 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Sun, 23 Jun 2019 02:17:47 -0700 X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 23 Jun 2019 11:17:45 +0200 Received: from lvlogina.cadence.com (10.165.176.102) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 23 Jun 2019 11:17:45 +0200 Received: from lvlogina.cadence.com (localhost.localdomain [127.0.0.1]) by lvlogina.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9HiCA007135; Sun, 23 Jun 2019 10:17:44 +0100 From: Parshuram Thombare To: , , , CC: , , , , , , , Subject: [PATCH v4 1/5] net: macb: add phylink support Date: Sun, 23 Jun 2019 10:17:37 +0100 Message-ID: <1561281457-6886-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1561281419-6030-1-git-send-email-pthombar@cadence.com> References: <1561281419-6030-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(346002)(396003)(136003)(376002)(39860400002)(2980300002)(199004)(189003)(36092001)(186003)(76176011)(48376002)(51416003)(316002)(77096007)(4326008)(47776003)(26005)(2906002)(11346002)(16586007)(426003)(107886003)(2616005)(5024004)(14444005)(476003)(7126003)(5660300002)(446003)(126002)(50226002)(50466002)(53416004)(336012)(305945005)(246002)(356004)(6666004)(110136005)(54906003)(7696005)(30864003)(478600001)(70586007)(86362001)(8936002)(26826003)(7636002)(486006)(36756003)(76130400001)(2201001)(8676002)(70206006); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR07MB6971; H:sjmaillnx2.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:corp.cadence.com; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0d57d1b2-ef66-44bd-ac7d-08d6f7bbab0b X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328); SRVR:DM6PR07MB6971; X-MS-TrafficTypeDiagnostic: DM6PR07MB6971: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:311; X-Forefront-PRVS: 00770C4423 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: ptvTISq6lqpleJhSqHBmNg+J7egOEDUNCRCZw8MubxCtZ3QTW4wpZKHnkCnaSB84Y/kNC9HGcMOvH/gSGkrjA8S2eISt6qqSWt8HJpGWjafksTgRMOexXaQ2FcBzMsJhe0+phNVRLVq6A3/4xmT4zRy/HtH9QFlHtW6hND2tqcnHFlM2+0sdaeQpdMOCVyp8Cc546zIJ4wUMpVM2m1EWa7EdrN+mt5IxngLfvvHaCEEBxc3euhHRLIO2TUyhVcfekkk0GDQuaxpn1CEzDM6EWeNuJsRyE9q/DEOxr1Iyd+reJ7NQG4FT/edQhtoQxr4XRtEj++B/e8kZFMmzQebJJIKeeSGRf/RCMmRuXWcxdHcQJnHsRIFalOPjU4CRaUk9wAoOPHvCC6VPqsW1kKTlNeFqJoYH3IDni/jDghZxUvY= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2019 09:17:51.7135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d57d1b2-ef66-44bd-ac7d-08d6f7bbab0b X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.28]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6971 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-23_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906230082 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch replace phylib API's by phylink API's. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/Kconfig | 2 +- drivers/net/ethernet/cadence/macb.h | 3 + drivers/net/ethernet/cadence/macb_main.c | 304 ++++++++++++----------- 3 files changed, 166 insertions(+), 143 deletions(-) diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig index 1766697c9c5a..d71411a71587 100644 --- a/drivers/net/ethernet/cadence/Kconfig +++ b/drivers/net/ethernet/cadence/Kconfig @@ -22,7 +22,7 @@ if NET_VENDOR_CADENCE config MACB tristate "Cadence MACB/GEM support" depends on HAS_DMA - select PHYLIB + select PHYLINK ---help--- The Cadence MACB ethernet interface is found on many Atmel AT32 and AT91 parts. This driver also supports the Cadence GEM (Gigabit diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 6ff123da6a14..8629d345af31 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -11,6 +11,7 @@ #include #include #include +#include #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) #define MACB_EXT_DESC @@ -1224,6 +1225,8 @@ struct macb { u32 rx_intr_mask; struct macb_pm_data pm_data; + struct phylink *pl; + struct phylink_config pl_config; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index b4fa0111cd7a..1d6527a5313f 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "macb.h" /* This structure is only used for MACB on SiFive FU540 devices */ @@ -435,115 +436,145 @@ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) netdev_err(dev, "adjusting tx_clk failed.\n"); } -static void macb_handle_link_change(struct net_device *dev) +static void gem_phylink_validate(struct phylink_config *pl_config, + unsigned long *supported, + struct phylink_link_state *state) { - struct macb *bp = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - unsigned long flags; - int status_change = 0; + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + switch (state->interface) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) { + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Half); + } + } + /* fallthrough */ + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + break; + default: + break; + } - spin_lock_irqsave(&bp->lock, flags); + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); - if (phydev->link) { - if ((bp->speed != phydev->speed) || - (bp->duplex != phydev->duplex)) { - u32 reg; +} - reg = macb_readl(bp, NCFGR); - reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (macb_is_gem(bp)) - reg &= ~GEM_BIT(GBE); +static int gem_phylink_mac_link_state(struct phylink_config *pl_config, + struct phylink_link_state *state) +{ + return -EOPNOTSUPP; +} - if (phydev->duplex) - reg |= MACB_BIT(FD); - if (phydev->speed == SPEED_100) - reg |= MACB_BIT(SPD); - if (phydev->speed == SPEED_1000 && - bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) - reg |= GEM_BIT(GBE); +static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, + const struct phylink_link_state *state) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + unsigned long flags; - macb_or_gem_writel(bp, NCFGR, reg); + spin_lock_irqsave(&bp->lock, flags); - bp->speed = phydev->speed; - bp->duplex = phydev->duplex; - status_change = 1; - } - } + if (!phylink_autoneg_inband(mode) && + (bp->speed != state->speed || + bp->duplex != state->duplex)) { + u32 reg; - if (phydev->link != bp->link) { - if (!phydev->link) { - bp->speed = 0; - bp->duplex = -1; + reg = macb_readl(bp, NCFGR); + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (macb_is_gem(bp)) + reg &= ~GEM_BIT(GBE); + if (state->duplex) + reg |= MACB_BIT(FD); + + switch (state->speed) { + case SPEED_1000: + reg |= GEM_BIT(GBE); + break; + case SPEED_100: + reg |= MACB_BIT(SPD); + break; + default: + break; } - bp->link = phydev->link; + macb_or_gem_writel(bp, NCFGR, reg); + + bp->speed = state->speed; + bp->duplex = state->duplex; - status_change = 1; + if (state->link) + macb_set_tx_clk(bp->tx_clk, state->speed, netdev); } spin_unlock_irqrestore(&bp->lock, flags); +} - if (status_change) { - if (phydev->link) { - /* Update the TX clock rate if and only if the link is - * up and there has been a link change. - */ - macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); +static void gem_mac_link_up(struct phylink_config *pl_config, unsigned int mode, + phy_interface_t interface, struct phy_device *phy) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); - netif_carrier_on(dev); - netdev_info(dev, "link up (%d/%s)\n", - phydev->speed, - phydev->duplex == DUPLEX_FULL ? - "Full" : "Half"); - } else { - netif_carrier_off(dev); - netdev_info(dev, "link down\n"); - } - } + bp->link = 1; + /* Enable TX and RX */ + macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); +} + +static void gem_mac_link_down(struct phylink_config *pl_config, + unsigned int mode, phy_interface_t interface) +{ + struct net_device *netdev = to_net_dev(pl_config->dev); + struct macb *bp = netdev_priv(netdev); + + bp->link = 0; + /* Disable TX and RX */ + macb_writel(bp, NCR, + macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE))); } +static const struct phylink_mac_ops gem_phylink_ops = { + .validate = gem_phylink_validate, + .mac_link_state = gem_phylink_mac_link_state, + .mac_config = gem_mac_config, + .mac_link_up = gem_mac_link_up, + .mac_link_down = gem_mac_link_down, +}; + /* based on au1000_eth. c*/ static int macb_mii_probe(struct net_device *dev) { struct macb *bp = netdev_priv(dev); struct phy_device *phydev; struct device_node *np; - int ret, i; + int ret; np = bp->pdev->dev.of_node; ret = 0; - if (np) { - if (of_phy_is_fixed_link(np)) { - bp->phy_node = of_node_get(np); - } else { - bp->phy_node = of_parse_phandle(np, "phy-handle", 0); - /* fallback to standard phy registration if no - * phy-handle was found nor any phy found during - * dt phy registration - */ - if (!bp->phy_node && !phy_find_first(bp->mii_bus)) { - for (i = 0; i < PHY_MAX_ADDR; i++) { - phydev = mdiobus_scan(bp->mii_bus, i); - if (IS_ERR(phydev) && - PTR_ERR(phydev) != -ENODEV) { - ret = PTR_ERR(phydev); - break; - } - } - - if (ret) - return -ENODEV; - } - } + bp->pl_config.dev = &dev->dev; + bp->pl_config.type = PHYLINK_NETDEV; + bp->pl = phylink_create(&bp->pl_config, of_fwnode_handle(np), + bp->phy_interface, &gem_phylink_ops); + if (IS_ERR(bp->pl)) { + netdev_err(dev, + "error creating PHYLINK: %ld\n", PTR_ERR(bp->pl)); + return PTR_ERR(bp->pl); } - if (bp->phy_node) { - phydev = of_phy_connect(dev, bp->phy_node, - &macb_handle_link_change, 0, - bp->phy_interface); - if (!phydev) - return -ENODEV; - } else { + ret = phylink_of_phy_connect(bp->pl, np, 0); + if (ret == -ENODEV && bp->mii_bus) { phydev = phy_find_first(bp->mii_bus); if (!phydev) { netdev_err(dev, "no PHY found\n"); @@ -551,29 +582,18 @@ static int macb_mii_probe(struct net_device *dev) } /* attach the mac to the phy */ - ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, - bp->phy_interface); + ret = phylink_connect_phy(bp->pl, phydev); if (ret) { netdev_err(dev, "Could not attach to PHY\n"); return ret; } } - /* mask with MAC supported features */ - if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) - phy_set_max_speed(phydev, SPEED_1000); - else - phy_set_max_speed(phydev, SPEED_100); - - if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF) - phy_remove_link_mode(phydev, - ETHTOOL_LINK_MODE_1000baseT_Half_BIT); - bp->link = 0; bp->speed = 0; bp->duplex = -1; - return 0; + return ret; } static int macb_mii_init(struct macb *bp) @@ -601,17 +621,7 @@ static int macb_mii_init(struct macb *bp) dev_set_drvdata(&bp->dev->dev, bp->mii_bus); np = bp->pdev->dev.of_node; - if (np && of_phy_is_fixed_link(np)) { - if (of_phy_register_fixed_link(np) < 0) { - dev_err(&bp->pdev->dev, - "broken fixed-link specification %pOF\n", np); - goto err_out_free_mdiobus; - } - - err = mdiobus_register(bp->mii_bus); - } else { - err = of_mdiobus_register(bp->mii_bus, np); - } + err = of_mdiobus_register(bp->mii_bus, np); if (err) goto err_out_free_fixed_link; @@ -627,7 +637,6 @@ static int macb_mii_init(struct macb *bp) err_out_free_fixed_link: if (np && of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); -err_out_free_mdiobus: of_node_put(bp->phy_node); mdiobus_free(bp->mii_bus); err_out: @@ -2418,12 +2427,6 @@ static int macb_open(struct net_device *dev) /* carrier starts down */ netif_carrier_off(dev); - /* if the phy is not yet register, retry later*/ - if (!dev->phydev) { - err = -EAGAIN; - goto pm_exit; - } - /* RX buffers initialization */ macb_init_rx_buffer_size(bp, bufsz); @@ -2441,7 +2444,7 @@ static int macb_open(struct net_device *dev) macb_init_hw(bp); /* schedule a link state check */ - phy_start(dev->phydev); + phylink_start(bp->pl); netif_tx_start_all_queues(dev); @@ -2468,8 +2471,7 @@ static int macb_close(struct net_device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_disable(&queue->napi); - if (dev->phydev) - phy_stop(dev->phydev); + phylink_stop(bp->pl); spin_lock_irqsave(&bp->lock, flags); macb_reset_hw(bp); @@ -3158,6 +3160,23 @@ static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) return ret; } +static int gem_ethtool_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct macb *bp = netdev_priv(netdev); + + return phylink_ethtool_ksettings_get(bp->pl, cmd); +} + +static int +gem_ethtool_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *cmd) +{ + struct macb *bp = netdev_priv(netdev); + + return phylink_ethtool_ksettings_set(bp->pl, cmd); +} + static const struct ethtool_ops macb_ethtool_ops = { .get_regs_len = macb_get_regs_len, .get_regs = macb_get_regs, @@ -3165,8 +3184,8 @@ static const struct ethtool_ops macb_ethtool_ops = { .get_ts_info = ethtool_op_get_ts_info, .get_wol = macb_get_wol, .set_wol = macb_set_wol, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_link_ksettings = gem_ethtool_get_link_ksettings, + .set_link_ksettings = gem_ethtool_set_link_ksettings, .get_ringparam = macb_get_ringparam, .set_ringparam = macb_set_ringparam, }; @@ -3179,8 +3198,8 @@ static const struct ethtool_ops gem_ethtool_ops = { .get_ethtool_stats = gem_get_ethtool_stats, .get_strings = gem_get_ethtool_strings, .get_sset_count = gem_get_sset_count, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_link_ksettings = gem_ethtool_get_link_ksettings, + .set_link_ksettings = gem_ethtool_set_link_ksettings, .get_ringparam = macb_get_ringparam, .set_ringparam = macb_set_ringparam, .get_rxnfc = gem_get_rxnfc, @@ -3189,17 +3208,13 @@ static const struct ethtool_ops gem_ethtool_ops = { static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { - struct phy_device *phydev = dev->phydev; struct macb *bp = netdev_priv(dev); if (!netif_running(dev)) return -EINVAL; - if (!phydev) - return -ENODEV; - if (!bp->ptp_info) - return phy_mii_ioctl(phydev, rq, cmd); + return phylink_mii_ioctl(bp->pl, rq, cmd); switch (cmd) { case SIOCSHWTSTAMP: @@ -3207,7 +3222,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) case SIOCGHWTSTAMP: return bp->ptp_info->get_hwtst(dev, rq); default: - return phy_mii_ioctl(phydev, rq, cmd); + return phylink_mii_ioctl(bp->pl, rq, cmd); } } @@ -3707,7 +3722,7 @@ static int at91ether_open(struct net_device *dev) MACB_BIT(HRESP)); /* schedule a link state check */ - phy_start(dev->phydev); + phylink_start(lp->pl); netif_start_queue(dev); @@ -4180,13 +4195,12 @@ static int macb_probe(struct platform_device *pdev) struct clk *tsu_clk = NULL; unsigned int queue_mask, num_queues; bool native_io; - struct phy_device *phydev; struct net_device *dev; struct resource *regs; void __iomem *mem; const char *mac; struct macb *bp; - int err, val; + int err, val, phy_mode; regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); mem = devm_ioremap_resource(&pdev->dev, regs); @@ -4307,12 +4321,12 @@ static int macb_probe(struct platform_device *pdev) macb_get_hwaddr(bp); } - err = of_get_phy_mode(np); - if (err < 0) + phy_mode = of_get_phy_mode(np); + if (phy_mode < 0) /* not found in DT, MII by default */ bp->phy_interface = PHY_INTERFACE_MODE_MII; else - bp->phy_interface = err; + bp->phy_interface = phy_mode; /* IP specific init */ err = init(pdev); @@ -4323,8 +4337,6 @@ static int macb_probe(struct platform_device *pdev) if (err) goto err_out_free_netdev; - phydev = dev->phydev; - netif_carrier_off(dev); err = register_netdev(dev); @@ -4336,8 +4348,6 @@ static int macb_probe(struct platform_device *pdev) tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task, (unsigned long)bp); - phy_attached_info(phydev); - netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), dev->base_addr, dev->irq, dev->dev_addr); @@ -4348,7 +4358,9 @@ static int macb_probe(struct platform_device *pdev) return 0; err_out_unregister_mdio: - phy_disconnect(dev->phydev); + rtnl_lock(); + phylink_disconnect_phy(bp->pl); + rtnl_unlock(); mdiobus_unregister(bp->mii_bus); of_node_put(bp->phy_node); if (np && of_phy_is_fixed_link(np)) @@ -4382,13 +4394,18 @@ static int macb_remove(struct platform_device *pdev) if (dev) { bp = netdev_priv(dev); - if (dev->phydev) - phy_disconnect(dev->phydev); + if (bp->pl) { + rtnl_lock(); + phylink_disconnect_phy(bp->pl); + rtnl_unlock(); + } mdiobus_unregister(bp->mii_bus); if (np && of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); dev->phydev = NULL; mdiobus_free(bp->mii_bus); + if (bp->pl) + phylink_destroy(bp->pl); unregister_netdev(dev); pm_runtime_disable(&pdev->dev); @@ -4431,8 +4448,9 @@ static int __maybe_unused macb_suspend(struct device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_disable(&queue->napi); - phy_stop(netdev->phydev); - phy_suspend(netdev->phydev); + phylink_stop(bp->pl); + if (netdev->phydev) + phy_suspend(netdev->phydev); spin_lock_irqsave(&bp->lock, flags); macb_reset_hw(bp); spin_unlock_irqrestore(&bp->lock, flags); @@ -4480,9 +4498,11 @@ static int __maybe_unused macb_resume(struct device *dev) for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) napi_enable(&queue->napi); - phy_resume(netdev->phydev); - phy_init_hw(netdev->phydev); - phy_start(netdev->phydev); + if (netdev->phydev) { + phy_resume(netdev->phydev); + phy_init_hw(netdev->phydev); + } + phylink_start(bp->pl); } bp->macbgem_ops.mog_init_rings(bp); From patchwork Sun Jun 23 09:23:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1120767 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="QVaKHnlx"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="Ft6YJFhu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Wn6970lnz9sBb for ; Sun, 23 Jun 2019 19:23:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726477AbfFWJXZ (ORCPT ); Sun, 23 Jun 2019 05:23:25 -0400 Received: from mx0b-0014ca01.pphosted.com ([208.86.201.193]:25178 "EHLO mx0a-0014ca01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726050AbfFWJXZ (ORCPT ); Sun, 23 Jun 2019 05:23:25 -0400 Received: from pps.filterd (m0042333.ppops.net [127.0.0.1]) by mx0b-0014ca01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5N9IfoX012134; Sun, 23 Jun 2019 02:23:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=proofpoint; bh=t3XQzEnaLKzOeV41HFcFt9k8uRQvmCY5jkBJ+JM3xtM=; b=QVaKHnlx9BSj/TmoWm67nW0OQhXXIcdmXrBYvl7R5vfWAWk4ogzWqPMq4GIqK20gZRIw FrH4ru6D+nDB7I6UPPoBJaTYkHV5vXA4/WOpshw8ZdnlOmvipiKn/ZzpEeShs/Y4Cb2d U/AVh1i2PGEEnWYXBCt3vtVxrt4GBCDm27nMh9bxqOvAnTuI1Auhwxl6g3QJgHByH4y6 dTglCh79QRjNELBz1WjX2eNOXC8OJtw63hdGACCjrYDVmj0eebaMgY41w8IdaY3EAfio KHo3kIdI8Q9Sy/Zr7qp4tOvHVfGFbpdOJyZuHSGboX3ADUx+u4QZyFkeFav8MHtsMLOx PQ== Authentication-Results: cadence.com; spf=pass smtp.mailfrom=pthombar@cadence.com Received: from nam04-co1-obe.outbound.protection.outlook.com (mail-co1nam04lp2058.outbound.protection.outlook.com [104.47.45.58]) by mx0b-0014ca01.pphosted.com with ESMTP id 2t9fwtjwdq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Jun 2019 02:23:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t3XQzEnaLKzOeV41HFcFt9k8uRQvmCY5jkBJ+JM3xtM=; b=Ft6YJFhurtfJN3+5c/LIqaXtAf6KLs06ZxnjfDfrghmK7FSK8pGfDjQsU9jymFZh0vRYybl99QW/dnvUQe6PLHlU+gEzGwYNM+B3WuqhqTb9izPFa3bv3hUJLKjzkQ0LjtEVctZLPnUcAwjK+XCyS9KZUoqt1btfGL8sNIRzqxo= Received: from DM5PR07CA0062.namprd07.prod.outlook.com (2603:10b6:4:ad::27) by DM6PR07MB6971.namprd07.prod.outlook.com (2603:10b6:5:1eb::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.13; Sun, 23 Jun 2019 09:23:11 +0000 Received: from DM3NAM05FT029.eop-nam05.prod.protection.outlook.com (2a01:111:f400:7e51::209) by DM5PR07CA0062.outlook.office365.com (2603:10b6:4:ad::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2008.16 via Frontend Transport; Sun, 23 Jun 2019 09:23:11 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning cadence.com discourages use of 199.43.4.28 as permitted sender) Received: from rmmaillnx1.cadence.com (199.43.4.28) by DM3NAM05FT029.mail.protection.outlook.com (10.152.98.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2032.6 via Frontend Transport; Sun, 23 Jun 2019 09:23:10 +0000 Received: from maileu3.global.cadence.com (maileu3.cadence.com [10.160.88.99]) by rmmaillnx1.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9N52x026779 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Sun, 23 Jun 2019 05:23:07 -0400 X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 23 Jun 2019 11:23:04 +0200 Received: from lvlogina.cadence.com (10.165.176.102) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 23 Jun 2019 11:23:04 +0200 Received: from lvlogina.cadence.com (localhost.localdomain [127.0.0.1]) by lvlogina.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9N3PU013548; Sun, 23 Jun 2019 10:23:03 +0100 From: Parshuram Thombare To: , , , CC: , , , , , , , Subject: [PATCH v4 2/5] net: macb: add support for sgmii MAC-PHY interface Date: Sun, 23 Jun 2019 10:23:01 +0100 Message-ID: <1561281781-13479-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1561281419-6030-1-git-send-email-pthombar@cadence.com> References: <1561281419-6030-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:199.43.4.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(979002)(346002)(396003)(136003)(376002)(39860400002)(2980300002)(199004)(189003)(36092001)(186003)(53936002)(76176011)(48376002)(51416003)(316002)(77096007)(4326008)(47776003)(26005)(2906002)(11346002)(16586007)(426003)(107886003)(2616005)(14444005)(476003)(7126003)(5660300002)(446003)(69596002)(126002)(50226002)(50466002)(53416004)(336012)(305945005)(356004)(110136005)(54906003)(7696005)(68736007)(478600001)(70586007)(86362001)(8936002)(26826003)(486006)(36756003)(76130400001)(2201001)(81166006)(81156014)(8676002)(70206006)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR07MB6971; H:rmmaillnx1.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:InfoDomainNonexistent; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 05fc56aa-d48e-4cf7-56c4-08d6f7bc692f X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328); SRVR:DM6PR07MB6971; X-MS-TrafficTypeDiagnostic: DM6PR07MB6971: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-Forefront-PRVS: 00770C4423 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: +AQ+R21ssNyUkffb8PNtxmOeYavMoccYsTD3UiHqtInZs2CXga0qlIk0p0XC/W4woE3a2q+jYaCh8BGszzQVPl3WvrqRuRdXYhDJsvK5YKqoDchtFKIOo6qn0z8xCTdLrFdvV6+K28I+yX92qvGiC1PMywzlL+puiY5V2n5UCd4QNQbGsL5Sv5YckAukTV66cPJanO2uXwvt/hrPFxYioGZasne4f6eEIcsYFfLl16Xn4Y5U10seFVHu7Aq31WuNFhcnXnDw6Kw5IjhlRYQXOYu8v9jUk+rnKY2zPBA3JG5Vsibw2py1aIuvtCaqORvZF6NaEUOTWrRaqSfZMugyAGCjvHUS05JVC0TpsB0iX2psJV52IqIbaa6u2u0ixzVBbptiQwyypB1AfC0mDWKem1tU0vf7EaOq5XRgt2EDlxM= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2019 09:23:10.4782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05fc56aa-d48e-4cf7-56c4-08d6f7bc692f X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6971 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-23_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906230083 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add support for SGMII interface) and 2.5Gbps MAC in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 54 ++++++++++++---- drivers/net/ethernet/cadence/macb_main.c | 80 +++++++++++++++++++++--- 2 files changed, 112 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 8629d345af31..6d268283c318 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -77,6 +77,7 @@ #define MACB_RBQPH 0x04D4 /* GEM register offsets. */ +#define GEM_NCR 0x0000 /* Network Control */ #define GEM_NCFGR 0x0004 /* Network Config */ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ @@ -156,6 +157,7 @@ #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ +#define GEM_PCS_CTRL 0x0200 /* PCS Control */ #define GEM_DCFG1 0x0280 /* Design Config 1 */ #define GEM_DCFG2 0x0284 /* Design Config 2 */ #define GEM_DCFG3 0x0288 /* Design Config 3 */ @@ -271,6 +273,10 @@ #define MACB_IRXFCS_OFFSET 19 #define MACB_IRXFCS_SIZE 1 +/* GEM specific NCR bitfields. */ +#define GEM_TWO_PT_FIVE_GIG_OFFSET 29 +#define GEM_TWO_PT_FIVE_GIG_SIZE 1 + /* GEM specific NCFGR bitfields. */ #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ #define GEM_GBE_SIZE 1 @@ -323,6 +329,9 @@ #define MACB_MDIO_SIZE 1 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ #define MACB_IDLE_SIZE 1 +#define MACB_DUPLEX_OFFSET 3 +#define MACB_DUPLEX_SIZE 1 + /* Bitfields in TSR */ #define MACB_UBR_OFFSET 0 /* Used bit read */ @@ -456,11 +465,17 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfields in PCS_CONTROL. */ +#define GEM_PCS_CTRL_RST_OFFSET 15 +#define GEM_PCS_CTRL_RST_SIZE 1 + /* Bitfields in DCFG1. */ #define GEM_IRQCOR_OFFSET 23 #define GEM_IRQCOR_SIZE 1 #define GEM_DBWDEF_OFFSET 25 #define GEM_DBWDEF_SIZE 3 +#define GEM_NO_PCS_OFFSET 0 +#define GEM_NO_PCS_SIZE 1 /* Bitfields in DCFG2. */ #define GEM_RX_PKT_BUFF_OFFSET 20 @@ -633,19 +648,32 @@ #define MACB_MAN_CODE 2 /* Capability mask bits */ -#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 -#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 -#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 -#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 -#define MACB_CAPS_USRIO_DISABLED 0x00000010 -#define MACB_CAPS_JUMBO 0x00000020 -#define MACB_CAPS_GEM_HAS_PTP 0x00000040 -#define MACB_CAPS_BD_RD_PREFETCH 0x00000080 -#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 -#define MACB_CAPS_FIFO_MODE 0x10000000 -#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 -#define MACB_CAPS_SG_DISABLED 0x40000000 -#define MACB_CAPS_MACB_IS_GEM 0x80000000 +#define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) +#define MACB_CAPS_USRIO_HAS_CLKEN BIT(1) +#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII BIT(2) +#define MACB_CAPS_NO_GIGABIT_HALF BIT(3) +#define MACB_CAPS_USRIO_DISABLED BIT(4) +#define MACB_CAPS_JUMBO BIT(5) +#define MACB_CAPS_GEM_HAS_PTP BIT(6) +#define MACB_CAPS_BD_RD_PREFETCH BIT(7) +#define MACB_CAPS_NEEDS_RSTONUBR BIT(8) +#define MACB_CAPS_FIFO_MODE BIT(28) +#define MACB_CAPS_GIGABIT_MODE_AVAILABLE BIT(29) +#define MACB_CAPS_SG_DISABLED BIT(30) +#define MACB_CAPS_MACB_IS_GEM BIT(31) +#define MACB_CAPS_PCS BIT(24) +#define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) + +#define MACB_GEM7010_IDNUM 0x009 +#define MACB_GEM7014_IDNU 0x107 +#define MACB_GEM7014A_IDNUM 0x207 +#define MACB_GEM7016_IDNUM 0x10a +#define MACB_GEM7017_IDNUM 0x00a +#define MACB_GEM7017A_IDNUM 0x20a +#define MACB_GEM7020_IDNUM 0x003 +#define MACB_GEM7021_IDNUM 0x00c +#define MACB_GEM7021A_IDNUM 0x20c +#define MACB_GEM7022_IDNUM 0x00b /* LSO settings */ #define MACB_LSO_UFO_ENABLE 0x01 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 1d6527a5313f..10d18b2cef31 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -445,15 +445,15 @@ static void gem_phylink_validate(struct phylink_config *pl_config, __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; switch (state->interface) { + case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { phylink_set(mask, 1000baseT_Full); phylink_set(mask, 1000baseX_Full); - if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) { + if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) phylink_set(mask, 1000baseT_Half); - phylink_set(mask, 1000baseT_Half); - } } /* fallthrough */ case PHY_INTERFACE_MODE_MII: @@ -469,7 +469,6 @@ static void gem_phylink_validate(struct phylink_config *pl_config, linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); - } static int gem_phylink_mac_link_state(struct phylink_config *pl_config, @@ -483,19 +482,42 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, { struct net_device *netdev = to_net_dev(pl_config->dev); struct macb *bp = netdev_priv(netdev); + bool change_interface = bp->phy_interface != state->interface; unsigned long flags; spin_lock_irqsave(&bp->lock, flags); + if (change_interface) { + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { + gem_writel(bp, NCFGR, ~GEM_BIT(SGMIIEN) & + ~GEM_BIT(PCSSEL) & + gem_readl(bp, NCFGR)); + gem_writel(bp, NCR, ~GEM_BIT(TWO_PT_FIVE_GIG) & + gem_readl(bp, NCR)); + gem_writel(bp, PCS_CTRL, gem_readl(bp, PCS_CTRL) | + GEM_BIT(PCS_CTRL_RST)); + } + bp->phy_interface = state->interface; + } + if (!phylink_autoneg_inband(mode) && (bp->speed != state->speed || - bp->duplex != state->duplex)) { + bp->duplex != state->duplex || + change_interface)) { u32 reg; reg = macb_readl(bp, NCFGR); reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); if (macb_is_gem(bp)) reg &= ~GEM_BIT(GBE); + macb_or_gem_writel(bp, NCFGR, reg); + + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) | + GEM_BIT(PCSSEL) | + gem_readl(bp, NCFGR)); + + reg = macb_readl(bp, NCFGR); if (state->duplex) reg |= MACB_BIT(FD); @@ -590,8 +612,8 @@ static int macb_mii_probe(struct net_device *dev) } bp->link = 0; - bp->speed = 0; - bp->duplex = -1; + bp->speed = SPEED_UNKNOWN; + bp->duplex = DUPLEX_UNKNOWN; return ret; } @@ -3340,6 +3362,22 @@ static void macb_configure_caps(struct macb *bp, dcfg = gem_readl(bp, DCFG1); if (GEM_BFEXT(IRQCOR, dcfg) == 0) bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; + if (GEM_BFEXT(NO_PCS, dcfg) == 0) + bp->caps |= MACB_CAPS_PCS; + switch (MACB_BFEXT(IDNUM, macb_readl(bp, MID))) { + case MACB_GEM7016_IDNUM: + case MACB_GEM7017_IDNUM: + case MACB_GEM7017A_IDNUM: + case MACB_GEM7020_IDNUM: + case MACB_GEM7021_IDNUM: + case MACB_GEM7021A_IDNUM: + case MACB_GEM7022_IDNUM: + bp->caps |= MACB_CAPS_USRIO_DISABLED; + bp->caps |= MACB_CAPS_MACB_IS_GEM_GXL; + break; + default: + break; + } dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -4322,11 +4360,35 @@ static int macb_probe(struct platform_device *pdev) } phy_mode = of_get_phy_mode(np); - if (phy_mode < 0) + if (phy_mode < 0) { /* not found in DT, MII by default */ bp->phy_interface = PHY_INTERFACE_MODE_MII; - else + } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { + u32 interface_supported = 1; + + if (phy_mode == PHY_INTERFACE_MODE_SGMII) { + if (!(bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + } else if (phy_mode == PHY_INTERFACE_MODE_GMII || + phy_mode == PHY_INTERFACE_MODE_RGMII) { + if (!macb_is_gem(bp)) + interface_supported = 0; + } else if (phy_mode != PHY_INTERFACE_MODE_RMII && + phy_mode != PHY_INTERFACE_MODE_MII) { + /* Add new mode before this */ + interface_supported = 0; + } + + if (!interface_supported) { + netdev_err(dev, "Phy mode %s not supported", + phy_modes(phy_mode)); + goto err_out_free_netdev; + } + bp->phy_interface = phy_mode; + } else { + bp->phy_interface = phy_mode; + } /* IP specific init */ err = init(pdev); From patchwork Sun Jun 23 09:23:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1120768 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="jjjcny+i"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="CV+6DBr4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Wn6N6ZRgz9s4Y for ; Sun, 23 Jun 2019 19:23:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726521AbfFWJXg (ORCPT ); Sun, 23 Jun 2019 05:23:36 -0400 Received: from mx0a-0014ca01.pphosted.com ([208.84.65.235]:34908 "EHLO mx0a-0014ca01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726050AbfFWJXg (ORCPT ); Sun, 23 Jun 2019 05:23:36 -0400 Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5N9LgSM007305; Sun, 23 Jun 2019 02:23:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=proofpoint; bh=LB0FWTEtmAYpoAQdPVue3wcRfmXie5oeI1DqYFDbiyo=; b=jjjcny+iDfxwBLDMIgn0qEUR/a7a4WgjIjPPf9S/WE3ijAsp7/0sg4rOm4PLo04U+oFX Eg2WixHEVcRdatPFD7Vcy2ByfaTYD3mGDgmgcu9iJvjTebn890HZDZvelOhlpCXTBe67 cJZOCgzq+GgyLX2mCUPkpimuo0hOEBWJfeJWQ+omoICNk8DHxYKAV9y+UIw0I2IL/td1 UVCVi8RXY1V102LG1EBvZ/7LCiaii7W+PGRIVQivdpEADC6yiQzRh5g5uD2OaF9aA5i7 j2iAPC1bVRFVZoUxKxtDUmKTBIPOAy/ph7lmy/hXSdz96oEqaH6IHkOba7W7fB4+khOj ww== Authentication-Results: cadence.com; spf=pass smtp.mailfrom=pthombar@cadence.com Received: from nam03-dm3-obe.outbound.protection.outlook.com (mail-dm3nam03lp2051.outbound.protection.outlook.com [104.47.41.51]) by mx0a-0014ca01.pphosted.com with ESMTP id 2t9gvs2nn9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Jun 2019 02:23:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LB0FWTEtmAYpoAQdPVue3wcRfmXie5oeI1DqYFDbiyo=; b=CV+6DBr4BTeehrAHilj3CSdhNQ5dXESU6rgPe7437N/uMrFhWVTuEXspvtwqdmw21d6CPhFy+nC5K6B9W5jANuLwj+jrpMCQFvABV4C3OYH3XaRJt7198zWq5UFNx+aFLWpbTFBNNNAkGGAcISvpZ3jFLC29BeLULxGra5OG3wY= Received: from SN4PR0701CA0001.namprd07.prod.outlook.com (2603:10b6:803:28::11) by BY5PR07MB6966.namprd07.prod.outlook.com (2603:10b6:a03:1e7::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; Sun, 23 Jun 2019 09:23:24 +0000 Received: from DM3NAM05FT055.eop-nam05.prod.protection.outlook.com (2a01:111:f400:7e51::207) by SN4PR0701CA0001.outlook.office365.com (2603:10b6:803:28::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2008.16 via Frontend Transport; Sun, 23 Jun 2019 09:23:24 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning cadence.com discourages use of 158.140.1.28 as permitted sender) Received: from sjmaillnx1.cadence.com (158.140.1.28) by DM3NAM05FT055.mail.protection.outlook.com (10.152.98.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2032.6 via Frontend Transport; Sun, 23 Jun 2019 09:23:23 +0000 Received: from maileu3.global.cadence.com (maileu3.cadence.com [10.160.88.99]) by sjmaillnx1.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9NKLQ008652 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Sun, 23 Jun 2019 02:23:22 -0700 X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 23 Jun 2019 11:23:20 +0200 Received: from lvlogina.cadence.com (10.165.176.102) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 23 Jun 2019 11:23:19 +0200 Received: from lvlogina.cadence.com (localhost.localdomain [127.0.0.1]) by lvlogina.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9NJM1013942; Sun, 23 Jun 2019 10:23:19 +0100 From: Parshuram Thombare To: , , , CC: , , , , , , , Subject: [PATCH v4 3/5] net: macb: add support for c45 PHY Date: Sun, 23 Jun 2019 10:23:17 +0100 Message-ID: <1561281797-13796-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1561281419-6030-1-git-send-email-pthombar@cadence.com> References: <1561281419-6030-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(396003)(136003)(346002)(376002)(39860400002)(2980300002)(36092001)(189003)(199004)(53416004)(26826003)(16586007)(305945005)(107886003)(110136005)(316002)(54906003)(76176011)(5660300002)(7696005)(4326008)(47776003)(26005)(77096007)(186003)(48376002)(8936002)(76130400001)(2906002)(50226002)(86362001)(336012)(246002)(486006)(7636002)(478600001)(51416003)(126002)(426003)(8676002)(2616005)(50466002)(11346002)(446003)(2201001)(356004)(476003)(36756003)(70586007)(70206006)(7126003); DIR:OUT; SFP:1101; SCL:1; SRVR:BY5PR07MB6966; H:sjmaillnx1.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:corp.cadence.com; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a5ad2636-2b9f-4f04-be9c-08d6f7bc70f5 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328); SRVR:BY5PR07MB6966; X-MS-TrafficTypeDiagnostic: BY5PR07MB6966: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2000; X-Forefront-PRVS: 00770C4423 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 0HFv4Gw2Y+fgO/W5vdEjV1BxvgMUauzqrOLXeP0Wq2PhuqRULvhtPx4jiQW/exH/gJnm6T3Itu9fjCavaxyKUDro2tyW6BO8bRP8gBI1ABChuPsmgyE78sxibTi/609eQcLS7FsxyfCBiDeVrutrFpwYxuICey+2rnPbu7ccwqdxJlApyhZgUsNeqBvMXu7+iwnNxb0onijS5jcl4g86ylfsVLsXhzIpf2TJCEuq9TPamFprGULOTn4AXGEXLMZ7qz2LmFANuAjlXgzjhQcHDag85HwE0hzDLOFqUTtTEua8AG19XTu/Y35IZdA6E98S4Xwi0L0dCu/5xplN1YZJZhcHXpF3PJeGOB1t86z6abaB58iJmq5LbHtjCqA1gIDJ55nUPex0fSOMAyk889TCaZ85ZQj1VQ6vfM6dpnJS/HY= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2019 09:23:23.5125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5ad2636-2b9f-4f04-be9c-08d6f7bc70f5 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR07MB6966 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-23_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=757 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906230083 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch modify MDIO read/write functions to support communication with C45 PHY. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 15 ++++-- drivers/net/ethernet/cadence/macb_main.c | 61 +++++++++++++++++++----- 2 files changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 6d268283c318..330da702b946 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -642,10 +642,17 @@ #define GEM_CLK_DIV96 5 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_C22_SOF 1 +#define MACB_MAN_C22_WRITE 1 +#define MACB_MAN_C22_READ 2 +#define MACB_MAN_C22_CODE 2 + +#define MACB_MAN_C45_SOF 0 +#define MACB_MAN_C45_ADDR 0 +#define MACB_MAN_C45_WRITE 1 +#define MACB_MAN_C45_POST_READ_INCR 2 +#define MACB_MAN_C45_READ 3 +#define MACB_MAN_C45_CODE 2 /* Capability mask bits */ #define MACB_CAPS_ISR_CLEAR_ON_WRITE BIT(0) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 10d18b2cef31..94145e460e6e 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -341,11 +341,30 @@ static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (status < 0) goto mdio_read_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_READ) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_read_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_READ) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE))); + } status = macb_mdio_wait_for_idle(bp); if (status < 0) @@ -374,12 +393,32 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, if (status < 0) goto mdio_write_exit; - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) - | MACB_BF(RW, MACB_MAN_WRITE) - | MACB_BF(PHYA, mii_id) - | MACB_BF(REGA, regnum) - | MACB_BF(CODE, MACB_MAN_CODE) - | MACB_BF(DATA, value))); + if (regnum & MII_ADDR_C45) { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_ADDR) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(DATA, regnum & 0xFFFF) + | MACB_BF(CODE, MACB_MAN_C45_CODE))); + + status = macb_mdio_wait_for_idle(bp); + if (status < 0) + goto mdio_write_exit; + + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF) + | MACB_BF(RW, MACB_MAN_C45_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, (regnum >> 16) & 0x1F) + | MACB_BF(CODE, MACB_MAN_C45_CODE) + | MACB_BF(DATA, value))); + } else { + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF) + | MACB_BF(RW, MACB_MAN_C22_WRITE) + | MACB_BF(PHYA, mii_id) + | MACB_BF(REGA, regnum) + | MACB_BF(CODE, MACB_MAN_C22_CODE) + | MACB_BF(DATA, value))); + } status = macb_mdio_wait_for_idle(bp); if (status < 0) From patchwork Sun Jun 23 09:23:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1120769 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="C7S1fqRW"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="npz1tagq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Wn6X5KXRz9sBb for ; Sun, 23 Jun 2019 19:23:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726544AbfFWJXo (ORCPT ); Sun, 23 Jun 2019 05:23:44 -0400 Received: from mx0a-0014ca01.pphosted.com ([208.84.65.235]:32560 "EHLO mx0a-0014ca01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726050AbfFWJXn (ORCPT ); Sun, 23 Jun 2019 05:23:43 -0400 Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5N9LhQ4007309; Sun, 23 Jun 2019 02:23:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=proofpoint; bh=c0t4VMV+2v8bQEtW4VrDj1n+L+Kl1QBMn2wQU9AXs60=; b=C7S1fqRWAWxfcngf/cgk8M08DSdzZ7oCizP3vETNZcK4MebjkYcFOxsaMNORQFoTKdhy WWS+K6dueY8JEJN8CBKXMlyp/mp5/zWeIi4CygZHVOb+vgeSNUCOx27zqwOtTukdhnzr IdSrIcmICBJsDIPSnWJrgbWpIFuquu3BqeSea11m7lpoUim19X4Xt5q7XD3QVJXvmtji JS1khCgSz1ibnmDlcQ9+S5XidTzZMOfXJgV1TdJM9YnJb9HGOtaYVXQkuD2kq/f+5Cmv 9SrtVSElgtSc+CVBbyMo0fGdCRvJ+XQExxI3zsrYT+R5WmHyxmR4MzSnoL3FmYWh5NWN 7g== Authentication-Results: cadence.com; spf=pass smtp.mailfrom=pthombar@cadence.com Received: from nam03-by2-obe.outbound.protection.outlook.com (mail-by2nam03lp2057.outbound.protection.outlook.com [104.47.42.57]) by mx0a-0014ca01.pphosted.com with ESMTP id 2t9gvs2nnd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 23 Jun 2019 02:23:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c0t4VMV+2v8bQEtW4VrDj1n+L+Kl1QBMn2wQU9AXs60=; b=npz1tagq5n7/WcIddzZSUXO99SVZhzzd34OxYndRe1BmYqlIgJLQfLFIJ6+Cpgga14ID8L8C7ylDHxQoEMJqNel1HBAlAgPbgge/V4AEyBDgqi8IpB/4XTI5lsld+egMrmmRFlppnhUviF8kGQu9BXhvcqtrkFhodGWkKvSjGVw= Received: from BYAPR07CA0058.namprd07.prod.outlook.com (2603:10b6:a03:60::35) by BYAPR07MB6824.namprd07.prod.outlook.com (2603:10b6:a03:128::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; Sun, 23 Jun 2019 09:23:33 +0000 Received: from DM3NAM05FT018.eop-nam05.prod.protection.outlook.com (2a01:111:f400:7e51::207) by BYAPR07CA0058.outlook.office365.com (2603:10b6:a03:60::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2008.16 via Frontend Transport; Sun, 23 Jun 2019 09:23:33 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning cadence.com discourages use of 158.140.1.28 as permitted sender) Received: from sjmaillnx2.cadence.com (158.140.1.28) by DM3NAM05FT018.mail.protection.outlook.com (10.152.98.127) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2032.6 via Frontend Transport; Sun, 23 Jun 2019 09:23:32 +0000 Received: from maileu3.global.cadence.com (maileu3.cadence.com [10.160.88.99]) by sjmaillnx2.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9NTfX011163 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Sun, 23 Jun 2019 02:23:31 -0700 X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 23 Jun 2019 11:23:28 +0200 Received: from lvlogina.cadence.com (10.165.176.102) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 23 Jun 2019 11:23:28 +0200 Received: from lvlogina.cadence.com (localhost.localdomain [127.0.0.1]) by lvlogina.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9NSLc014059; Sun, 23 Jun 2019 10:23:28 +0100 From: Parshuram Thombare To: , , , CC: , , , , , , , Subject: [PATCH v4 4/5] net: macb: add support for high speed interface Date: Sun, 23 Jun 2019 10:23:26 +0100 Message-ID: <1561281806-13991-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1561281419-6030-1-git-send-email-pthombar@cadence.com> References: <1561281419-6030-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(376002)(39860400002)(346002)(136003)(396003)(2980300002)(36092001)(189003)(199004)(50466002)(186003)(26826003)(36756003)(336012)(4326008)(426003)(86362001)(5660300002)(26005)(77096007)(48376002)(478600001)(30864003)(356004)(70206006)(70586007)(76130400001)(53416004)(7696005)(486006)(476003)(2201001)(14444005)(50226002)(7126003)(11346002)(446003)(126002)(2616005)(305945005)(7636002)(246002)(2906002)(316002)(8936002)(107886003)(8676002)(76176011)(47776003)(110136005)(16586007)(54906003)(51416003); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB6824; H:sjmaillnx2.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:corp.cadence.com; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 360d41a0-dcfe-46f7-3d76-08d6f7bc767a X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328); SRVR:BYAPR07MB6824; X-MS-TrafficTypeDiagnostic: BYAPR07MB6824: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-Forefront-PRVS: 00770C4423 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: CMcgJ9yFNfSJTSNunVT/m3MgbE4hWRwg99OnW6YcC3gIYkQfuD/Bb8aAui38U6KXpVuclwNH9TCc+mUSI9SpRT5c3Z4BnOHAgX19GlUfMqSVXNJL6dygStnWWSJFN7QmNjUoNJbrm2nuSb6sT8+oP2lYOuRRYQWDwxYkIZ0oWukg7WTltzT+nS+ghVUMTNfCADFOoAAsP+QFFlFWB9sF+xsO9wCVUfnPeMEsoL/zH523/o2tYdQqBFQTVh8puwSBaWqW0zT2KG6t11VNZwvCw3Du3dOKRlQgx2XIhR9CNPHIR08N8X0McxImB3dllp/QG2ejeQjX7nrvIhH6gdBRFdalyB1j2lutNOUbouZf3N/EI9kyAemtB8sUFUkh9SoVpeuqFGtHQR/USM7QyyCl/uyV+ecYvpYEKkMeVmS6hiQ= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2019 09:23:32.7784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 360d41a0-dcfe-46f7-3d76-08d6f7bc767a X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.28]; Helo=[sjmaillnx2.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB6824 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-23_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906230083 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add support for high speed USXGMII PCS and 10G speed in Cadence ethernet controller driver. Signed-off-by: Parshuram Thombare --- drivers/net/ethernet/cadence/macb.h | 41 +++++ drivers/net/ethernet/cadence/macb_main.c | 194 +++++++++++++++++++---- 2 files changed, 207 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 330da702b946..809acff19be9 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -82,6 +82,7 @@ #define GEM_USRIO 0x000c /* User IO */ #define GEM_DMACFG 0x0010 /* DMA Configuration */ #define GEM_JML 0x0048 /* Jumbo Max Length */ +#define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ #define GEM_HRB 0x0080 /* Hash Bottom */ #define GEM_HRT 0x0084 /* Hash Top */ #define GEM_SA1B 0x0088 /* Specific1 Bottom */ @@ -167,6 +168,9 @@ #define GEM_DCFG7 0x0298 /* Design Config 7 */ #define GEM_DCFG8 0x029C /* Design Config 8 */ #define GEM_DCFG10 0x02A4 /* Design Config 10 */ +#define GEM_DCFG12 0x02AC /* Design Config 12 */ +#define GEM_USX_CONTROL 0x0A80 /* USXGMII control register */ +#define GEM_USX_STATUS 0x0A88 /* USXGMII status register */ #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ @@ -274,6 +278,8 @@ #define MACB_IRXFCS_SIZE 1 /* GEM specific NCR bitfields. */ +#define GEM_ENABLE_HS_MAC_OFFSET 31 +#define GEM_ENABLE_HS_MAC_SIZE 1 #define GEM_TWO_PT_FIVE_GIG_OFFSET 29 #define GEM_TWO_PT_FIVE_GIG_SIZE 1 @@ -465,6 +471,10 @@ #define MACB_REV_OFFSET 0 #define MACB_REV_SIZE 16 +/* Bitfield in HS_MAC_CONFIG */ +#define GEM_HS_MAC_SPEED_OFFSET 0 +#define GEM_HS_MAC_SPEED_SIZE 3 + /* Bitfields in PCS_CONTROL. */ #define GEM_PCS_CTRL_RST_OFFSET 15 #define GEM_PCS_CTRL_RST_SIZE 1 @@ -510,6 +520,34 @@ #define GEM_RXBD_RDBUFF_OFFSET 8 #define GEM_RXBD_RDBUFF_SIZE 4 +/* Bitfields in DCFG12. */ +#define GEM_HIGH_SPEED_OFFSET 26 +#define GEM_HIGH_SPEED_SIZE 1 + +/* Bitfields in USX_CONTROL. */ +#define GEM_USX_CTRL_SPEED_OFFSET 14 +#define GEM_USX_CTRL_SPEED_SIZE 3 +#define GEM_SERDES_RATE_OFFSET 12 +#define GEM_SERDES_RATE_SIZE 2 +#define GEM_RX_SCR_BYPASS_OFFSET 9 +#define GEM_RX_SCR_BYPASS_SIZE 1 +#define GEM_TX_SCR_BYPASS_OFFSET 8 +#define GEM_TX_SCR_BYPASS_SIZE 1 +#define GEM_RX_SYNC_RESET_OFFSET 2 +#define GEM_RX_SYNC_RESET_SIZE 1 +#define GEM_TX_EN_OFFSET 1 +#define GEM_TX_EN_SIZE 1 +#define GEM_SIGNAL_OK_OFFSET 0 +#define GEM_SIGNAL_OK_SIZE 1 + +/* Bitfields in USX_STATUS. */ +#define GEM_USX_TX_FAULT_OFFSET 28 +#define GEM_USX_TX_FAULT_SIZE 1 +#define GEM_USX_RX_FAULT_OFFSET 27 +#define GEM_USX_RX_FAULT_SIZE 1 +#define GEM_USX_BLOCK_LOCK_OFFSET 0 +#define GEM_USX_BLOCK_LOCK_SIZE 1 + /* Bitfields in TISUBN */ #define GEM_SUBNSINCR_OFFSET 0 #define GEM_SUBNSINCR_SIZE 16 @@ -670,6 +708,7 @@ #define MACB_CAPS_MACB_IS_GEM BIT(31) #define MACB_CAPS_PCS BIT(24) #define MACB_CAPS_MACB_IS_GEM_GXL BIT(25) +#define MACB_CAPS_HIGH_SPEED BIT(26) #define MACB_GEM7010_IDNUM 0x009 #define MACB_GEM7014_IDNU 0x107 @@ -749,6 +788,7 @@ }) #define MACB_READ_NSR(bp) macb_readl(bp, NSR) +#define GEM_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS) /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer @@ -1262,6 +1302,7 @@ struct macb { struct macb_pm_data pm_data; struct phylink *pl; struct phylink_config pl_config; + u32 serdes_rate; }; #ifdef CONFIG_MACB_USE_HWSTAMP diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 94145e460e6e..65eda399aef8 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -84,6 +84,20 @@ static struct sifive_fu540_macb_mgmt *mgmt; #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) #define MACB_WOL_ENABLED (0x1 << 1) +enum { + HS_MAC_SPEED_100M, + HS_MAC_SPEED_1000M, + HS_MAC_SPEED_2500M, + HS_MAC_SPEED_5000M, + HS_MAC_SPEED_10000M, + HS_MAC_SPEED_25000M, +}; + +enum { + MACB_SERDES_RATE_5_PT_15625Gbps = 5, + MACB_SERDES_RATE_10_PT_3125Gbps = 10, +}; + /* Graceful stop timeouts in us. We should allow up to * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) */ @@ -93,6 +107,8 @@ static struct sifive_fu540_macb_mgmt *mgmt; #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ +#define MACB_USX_BLOCK_LOCK_TIMEOUT 1000000 /* in usecs */ + /* DMA buffer descriptor might be different size * depends on hardware configuration: * @@ -439,23 +455,37 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, */ static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) { + struct macb *bp = netdev_priv(dev); long ferr, rate, rate_rounded; if (!clk) return; - switch (speed) { - case SPEED_10: - rate = 2500000; - break; - case SPEED_100: - rate = 25000000; - break; - case SPEED_1000: - rate = 125000000; - break; - default: - return; + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + switch (bp->serdes_rate) { + case MACB_SERDES_RATE_5_PT_15625Gbps: + rate = 78125000; + break; + case MACB_SERDES_RATE_10_PT_3125Gbps: + rate = 156250000; + break; + default: + return; + } + } else { + switch (speed) { + case SPEED_10: + rate = 2500000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_1000: + rate = 125000000; + break; + default: + return; + } } rate_rounded = clk_round_rate(clk, rate); @@ -485,6 +515,21 @@ static void gem_phylink_validate(struct phylink_config *pl_config, switch (state->interface) { case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GKR: + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) { + phylink_set(mask, 10000baseCR_Full); + phylink_set(mask, 10000baseER_Full); + phylink_set(mask, 10000baseKR_Full); + phylink_set(mask, 10000baseLR_Full); + phylink_set(mask, 10000baseLRM_Full); + phylink_set(mask, 10000baseSR_Full); + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 5000baseT_Full); + phylink_set(mask, 2500baseX_Full); + phylink_set(mask, 1000baseX_Full); + } + /* fallthrough */ case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: @@ -516,6 +561,91 @@ static int gem_phylink_mac_link_state(struct phylink_config *pl_config, return -EOPNOTSUPP; } +static int macb_wait_for_usx_block_lock(struct macb *bp) +{ + u32 val; + + return readx_poll_timeout(GEM_READ_USX_STATUS, bp, val, + val & GEM_BIT(USX_BLOCK_LOCK), + 1, MACB_USX_BLOCK_LOCK_TIMEOUT); +} + +static inline int gem_mac_usx_configure(struct macb *bp, int spd) +{ + u32 speed, config; + + gem_writel(bp, NCFGR, GEM_BIT(PCSSEL) | + (~GEM_BIT(SGMIIEN) & gem_readl(bp, NCFGR))); + gem_writel(bp, NCR, gem_readl(bp, NCR) | + GEM_BIT(ENABLE_HS_MAC)); + gem_writel(bp, NCFGR, gem_readl(bp, NCFGR) | + MACB_BIT(FD)); + config = gem_readl(bp, USX_CONTROL); + config = GEM_BFINS(SERDES_RATE, bp->serdes_rate, config); + config &= ~GEM_BIT(TX_SCR_BYPASS); + config &= ~GEM_BIT(RX_SCR_BYPASS); + gem_writel(bp, USX_CONTROL, config | + GEM_BIT(TX_EN)); + config = gem_readl(bp, USX_CONTROL); + gem_writel(bp, USX_CONTROL, config | GEM_BIT(SIGNAL_OK)); + if (macb_wait_for_usx_block_lock(bp) < 0) { + netdev_warn(bp->dev, "USXGMII block lock failed"); + return -ETIMEDOUT; + } + + switch (spd) { + case SPEED_10000: + if (bp->serdes_rate >= MACB_SERDES_RATE_10_PT_3125Gbps) { + speed = HS_MAC_SPEED_10000M; + } else { + netdev_warn(bp->dev, "10G speed isn't supported by HW"); + netdev_warn(bp->dev, "Setting speed to 1G"); + speed = HS_MAC_SPEED_1000M; + } + break; + case SPEED_5000: + speed = HS_MAC_SPEED_5000M; + break; + case SPEED_2500: + speed = HS_MAC_SPEED_2500M; + break; + case SPEED_1000: + speed = HS_MAC_SPEED_1000M; + break; + default: + case SPEED_100: + speed = HS_MAC_SPEED_100M; + break; + } + + gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, speed, + gem_readl(bp, HS_MAC_CONFIG))); + gem_writel(bp, USX_CONTROL, GEM_BFINS(USX_CTRL_SPEED, speed, + gem_readl(bp, USX_CONTROL))); + return 0; +} + +static inline void gem_mac_configure(struct macb *bp, int speed) +{ + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) + gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) | + GEM_BIT(PCSSEL) | + gem_readl(bp, NCFGR)); + + switch (speed) { + case SPEED_1000: + gem_writel(bp, NCFGR, GEM_BIT(GBE) | + gem_readl(bp, NCFGR)); + break; + case SPEED_100: + macb_writel(bp, NCFGR, MACB_BIT(SPD) | + macb_readl(bp, NCFGR)); + break; + default: + break; + } +} + static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, const struct phylink_link_state *state) { @@ -551,26 +681,20 @@ static void gem_mac_config(struct phylink_config *pl_config, unsigned int mode, reg &= ~GEM_BIT(GBE); macb_or_gem_writel(bp, NCFGR, reg); - if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) - gem_writel(bp, NCFGR, GEM_BIT(SGMIIEN) | - GEM_BIT(PCSSEL) | - gem_readl(bp, NCFGR)); - reg = macb_readl(bp, NCFGR); if (state->duplex) reg |= MACB_BIT(FD); + macb_or_gem_writel(bp, NCFGR, reg); - switch (state->speed) { - case SPEED_1000: - reg |= GEM_BIT(GBE); - break; - case SPEED_100: - reg |= MACB_BIT(SPD); - break; - default: - break; + if (bp->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + if (gem_mac_usx_configure(bp, state->speed) < 0) { + spin_unlock_irqrestore(&bp->lock, flags); + phylink_mac_change(bp->pl, false); + return; + } + } else { + gem_mac_configure(bp, state->speed); } - macb_or_gem_writel(bp, NCFGR, reg); bp->speed = state->speed; bp->duplex = state->duplex; @@ -3417,6 +3541,9 @@ static void macb_configure_caps(struct macb *bp, default: break; } + dcfg = gem_readl(bp, DCFG12); + if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) + bp->caps |= MACB_CAPS_HIGH_SPEED; dcfg = gem_readl(bp, DCFG2); if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) bp->caps |= MACB_CAPS_FIFO_MODE; @@ -4405,7 +4532,18 @@ static int macb_probe(struct platform_device *pdev) } else if (bp->caps & MACB_CAPS_MACB_IS_GEM_GXL) { u32 interface_supported = 1; - if (phy_mode == PHY_INTERFACE_MODE_SGMII) { + if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { + if (!(bp->caps & MACB_CAPS_HIGH_SPEED && + bp->caps & MACB_CAPS_PCS)) + interface_supported = 0; + + if (of_property_read_u32(np, "serdes-rate-gbps", + &bp->serdes_rate)) { + netdev_err(dev, + "GEM serdes_rate not specified"); + interface_supported = 0; + } + } else if (phy_mode == PHY_INTERFACE_MODE_SGMII) { if (!(bp->caps & MACB_CAPS_PCS)) interface_supported = 0; } else if (phy_mode == PHY_INTERFACE_MODE_GMII || From patchwork Sun Jun 23 09:24:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parshuram Raju Thombare X-Patchwork-Id: 1120770 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=cadence.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="nndYEEkf"; dkim=pass (1024-bit key; unprotected) header.d=cadence.com header.i=@cadence.com header.b="VCAlD9Gj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Wn7g5gvtz9sBb for ; Sun, 23 Jun 2019 19:24:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726559AbfFWJYn (ORCPT ); Sun, 23 Jun 2019 05:24:43 -0400 Received: from mx0a-0014ca01.pphosted.com ([208.84.65.235]:14266 "EHLO mx0a-0014ca01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726050AbfFWJYn (ORCPT ); Sun, 23 Jun 2019 05:24:43 -0400 Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5N9M7or007367; Sun, 23 Jun 2019 02:24:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=proofpoint; bh=bTZct3WyNTs8t7ljibZ5PG06Ui+Yj9uekmABLoOpIrI=; b=nndYEEkfAJrNUT/AWQJJdY9cSH1V7d2AhZKda9mr35Lbu6AwCCVKP484djAcy+bHCs0+ y7t/Vfq0FAtWH0eqoxy6PAduc1313tfMIol6EV6HH5QdqpE20TrInOcGHNdVamQyEJVA djx20U6UAJeQ3sEuoAvyQlIpT6wWquQCNXpunz1On6gv9/1vVuGvYIn7FmT48BNbITtD 1Jfs7eSPel3v4Qp0Ll0O6EB9m1jbwxUBzsZPaYYR4Nn2e4zPfj5t1bSsxMew909e1LMQ AxUEflRKUJX/Tgqk08mAOK5mXAKPIgAxNf8l7SsLuRatb5+xmgOBYA25BAmc+PKGxEFt OQ== Authentication-Results: cadence.com; spf=pass smtp.mailfrom=pthombar@cadence.com Received: from nam01-by2-obe.outbound.protection.outlook.com (mail-by2nam01lp2054.outbound.protection.outlook.com [104.47.34.54]) by mx0a-0014ca01.pphosted.com with ESMTP id 2t9gvs2nqe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Jun 2019 02:24:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cadence.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bTZct3WyNTs8t7ljibZ5PG06Ui+Yj9uekmABLoOpIrI=; b=VCAlD9GjnVjTuAN+WhW9Nk8NO3FfXQ9+p+bzwLHwX9zs7SmnJzB7LJz2kWlMcwQrRY1A8occrABkO/0CTUFxDq7FohDCMzVmMAoztR52L6uwqCGK2w6SNGqhNQvpZqKWHhcz8RthI+4Vl4OsHjD8PinTOsFbNyZOOyTPVledLFU= Received: from DM5PR07CA0089.namprd07.prod.outlook.com (2603:10b6:4:ae::18) by DM6PR07MB6827.namprd07.prod.outlook.com (2603:10b6:5:159::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.13; Sun, 23 Jun 2019 09:24:32 +0000 Received: from BY2NAM05FT055.eop-nam05.prod.protection.outlook.com (2a01:111:f400:7e52::208) by DM5PR07CA0089.outlook.office365.com (2603:10b6:4:ae::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2008.16 via Frontend Transport; Sun, 23 Jun 2019 09:24:32 +0000 Received-SPF: SoftFail (protection.outlook.com: domain of transitioning cadence.com discourages use of 199.43.4.28 as permitted sender) Received: from rmmaillnx1.cadence.com (199.43.4.28) by BY2NAM05FT055.mail.protection.outlook.com (10.152.100.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2032.6 via Frontend Transport; Sun, 23 Jun 2019 09:24:32 +0000 Received: from maileu3.global.cadence.com (maileu3.cadence.com [10.160.88.99]) by rmmaillnx1.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9OTjd026804 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Sun, 23 Jun 2019 05:24:30 -0400 X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 23 Jun 2019 11:24:28 +0200 Received: from lvlogina.cadence.com (10.165.176.102) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Sun, 23 Jun 2019 11:24:28 +0200 Received: from lvlogina.cadence.com (localhost.localdomain [127.0.0.1]) by lvlogina.cadence.com (8.14.4/8.14.4) with ESMTP id x5N9OSIZ015394; Sun, 23 Jun 2019 10:24:28 +0100 From: Parshuram Thombare To: , , , CC: , , , , , , , Subject: [PATCH v4 5/5] net: macb: parameter added to cadence ethernet controller DT binding Date: Sun, 23 Jun 2019 10:24:25 +0100 Message-ID: <1561281865-15328-1-git-send-email-pthombar@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1561281419-6030-1-git-send-email-pthombar@cadence.com> References: <1561281419-6030-1-git-send-email-pthombar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:199.43.4.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(39860400002)(396003)(346002)(376002)(136003)(2980300002)(199004)(189003)(36092001)(16586007)(7696005)(356004)(6666004)(76176011)(4744005)(5660300002)(8936002)(4326008)(50226002)(51416003)(69596002)(336012)(486006)(7126003)(70206006)(11346002)(76130400001)(81166006)(107886003)(126002)(81156014)(26826003)(54906003)(53936002)(446003)(476003)(426003)(70586007)(2616005)(316002)(53416004)(68736007)(110136005)(478600001)(77096007)(48376002)(2906002)(86362001)(8676002)(2201001)(47776003)(50466002)(305945005)(186003)(36756003)(26005); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR07MB6827; H:rmmaillnx1.cadence.com; FPR:; SPF:SoftFail; LANG:en; PTR:InfoDomainNonexistent; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 70954ab7-e528-4c23-4d2c-08d6f7bc99ad X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328); SRVR:DM6PR07MB6827; X-MS-TrafficTypeDiagnostic: DM6PR07MB6827: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-Forefront-PRVS: 00770C4423 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: zWYZ9SrpO+zApTYHSbQHUbmGkNwXBD/QTuEritfHsMM2bybP7bg4Iu9bp3jYfA0ZSq/Zn5kAhGaGgzZarHakGc0WwET2P9zBEEefCgbf6wjxnMAh3jz5noNuN+W4GoC5sSxq5b1iBcAZK9TCkeaKNfTd9/wZ/GCcTMHXU+rHLvXR566mrGctEm0d05nNFaAS9DU0ZN0Eg3rUwqzJu3iyqfW7Pqw859HgogN61ygAtag4AkXONkIF07kYiNTsILW7cqpLCQv10mEtv472esNNpV/TuKFWS2EFIFw7Z4HbfCW1F/sjlQur87TilI7nHm+/OolZpTXRfyoWG0ie+LMtI8TzF0Fwf8PmT8FOkIpAKWbIdkno7JXWYgOJwbl2M9iXjfZs3MT1YS9RsUu0hUkfoV0cH0cX9gk9+YnHZMjLMPs= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2019 09:24:32.1175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70954ab7-e528-4c23-4d2c-08d6f7bc99ad X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[199.43.4.28]; Helo=[rmmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6827 X-Proofpoint-SPF-Result: pass X-Proofpoint-SPF-Record: v=spf1 include:spf.smktg.jp include:_spf.salesforce.com include:mktomail.com include:spf-0014ca01.pphosted.com include:spf.protection.outlook.com include:auth.msgapp.com include:spf.mandrillapp.com ~all X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-23_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906230083 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org New parameters added to Cadence ethernet controller DT binding for USXGMII interface. Signed-off-by: Parshuram Thombare --- Documentation/devicetree/bindings/net/macb.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 63c73fafe26d..dabdf9d3b574 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -28,6 +28,9 @@ Required properties: Optional elements: 'rx_clk' applies to cdns,zynqmp-gem Optional elements: 'tsu_clk' - clocks: Phandles to input clocks. +- serdes-rate-gbps External serdes rate.Mandatory for USXGMII mode. + 5 - 5G + 10 - 10G The MAC address will be determined using the optional properties defined in ethernet.txt.