From patchwork Thu Jun 20 08:17:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1119244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="SjUgDKdH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45TvpM4n0Jz9sDX for ; Thu, 20 Jun 2019 18:18:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726506AbfFTISS (ORCPT ); Thu, 20 Jun 2019 04:18:18 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11518 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725877AbfFTISS (ORCPT ); Thu, 20 Jun 2019 04:18:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 20 Jun 2019 01:18:16 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 20 Jun 2019 01:18:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 20 Jun 2019 01:18:17 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 20 Jun 2019 08:18:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 20 Jun 2019 08:18:16 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.148]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 20 Jun 2019 01:18:16 -0700 From: Jon Hunter To: Thierry Reding , Rob Herring , Mark Rutland CC: , , Jon Hunter , Subject: [PATCH 1/3] arm64: tegra: Fix AGIC register range Date: Thu, 20 Jun 2019 09:17:00 +0100 Message-ID: <20190620081702.17209-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190620081702.17209-1-jonathanh@nvidia.com> References: <20190620081702.17209-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561018696; bh=AFWbg5jHWgDuhe1K+3FnMNM26/5yFQ71F6D5eMqY7+8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SjUgDKdHcWadQA0jGkdW9zLhjKICCJ2s+KBdmiy0Cixd5uM3C3uLGl6pYB9rqphmN dydNUtci5cccMstt45mc3jgfpWtA8B1cYZcgcb+hl5+S/VReuukiv3uCUMXIFQP69F 8xihO3kyBsh6Dp3gHLgwohqbWKwK5+4GZlpTO47iwl08AAS7H1gdMpHgTQE7JU8Kkv L1EgBWQ21sU36sRTa2q0oUKwZw4HSKhWmWLHfjDcawy1LI3jGuAViBlk8Vkj41h8tF ulQdjxKkNgMVGJga5htT8r25HKeR+y5ZvarJCxrSWXkwXi//QD3AmptBvIyCEjaMzt +IChI4oO3w3DA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra AGIC interrupt controller is an ARM GIC400 interrupt controller. Per the ARM GIC device-tree binding, the first address region is for the GIC distributor registers and the second address region is for the GIC CPU interface registers. The address space for the distributor registers is 4kB, but currently this is incorrectly defined as 8kB for the Tegra AGIC and overlaps with the CPU interface registers. Correct the address space for the distributor to be 4kB. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index edf27fe2f10e..ec762b3455b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1258,7 +1258,7 @@ compatible = "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x702f9000 0x2000>, + reg = <0x702f9000 0x1000>, <0x702fa000 0x2000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_APE>; From patchwork Thu Jun 20 08:17:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1119245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="JZIyrluG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45TvpN50ZXz9s4Y for ; Thu, 20 Jun 2019 18:18:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726351AbfFTIST (ORCPT ); Thu, 20 Jun 2019 04:18:19 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3266 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725877AbfFTIST (ORCPT ); Thu, 20 Jun 2019 04:18:19 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 20 Jun 2019 01:18:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 20 Jun 2019 01:18:18 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 20 Jun 2019 01:18:18 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 20 Jun 2019 08:18:18 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 20 Jun 2019 08:18:18 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.148]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 20 Jun 2019 01:18:17 -0700 From: Jon Hunter To: Thierry Reding , Rob Herring , Mark Rutland CC: , , Jon Hunter , Subject: [PATCH 2/3] arm64: tegra: Update Jetson TX1 GPU regulator timings Date: Thu, 20 Jun 2019 09:17:01 +0100 Message-ID: <20190620081702.17209-3-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190620081702.17209-1-jonathanh@nvidia.com> References: <20190620081702.17209-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561018699; bh=pWavaGbgye2Pi/FLNO2W87uDt3CkK2tN/NQb369yLbI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JZIyrluGqOYojjp+ukpvJS6N8MYunZyJVS8tBdjtdvQEY/9aapRJtiAHMQCG8sPl9 Xxwh5zXENvpIoy+2gRsZhMlgxVNxInFwcqiQwdF/Mn35zlnlN3d62PpAyCT6hzuKKM /kv9LOb6Yrrt1Bmvox1azyZkO+zfH4JU6bqB8lxeA53q8veT3GynRSisTVxdcyk6EW BzPMsN5dWin4yXsO3YmdlYEyrDIyHuLRY3cPlIxDnKmqKztTQylOOD1d0p27ahvVRg 3T+1P3V7/qCC0zRWvtLJoUlWxLd0wIqnd0J9ofevS+cCs7/YM9FBsPM/dQcEJWmqgq GoOulxpYJQ4Lg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The GPU regulator enable ramp delay for Jetson TX1 is set to 1ms which not sufficient because the enable ramp delay has been measured to be greater than 1ms. Furthermore, the downstream kernels released by NVIDIA for Jetson TX1 are using a enable ramp delay 2ms and a settling delay of 160us. Update the GPU regulator enable ramp delay for Jetson TX1 to be 2ms and add a settling delay of 160us. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index e8654061ce03..27723829d033 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -341,7 +341,8 @@ regulator-max-microvolt = <1320000>; enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <1000>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; }; }; }; From patchwork Thu Jun 20 08:17:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1119246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="dO+pB5Vr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45TvpQ3N4Qz9s3l for ; Thu, 20 Jun 2019 18:18:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731080AbfFTISV (ORCPT ); Thu, 20 Jun 2019 04:18:21 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11525 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725877AbfFTISV (ORCPT ); Thu, 20 Jun 2019 04:18:21 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 20 Jun 2019 01:18:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 20 Jun 2019 01:18:20 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 20 Jun 2019 01:18:20 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 20 Jun 2019 08:18:19 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 20 Jun 2019 08:18:19 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.148]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 20 Jun 2019 01:18:19 -0700 From: Jon Hunter To: Thierry Reding , Rob Herring , Mark Rutland CC: , , Jon Hunter , Subject: [PATCH 3/3] arm64: tegra: Fix Jetson Nano GPU regulator Date: Thu, 20 Jun 2019 09:17:02 +0100 Message-ID: <20190620081702.17209-4-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190620081702.17209-1-jonathanh@nvidia.com> References: <20190620081702.17209-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561018699; bh=4BwHSOEWA4xYe11LAIREqHwR6axdZ3eGywYYy70TgW8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dO+pB5Vrs3cuDGLZqJ7Ruu7nqJsI3Dj87xL3W4JQ/bejWWxHemt12lK/Jnd41uihN T1cDI5B6OzTT63Zbl125ecsHEXI6k9vKJRaclNzkRJRNdxUZCqwldoOzqeR8MBhRNc FFDCRxvS3Uv0cKoXvSufbZRTgCjyQ9lUDSzPfg4y40odu7iCOw4dM0iadYnyuqUSp7 JNPHqE2WK26kMscAsCgPWDWkFYvlVonNijQVAGKBf08TWF1psufYwfkslC2A0qQ6ps Dh0VjQw/iag/Hx7ZUeGaECr9IRaKudQZTj6JsZ9+RsH3Q4qEtdeRGQjoZVKUmqM5Av sE8OqSKZS1BwQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org There are a few issues with the GPU regulator defined for Jetson Nano which are: 1. The GPU regulator is a PWM based regulator and not a fixed voltage regulator. 2. The output voltages for the GPU regulator are not correct. 3. The regulator enable ramp delay is too short for the regulator and needs to be increased. 2ms should be sufficient. 4. This is the same regulator used on Jetson TX1 and so make the ramp delay and settling time the same as Jetson TX1. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter --- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 63df72eecf21..9d17ec707bce 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -88,6 +88,10 @@ status = "okay"; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c500 { status = "okay"; clock-frequency = <100000>; @@ -664,17 +668,16 @@ }; vdd_gpu: regulator@6 { - compatible = "regulator-fixed"; + compatible = "pwm-regulator"; reg = <6>; - + pwms = <&pwm 1 4880>; regulator-name = "VDD_GPU"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-enable-ramp-delay = <250>; - - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1320000>; + regulator-ramp-delay = <80>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; + enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; vin-supply = <&vdd_5v0_sys>; }; };